- 17 Jan, 2023 11 commits
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Wenjing Liu authored
Tested-by:
Daniel Wheeler <Daniel.Wheeler@amd.com> Reviewed-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
Wenjing Liu <wenjing.liu@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Wenjing Liu authored
Tested-by:
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Wenjing Liu authored
[why] Extract dp link training logic out to their own files. link_dp_training - high level training sequence and helper functions. link_dp_training_8b_10b - dp1.x training link_dp_training_auxless - aux-less training link_dp_traininig_dpia - dpia training link_dp_training_fixed_vs_pe_retimer - fixed vs pe retimer training link_dp_training_128b_132b - dp2.1 training Tested-by:
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Saaem Rizvi authored
Current implementation of SubVP does not support cases where stream timing matched neither the destination rect nor the source rect. Will need to further debug to see how we can support these cases. Tested-by:
Alvin Lee <Alvin.Lee2@amd.com> Acked-by:
Saaem Rizvi <SyedSaaem.Rizvi@amd.com> Signed-off-by:
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Bhawanpreet Lakha authored
[why] HDCP 1.4 failed on SL8800 SW w/a test driver use. [how] slower down the HW i2c speed when used by HW i2c. Tested-by:
Aurabindo Pillai <Aurabindo.Pillai@amd.com> Reviewed-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by:
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Dillon Varone authored
Remove array size on array passed to CalculateDETSwathFillLatencyHiding. Tested-by:
Dillon Varone <Dillon.Varone@amd.com> Signed-off-by:
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Dillon Varone authored
MALL SS and Subvp use the same calculations for determining the size of the required allocation for a given surface, which is already done in DML. Add an interface to extract this information from VBA variables and use in their respective helper functions. Also refactor existing code to remove stale workarounds. Tested-by:
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Dillon Varone authored
DML does not explicitly consider support for space in MALL required for subvp phantom pipes. This adds a check to make sure portion of phantom surface can fit in MALL. Tested-by:
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Dillon Varone authored
DML incorrectly uses surface width for determining DCC meta size in MALL allocation calculations. Meta pitch should be used instead. Tested-by:
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Dillon Varone authored
Two issues existed: 1) Configs that support DRR, but have it disabled will fail subvp+vblank validation incorrectly. Use subvp+vblank path for this case. 2) Configs that support DRR and have it enabled can use higher voltage level than required if they also support subvp+vblank. Use lowest supported voltage level for this case. Tested-by:
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Dan Carpenter authored
This tab was deleted accidentally and triggers a Smatch warning: drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c:1006 gfx_v8_0_init_microcode() warn: inconsistent indenting Add it back. Fixes: 0aaafb73 ("drm/amd: Use `amdgpu_ucode_*` helpers for GFX8") Signed-off-by:Dan Carpenter <error27@gmail.com> Signed-off-by:
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- 13 Jan, 2023 21 commits
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Charlene Liu authored
Required by display init, also update get_dig_mode Tested-by:
Hansen Dsouza <hansen.dsouza@amd.com> Reviewed-by:
Duncan Ma <duncan.ma@amd.com> Acked-by:
Charlene Liu <Charlene.Liu@amd.com> Signed-off-by:
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Mustapha Ghaddar authored
[WHY] Last PR missed name of a struct to match in DMUB [HOW] Update the logic in dmub_cmh.h header Tested-by:
Meenakshikumar Somasundaram <Meenakshikumar.Somasundaram@amd.com> Acked-by:
Mustapha Ghaddar <mghaddar@amd.com> Signed-off-by:
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Yifan Zha authored
[Why] SDMA0_CNTL and MMHUB system aperture related registers are blocked by L1 Policy. Therefore, they cannot be accessed by VF and loged in violation. [How] For MMHUB registers, they will be programmed by PF. So VF will skip to program them in mmhubv3_0. For SDMA0_CNTL which is a PF_only register, VF don't need to program it in sdma_v6_0. Signed-off-by:
Yifan Zha <Yifan.Zha@amd.com> Acked-by:
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Candice Li authored
Support RAS fatal error mode1 reset on smu v13_0_0 and v13_0_10. Signed-off-by:
Candice Li <candice.li@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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jie1zhan authored
From smu firmware,the value of power is transferred in units of watts. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2321 Fixes: 137aac26 ("drm/amdgpu/smu12: fix power reporting on renoir") Acked-by:
Jesse Zhang <Jesse.Zhang@amd.com> Reviewed-by:
Aaron Liu <aaron.liu@amd.com> Signed-off-by:
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Mario Limonciello authored
Some dead code was introduced as part of utilizing the `amdgpu_ucode_*` helpers. Adjust the control flow to make sure that firmware is released in the appropriate error flows. Reported-by:
coverity-bot <keescook+coverity-bot@chromium.org> Addresses-Coverity-ID: 1530548 ("Control flow issues") Fixes: ec787deb ("drm/amd: Use `amdgpu_ucode_*` helpers for GFX9") Signed-off-by:
Mario Limonciello <mario.limonciello@amd.com> Reviewed-by:
Kees Cook <keescook@chromium.org> Reviewed-by:
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Wenjing Liu authored
Tested-by:
George Shen <George.Shen@amd.com> Acked-by:
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Wenjing Liu authored
[why] Moving dpcd logic from dc_link_dpcd to link_dpcd as part of link file restructure Tested-by:
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Wenjing Liu authored
[why] 1. Move dd_link_ddc functions to link_ddc. 2. Move link ddc functions declaration exposed in dc to link.h 3. Move link ddc functions declaration exposed in dm to dc_link.h 4. Remove i2caux_interface.h file Tested-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Wenjing Liu authored
[why] Factor out hpd handling logic from generic dc link file. Tested-by:
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Dillon Varone authored
[WHY?] FIFO enable sequence is incomplete as it is currently implemented in FW, and requires reset to prevent the FIFO to be enabled in an invalid state. This cannot be done until DIG FE is connected to the BE. [HOW?] Add FIFO enable sequence in driver for dcn32 with reset after DIG FE is connected to BE. Tested-by:
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Cruise Hung authored
[Why] The DPIA link encoder (DIG) was not released when a Display XDR 6K monitor was disconnected. That's because the DPIA link encoder logic checked the BW when it removed the link encoder for it. And the timing BW was less than DP link BW. So, it failed to release the link encoder. And that caused the DIG was occupied and can't be used. The reason it checked the BW is it wants to identify whether this link was using DIG or HPO. It skips if it's not DIG. [How] Not to check the BW when it removes the link encoder because it's already in the assignment table, it must be the DIG. Tested-by:
Cruise Hung <Cruise.Hung@amd.com> Signed-off-by:
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Dmytro Laktyushkin authored
A previous fix attempted to correct mismatch between DM display targets and dc panel instancing by only counting connected panels. This behaviour breaks a feature, thus this is an alternative solution that allows mapping display targets to dc links during mod_power_create. Tested-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Signed-off-by:
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Martin Leung authored
This reverts commit 1b5d0e7e. It caused corruption in some media players. Tested-by:
Aric Cyr <Aric.Cyr@amd.com> Reviewed-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Acked-by:
Martin Leung <Martin.Leung@amd.com> Signed-off-by:
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Mustapha Ghaddar authored
[WHY] After introducing new DPIA NOTIFICATION we will need to update the exiting BW allocation logic [HOW] Updated the BW alloc source and header files Tested-by:
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Konstantin Meskhidze authored
This commit fixes memory leakage in dc_construct_ctx() function. Signed-off-by:
Konstantin Meskhidze <konstantin.meskhidze@huawei.com> Signed-off-by:
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Deepak R Varma authored
A logical evaluation already results in bool. There is no need for using a ternary operator based evaluation and bool conversion of the outcome. Issue identified using boolconv.cocci Coccinelle semantic patch. This was also reported by the Kernel Test Robot. Hence Fixes: 473683a0 ("drm/amd/display: Create a file dedicated for CRTC") Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
Deepak R Varma <drv@mailo.com> Signed-off-by:
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Jiapeng Chong authored
The assignment of the else and if branches is the same, so the if else here is redundant, so we remove it. ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:1951:2-4: WARNING: possible condition with no effect (if == else). Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=3719Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Signed-off-by:
Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by:
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Mario Limonciello authored
On DCN314 when resuming from s0i3 an ASSERT is shown indicating that `VBIOSSMC_MSG_SetHardMinDcfclkByFreq` returned `VBIOSSMC_Result_Failed`. This isn't a driver bug; it's a BIOS/configuration bug. To make this easier to triage, add an explicit warning when this issue happens. This matches the behavior utilized for failures with `VBIOSSMC_MSG_TransferTableDram2Smu` configuration. Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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hongao authored
[Why] Setting scaling does not correctly update CRTC state. As a result dc stream state's src (composition area) && dest (addressable area) was not calculated as expected. This causes set scaling doesn's work. [How] Correctly update CRTC state when setting scaling property. Reviewed-by:
hongao <hongao@uniontech.com> Signed-off-by:
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Hamza Mahfooz authored
It is possible that adev->dm.dc->caps.max_links is greater than AMDGPU_MAX_CRTCS. So, to not potentially access unallocated memory use adev->mode_info.num_crtc to do the bounds check instead of adev->dm.dc->caps.max_links. Fixes: 1b11ff76 ("drm/amd/display: Implement multiple secure display") Fixes: b8ff7e08 ("drm/amd/display: Fix when disabling secure_display") Reviewed-by:
Alan Liu <HaoPing.Liu@amd.com> Signed-off-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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- 11 Jan, 2023 2 commits
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Philip Yang authored
Use page aligned size to reserve memory usage because page aligned TTM BO size is used to unreserve memory usage, otherwise no page aligned size causes memory usage accounting unbalanced. Change vram_used definition type to int64_t to be able to trigger WARN_ONCE(adev && adev->kfd.vram_used < 0, "..."), to help debug the accounting issue with warning and backtrace. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Philip Yang authored
If acquire_vm failed when initializing KFD vm, set vm->process_info to NULL and free process info, otherwise, the future acquire_vm will always fail as vm->process_info is not NULL. Pass avm as parameter to remove the duplicate code. Signed-off-by:
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- 10 Jan, 2023 6 commits
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Eric Huang authored
The point bo->kfd_bo is NULL for queue's write pointer BO when creating queue on mGPU. To avoid using the pointer fixes the error. Signed-off-by:
Eric Huang <jinhuieric.huang@amd.com> Reviewed-by:
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Deepak R Varma authored
kfree() & vfree() internally performs NULL check on the pointer handed to it and take no action if it indeed is NULL. Hence there is no need for a pre-check of the memory pointer before handing it to kfree()/vfree(). Issue reported by ifnullfree.cocci Coccinelle semantic patch script. Reviewed-by:
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Guchun Chen authored
This leverages the logic in smu11. No need to talk to SMU to check BACO enablement as it's in BACO state already. Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
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Eric Huang authored
There will be data corruption on vram allocated by svm if the initialization is not complete and application is writting on the memory. Adding sync to wait for the initialization completion is to resolve this issue. Signed-off-by:
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Deepak R Varma authored
Use the resource_size() function instead of a open coded computation resource size. It makes the code more readable. Issue identified using resource_size.cocci coccinelle semantic patch. Signed-off-by:
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YiPeng Chai authored
Fixed bug on error when unloading amdgpu. The error message is as follows: [ 377.706202] kernel BUG at drivers/gpu/drm/drm_buddy.c:278! [ 377.706215] invalid opcode: 0000 [#1] PREEMPT SMP NOPTI [ 377.706222] CPU: 4 PID: 8610 Comm: modprobe Tainted: G IOE 6.0.0-thomas #1 [ 377.706231] Hardware name: ASUS System Product Name/PRIME Z390-A, BIOS 2004 11/02/2021 [ 377.706238] RIP: 0010:drm_buddy_free_block+0x26/0x30 [drm_buddy] [ 377.706264] Code: 00 00 00 90 0f 1f 44 00 00 48 8b 0e 89 c8 25 00 0c 00 00 3d 00 04 00 00 75 10 48 8b 47 18 48 d3 e0 48 01 47 28 e9 fa fe ff ff <0f> 0b 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 41 54 55 48 89 f5 53 [ 377.706282] RSP: 0018:ffffad2dc4683cb8 EFLAGS: 00010287 [ 377.706289] RAX: 0000000000000000 RBX: ffff8b1743bd5138 RCX: 0000000000000000 [ 377.706297] RDX: ffff8b1743bd5160 RSI: ffff8b1743bd5c78 RDI: ffff8b16d1b25f70 [ 377.706304] RBP: ffff8b1743bd59e0 R08: 0000000000000001 R09: 0000000000000001 [ 377.706311] R10: ffff8b16c8572400 R11: ffffad2dc4683cf0 R12: ffff8b16d1b25f70 [ 377.706318] R13: ffff8b16d1b25fd0 R14: ffff8b1743bd59c0 R15: ffff8b16d1b25f70 [ 377.706325] FS: 00007fec56c72c40(0000) GS:ffff8b1836500000(0000) knlGS:0000000000000000 [ 377.706334] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 377.706340] CR2: 00007f9b88c1ba50 CR3: 0000000110450004 CR4: 00000000003706e0 [ 377.706347] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 377.706354] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 [ 377.706361] Call Trace: [ 377.706365] <TASK> [ 377.706369] drm_buddy_free_list+0x2a/0x60 [drm_buddy] [ 377.706376] amdgpu_vram_mgr_fini+0xea/0x180 [amdgpu] [ 377.706572] amdgpu_ttm_fini+0x12e/0x1a0 [amdgpu] [ 377.706650] amdgpu_bo_fini+0x22/0x90 [amdgpu] [ 377.706727] gmc_v11_0_sw_fini+0x26/0x30 [amdgpu] [ 377.706821] amdgpu_device_fini_sw+0xa1/0x3c0 [amdgpu] [ 377.706897] amdgpu_driver_release_kms+0x12/0x30 [amdgpu] [ 377.706975] drm_dev_release+0x20/0x40 [drm] [ 377.707006] release_nodes+0x35/0xb0 [ 377.707014] devres_release_all+0x8b/0xc0 [ 377.707020] device_unbind_cleanup+0xe/0x70 [ 377.707027] device_release_driver_internal+0xee/0x160 [ 377.707033] driver_detach+0x44/0x90 [ 377.707039] bus_remove_driver+0x55/0xe0 [ 377.707045] pci_unregister_driver+0x3b/0x90 [ 377.707052] amdgpu_exit+0x11/0x6c [amdgpu] [ 377.707194] __x64_sys_delete_module+0x142/0x2b0 [ 377.707201] ? fpregs_assert_state_consistent+0x22/0x50 [ 377.707208] ? exit_to_user_mode_prepare+0x3e/0x190 [ 377.707215] do_syscall_64+0x38/0x90 [ 377.707221] entry_SYSCALL_64_after_hwframe+0x63/0xcd Signed-off-by:
YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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