- 15 Sep, 2021 27 commits
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Jonathan Lemon authored
This patch describes the sysfs interface implemented by the ptp_ocp driver, under /sys/class/timecard. Signed-off-by:
Jonathan Lemon <jonathan.lemon@gmail.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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Jonathan Lemon authored
The following process is used to read the PHC clock and correlate the reading with the "correct" system time. - get starting timestamp - issue PCI write command - issue PCI read command - get ending timestamp - read latched sec/nsec registers The write command is posted to PCI bus and returns. When the write arrives at the FPGA, the PHC time is latched into the sec/nsec registers, and a flag is set indicating the registers are valid. The read command returns this flag, and the time retrieval proceeds. Below is a non-scaled picture of the timing diagram involved. The PHC time corresponds to some SYS time between [start, end]. Userspace usually uses the midpoint between [start, end] to estimate the PCI delay and match this with the PHC time. [start] | | write |-------+ | | \ | read |----+ +----->| | \ * PHC time latched into register | \ | midpoint | +------->| | | | | | +----| | / | |<--------+ | [end] | | As the diagram indicates, the PHC time is latched before the midpoint, so the system clock time is slightly off the real PHC time. This shows up as a phase error with an oscilliscope. The workaround here is to provide a tunable which reduces (shrinks) the end time in the above diagram. This in turn moves the calculated midpoint so the system time and PHC time are in agreemment. Currently, the adjustment reduces the end time by 3/16th of the entire window. E.g.: [start, end] ==> [start, (end - (3/16 * end)], which produces reasonably good results. Also reduce delays by just writing to the clock control register instead of performing a read/modify/write sequence, as the contents of the control register are known. Signed-off-by: -
Jonathan Lemon authored
The current implementation of adjtime uses gettime/settime to perform nanosecond adjustments. This introduces addtional phase errors due to delays. Instead, use the FPGA's ability to just apply the nanosecond adjustment to the clock directly. Signed-off-by:
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Jonathan Lemon authored
A 4th timestamper is added which timestamps the output of the PHC. The clock nanosecond offset is not always zero, so when compared to other timestampers, this provides precise measurements. Also, the timestamper interrupt from the PHC can be used to generate a PPS signal for /dev/pps. Also allow PTP_CLK_REQ_PEROUT requests for a 1PPS output, but do not actually configure any output pins, this is done via sysfs. Signed-off-by:
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Jonathan Lemon authored
Upcoming boards may have a second GNSS receiver, getting information from a different constellation than the first receiver, which provides some measure of anti-spoofing. Expose the sysfs attribute for this device, if detected. Signed-off-by:
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Jonathan Lemon authored
The timecard can provide a NMEA-1083 ZDA (time and date) output string on a serial port, which can be used to drive other devices. Add the NMEA resources, and the serial port as a sysfs attribute. Signed-off-by:
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Jonathan Lemon authored
Provide a view into the timecard internals for debugging. Signed-off-by:
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Jonathan Lemon authored
On startup, parts of the FPGA need to be initialized - break these out into their own functions, separate from the purely informational blocks. On startup, distrbute the UTC:TAI offset from the NMEA GNSS parser, if it is available. Signed-off-by:
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Jonathan Lemon authored
IRIG and DCF output time in UTC, but the timecard operates on TAI internally. Add an attribute node which allows adding an offset to these modes before output. Signed-off-by:
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Jonathan Lemon authored
IRIG-B has several different output formats, the timecard defaults to using B007. Add a control which selects different output modes. Signed-off-by:
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Jonathan Lemon authored
IRIG (Inter-range Instrumentation Group) timecode format on one of the SMA output channels is provided by the IRIG master FPGA block. Enable the master when the IRIG output format is selected on either one of the output channels. By default, the output is in B007 format. DCF output format is provided by the DCF master block. Also enable the IRIG and DCF slaves, which parse an incoming signal from the external SMA connectors, and may be used to adjust the PHC. Signed-off-by:
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Jonathan Lemon authored
The latest firmware for the TimeCard adds selectable signals for the SMA input/outputs. Add support for SMA selectors, and the GPIO controls needed for steering signals. Signed-off-by:
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Jonathan Lemon authored
The firmware may provide a third signal timestamper, so make it available for use. Signed-off-by:
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Jonathan Lemon authored
If a resource could not be registered, report the name of the resource and the error code. Signed-off-by:
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Jonathan Lemon authored
The TimeCard exposes different resources, which may have their own irqs. Space for the irqs is allocated through a MSI or MSI-X interrupt vector. On some platforms, the interrupt allocation fails. Rather than making this fatal, just skip exposing those resources. The main timecard functionality (that of a PTP clock) will work without the additional resources. Signed-off-by:
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Jonathan Lemon authored
If an I2C controller isn't present, don't try and read the I2C flash. Signed-off-by:
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Jonathan Lemon authored
Only display the TOD information if there is a corresponding TOD resource. Signed-off-by:
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Jonathan Lemon authored
Move the xilinx i2c driver parameters to the resource block instead of hardcoding things in the registration functions. Signed-off-by:
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Aleksander Jan Bajkowski authored
The new added properties are used for configuring burst length. Signed-off-by:
Aleksander Jan Bajkowski <olek2@wp.pl> Signed-off-by:
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Aleksander Jan Bajkowski authored
Document the Lantiq Xway SoC series External Bus Unit (ETOP) bindings. Signed-off-by:
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Aleksander Jan Bajkowski authored
Convert the Lantiq PMAC Device Tree binding documentation to json-schema. Signed-off-by:
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Aleksander Jan Bajkowski authored
Configure the burst length in Ethernet drivers. This improves Ethernet performance by 58%. According to the vendor BSP, 8W burst length is supported by ar9 and newer SoCs. The NAT benchmark results on xRX200 (Down/Up): * 2W: 330 Mb/s * 4W: 432 Mb/s 372 Mb/s * 8W: 520 Mb/s 389 Mb/s Tested on xRX200 and xRX330. Signed-off-by:
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Aleksander Jan Bajkowski authored
Make the burst length configurable by the drivers. Signed-off-by:
Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by:
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Aleksander Jan Bajkowski authored
The current definition of 2W burst length is invalid. This patch fixes it. Current downstream DEU driver doesn't use DMA. An incorrect burst length value doesn't cause any errors. This patch also adds other burst length values. Fixes: dfec1a82 ("MIPS: Lantiq: Add DMA support") Signed-off-by:
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Aleksander Jan Bajkowski authored
Different SoCs have a different number of channels, e.g .: * amazon-se has 10 channels, * danube+ar9 have 20 channels, * vr9 has 28 channels, * ar10 has 24 channels. We can read the ID register and, depending on the reported number of channels, reset the appropriate number of channels. Signed-off-by:
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Aleksander Jan Bajkowski authored
Reading the DMA registers immediately after the reset causes Data Bus Error. Adding a small delay fixes this issue. Signed-off-by:
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Linus Walleij authored
This drops the code setting bit 9 on egress frames on the Realtek "type A" (RTL8366RB) frames. This bit was set on ingress frames for unknown reason, and was set on egress frames as the format of ingress and egress frames was believed to be the same. As that assumption turned out to be false, and since this bit seems to have zero effect on the behaviour of the switch let's drop this bit entirely. Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Reviewed-by:
Andrew Lunn <andrew@lunn.ch> Reviewed-by:
Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20210913143156.1264570-1-linus.walleij@linaro.orgSigned-off-by:
Jakub Kicinski <kuba@kernel.org>
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- 14 Sep, 2021 13 commits
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David S. Miller authored
Guangbin Huang says: ==================== PF support get MAC address space assigned by firmware This series add support PF to get unicast/multicast MAC address space assigned by firmware for the HNS3 ethernet driver. ==================== Signed-off-by: -
Guangbin Huang authored
The new firmware supports to divides the whole multicast MAC address space equally to functions of all PFs, and calculates the space size of each PF according to its function number. To support this feature, PF driver adds querying multicast MAC address space size from firmware and limits used number according to space size. Signed-off-by:
Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by:
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Guangbin Huang authored
Currently, there are two ways for PF to set the unicast MAC address space size: specified by config parameters in firmware or set to default value. That's mean if the config parameters in firmware is zero, driver will divide the whole unicast MAC address space equally to 8 PFs. However, in this case, the unicast MAC address space will be wasted a lot when the hardware actually has less then 8 PFs. And in the other hand, if one PF has much more VFs than other PFs, then each function of this PF will has much less address space than other PFs. In order to ameliorate the above two situations, introduce the third way of unicast MAC address space assignment: firmware divides the whole unicast MAC address space equally to functions of all PFs, and calculates the space size of each PF according to its function number. PF queries the space size by the querying device specification command when in initialization process. The third way assignment is lower priority than specified by config parameters, only if the config parameters is zero can be used, and if firmware does not support the third way assignment, then driver still divides the whole unicast MAC address space equally to 8 PFs. Signed-off-by:
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Ansuel Smith authored
Add support for qca8327 internal phy needed for correct init of the switch port. It does use the same qca8337 function and reg just with a different id. Signed-off-by:
Ansuel Smith <ansuelsmth@gmail.com> Tested-by:
Rosen Penev <rosenp@gmail.com> Tested-by:
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Yajun Deng authored
The __alloc_frag_align() is short, and only called by two functions, so inline page_frag_alloc_align() for reduce the overhead of calls. Reported-by:
kernel test robot <oliver.sang@intel.com> Signed-off-by:
Yajun Deng <yajun.deng@linux.dev> Signed-off-by:
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Heiner Kallweit authored
It shouldn't happen, but can happen that readable eeprom size is smaller than announced. Then we would be stuck in an endless loop here because after reaching the actual end reads return eeprom.len = 0. I faced this issue when making a mistake in driver development. Detect this scenario and return an error. Signed-off-by:
Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by:
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M Chetan Kumar authored
Removed "stdbool.h" inclusion in iosm_ipc_imem.h Fixes: 13bb8429 ("net: wwan: iosm: firmware flashing and coredump collection") Reported-by:
Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by:
M Chetan Kumar <m.chetan.kumar@linux.intel.com> Signed-off-by:
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Min Li authored
Also correct how initialize_dco_operating_mode is called Signed-off-by:
Min Li <min.li.xe@renesas.com> Signed-off-by:
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Min Li authored
So far we don't need to support new 5.2 functions but different register addresses Signed-off-by:
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Min Li authored
Not need since TCS firmware file will configure it properlly. Signed-off-by:
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Heiner Kallweit authored
This patch is a follow-up to beb401ec ("r8169: deprecate support for RTL_GIGA_MAC_VER_27") that came with 5.12. Nobody complained, so let's remove support for this chip version. Signed-off-by:
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David S. Miller authored
Guvenc Gulce says: ==================== net/smc: add EID support please apply the following patch series for smc to netdev's net-next tree. The series introduce the so called Enterprise ID support for smc protocol. Including the generic netlink based interface. ==================== Signed-off-by: -
Karsten Graul authored
With SMC-Dv2 users can configure if the static system EID should be used during CLC handshake, or if only user EIDs are allowed. Add generic netlink support to enable and disable the system EID, and to retrieve the system EID and its current enabled state. Signed-off-by:
Karsten Graul <kgraul@linux.ibm.com> Reviewed-by:
Guvenc Gulce <guvenc@linux.ibm.com> Signed-off-by:
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