- 20 Sep, 2023 1 commit
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Duncan Ma authored
[Why] Two issues fixed: 1. Currently, driver does not allow idle prior to PSR entry. Once PSR1+IPS is enabled, there is intermittent hang due to DCN access from IrqMgr during IPS2. 2. Driver is sending multiple commands to PMFW and dmcub to exit IPS even during IPS0. [How] 1. Set driver allow optimization prior to entering PSR mode with the condition for eDP display only. Unregister all interrupts before allowing driver idle and re-register interrupts when exiting from idle. This will prevent IrqMgr to access DCN during IPS2. 2. Block sending PMFW and dmcub exit low power state commands when driver is not in idle state. Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by:
Charlene Liu <charlene.liu@amd.com> Reviewed-by:
Jun Lei <jun.lei@amd.com> Reviewed-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by:
Duncan Ma <duncan.ma@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- 11 Sep, 2023 1 commit
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Austin Zheng authored
Why: vrr_active_fixed should also be checked when determining if DRR is in use How: Add check for vrr_active_fixed when allow_freesync and vrr_active_variable are also checked Reviewed-by:
Alvin Lee <alvin.lee2@amd.com> Acked-by:
Stylon Wang <stylon.wang@amd.com> Signed-off-by:
Austin Zheng <austin.zheng@amd.com> Tested-by:
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- 30 Aug, 2023 3 commits
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Qingqing Zhuo authored
[Why & How] Add DMUB handling for DCN35. Signed-off-by:
Harry Wentland <Harry.Wentland@amd.com> Signed-off-by:
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Samson Tam authored
[Why] ignore_msa_timing_param indicates FS is capable but not necessarily enabled [How] add check for either allow_freesync or vrr_active_variable to confirm FS is enabled Reviewed-by:
Wayne Lin <wayne.lin@amd.com> Signed-off-by:
Samson Tam <samson.tam@amd.com> Tested-by:
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Alvin Lee authored
[Description] SubVP needs to "calculate" the earliest in use META address by using the current primary / meta addresses, but this leads to a race condition where FW and driver can read/write the address at the same time and intermittently produce inconsistent address offsets. To mitigate this issue without locking (too slow), save each surface flip addr into scratch registers and use this to keep track of the earliest in use META addres. Reviewed-by:
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- 15 Aug, 2023 2 commits
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Wenjing Liu authored
[why] There is a lack of encapsulation of pipe connection representation in pipe context. This has caused many challenging bugs and coding errors with repeated logic to identify the same pipe type. [how] Formally define pipe types and provide getters to identify a pipe type and find a pipe based on specific requirements. Update existing logic in non dcn specific files and dcn32 and future versions to use the new accessors. Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Tested-by:
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Bhawanpreet Lakha authored
- Add checks for Cursor update and dirty rects (sending updates to dmub) - Add checks for dc_notify_vsync, and fbc and subvp Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by:
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- 07 Aug, 2023 1 commit
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Stylon Wang authored
[Why] DPIA traces from DMUB is not enabled by default, which is less convenient to debug DPIA related issues because we have to resort to other debug tools to enable DPIA trace. [How] Exposes interfaces to update trace mask from the DMUB GPINT commands. Also provides DC implementations to enable DPIA trace. Reviewed-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by:
Tom Chung <chiahsuan.chung@amd.com> Signed-off-by:
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- 18 Jul, 2023 1 commit
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Nicholas Kazlauskas authored
[Why] Workaround to avoid accessing DMCUB state too early if the emulator is in use - we don't support any of the features the caps are querying with emulation anyway. [How] Guard the query if emulation is in use. Reviewed-by:
Alan Liu <haoping.liu@amd.com> Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by:
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- 30 Jun, 2023 1 commit
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Mario Limonciello authored
A number of parade TCONs are causing system hangs when utilized with older DMUB firmware and PSR-SU. Some changes have been introduced into DMUB firmware to add resilience against these failures. Don't allow running PSR-SU unless on the newer firmware. Cc: stable@vger.kernel.org Cc: Sean Wang <sean.ns.wang@amd.com> Cc: Marc Rossi <Marc.Rossi@amd.com> Cc: Hamza Mahfooz <Hamza.Mahfooz@amd.com> Cc: Tsung-hua (Ryan) Lin <Tsung-hua.Lin@amd.com> Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2443 Signed-off-by:
Mario Limonciello <mario.limonciello@amd.com> Reviewed-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
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- 09 Jun, 2023 3 commits
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Cruise Hung authored
[Why] The DMUB diagnostic data was not printed out correctly. [How] Print the DMUB diagnostic data line by line. Reviewed-by:
Cruise Hung <cruise.hung@amd.com> Tested-by:
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Harshit Mogalapalli authored
We have a NULL check for 'dc_dmub_srv' in dc_dmub_srv_cmd_run_list() but we are dereferencing it before checking. Fix this moving the dereference next to NULL check. This issue is found with Smatch(static analysis tool). Fixes: e97cc04f ("drm/amd/display: refactor dmub commands into single function") Signed-off-by:
Harshit Mogalapalli <harshit.m.mogalapalli@oracle.com> Signed-off-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Tom Rix authored
gcc with W=1 reports drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dmub_srv.c: In function ‘dc_dmub_srv_optimized_init_done’: drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dmub_srv.c:184:26: error: variable ‘dmub’ set but not used [-Werror=unused-but-set-variable] 184 | struct dmub_srv *dmub; | ^~~~ The return status is never set. It looks like a call to dmub_srv_get_fw_boot_status is missing. Fixes: 499e4b1c ("drm/amd/display: add mechanism to skip DCN init") Signed-off-by:Tom Rix <trix@redhat.com> Signed-off-by:
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- 18 Apr, 2023 3 commits
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Eric Yang authored
[Why] If optimized init is done in FW. DCN init can be skipped in driver. This need to be communicated between driver and fw and maintain backwards compatibility. [How] Use DMUB scratch 0 bit 2 to indicate optimized init done in fw and use DMUB scatch 4 bit 0 to indicate drive supports the optimized flow so FW will perform it. Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Acked-by:
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Josip Pavic authored
[Why & How] If dmub command queuing fails due to the inbox being full, flush the inbox and resubmit the comamnd. This was previously the default behavior but was lost in a refactor. Reviewed-by:
Josip Pavic <Josip.Pavic@amd.com> Tested-by:
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Josip Pavic authored
[Why & How] Consolidate dmub access to a single interface. This makes it easier to add code in the future that needs to run every time a dmub command is requested (e.g. instrumentation, locking etc). Reviewed-by:
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- 11 Apr, 2023 1 commit
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Alvin Lee authored
[Description] - When determining FPO support, include FPO + VActive support - Support FPO + VActive if one display meets regular requirements for FPO and the second display is able to switch in VACTIVE with a given amount of margin Reviewed-by:
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- 31 Mar, 2023 2 commits
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Alvin Lee authored
[Description] Assign the correct info now that FW headers are promoted Acked-by:
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Alvin Lee authored
[Description] * Pass in pipe index for FPO cmd to DMCUB - This change will pass in the pipe index for each stream that is using FPO - This change is in preparation to enable FPO + VActive * Use per pipe P-State force for FPO - For FPO, instead of using max watermarks value for P-State disallow, use per pipe p-state force instead - This is in preparation to enable FPO + VActive Reviewed-by:
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- 07 Mar, 2023 2 commits
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Alvin Lee authored
[Description] - For pipe harvesting cases, the pipe index does not necessarily match up with the OTG instance, so pass index by OTG Instance instead - For pipe split cases pass HUBP instance, since the split index is only used for HUBP programming - Also check for OPP ID when accessing opp for pipe harvesting cases Reviewed-by:
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Harry Wentland authored
[Why & How] DC is littered with many DCN guards that are not needed. Drop them. Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by:
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- 28 Feb, 2023 1 commit
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Ayush Gupta authored
[Why] System restart observed while changing the display resolution to 8k with extended mode. Sytem restart was caused by a page fault. [How] When the driver populates subvp info it did it for both the pipes using vblank which caused an outof bounds array access causing the page fault. added checks to allow the top pipe only to fix this issue. Co-authored-by:
Ayush Gupta <ayush.gupta@amd.com> Reviewed-by:
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- 16 Feb, 2023 1 commit
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Arthur Grillo authored
Remove arguments present on kernel-doc that are not present on the function declaration and add the new ones if present. Signed-off-by:
Arthur Grillo <arthurgrillo@riseup.net> Signed-off-by:
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- 23 Nov, 2022 1 commit
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Alvin Lee authored
[Description] - Add margin for HUBP "jitter" for SubVp + DRR case - Also do a min transition even if MPO is added on a non SubVP pipe (i.e. added on DRR pipe for SubVP + DRR) Reviewed-by:
Brian Chang <Brian.Chang@amd.com> Signed-off-by:
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- 09 Nov, 2022 2 commits
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Alvin Lee authored
[Description] - Incorporate FW delays as port of max VTOTAL calculated for SubVP + DRR cases (since it is part of the microschedule). - Also add margin for the max VTOTAL possible for SubVP + DRR cases. - Due to rounding errors in FW (integer arithmetic), the microschedule calculation can get pushed to the next frame (incorrectly) in cases where we use the max VTOTAL possible to complete the MCLK switch. - When the rounding error occurs, we are only off by 1-2 lines, use 40us margin which is working consistently. Reviewed-by:
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Max Tseng authored
[Why] PSR-SU requires extra conditions while cursor update. Reviewed-by:
Robin Chen <robin.chen@amd.com> Acked-by:
Max Tseng <Max.Tseng@amd.com> Tested-by:
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- 27 Oct, 2022 1 commit
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Jiapeng Chong authored
No functional modification involved. drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dmub_srv.c:615: warning: expecting prototype for setup_subvp_dmub_command(). Prototype was for populate_subvp_cmd_pipe_info() instead. Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2587 Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Signed-off-by:
Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by:
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- 24 Oct, 2022 1 commit
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Rodrigo Siqueira authored
The dc_dmub_srv file has a lot of documentation associated with SubVP that could be converted to a kernel-doc. This commit just changes the comment style to a kernel-doc. Tested-by:
Mark Broadworth <mark.broadworth@amd.com> Reviewed-by:
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- 10 Oct, 2022 2 commits
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Alvin Lee authored
Watermark calculation was incorrect due to missing brackets. Fixes: 85f4bc0c ("drm/amd/display: Add SubVP required code") Tested-by:
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Max Tseng authored
Since different features would need to update cursor registers, However, they would use different approaches. To unify varied methods, this refactor is implemented the same update cursor info method for current varied features. Tested-by:
Anthony Koo <Anthony.Koo@amd.com> Reviewed-by:
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- 19 Sep, 2022 2 commits
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Alvin Lee authored
[Why & How] Uncomment SubVP pipe split assignment in driver since FW headers are now promoted Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Acked-by:
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Alvin Lee authored
[Why and How] For SubVP pipe split case, pass in split index for main and phantom pipes to ensure that the P-State sequence will force P-State for all required pipes. Reviewed-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Reviewed-by:
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- 13 Sep, 2022 2 commits
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Alvin Lee authored
Refactor calculation to remove floating point operations from dmub_srv. To ensure that 32-bit compilation works well, we use the div64 family of macros to do integer division for SubVP-related timing parameters. Cc: Maíra Canal <mairacanal@riseup.net> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Isabella Basso <isabbasso@riseup.net> Cc: Magali Lemes <magalilemes00@gmail.com> Tested-by:
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Alvin Lee authored
Refactor calculation to remove floating point operations from dmub_srv. To ensure that 32-bit compilation works well, we use the div64 family of macros to do integer division for SubVP-related timing parameters. Cc: Maíra Canal <mairacanal@riseup.net> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Isabella Basso <isabbasso@riseup.net> Cc: Magali Lemes <magalilemes00@gmail.com> Tested-by:
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- 29 Aug, 2022 3 commits
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Alvin Lee authored
[Description] For SubVP scaling case we have to combine the plane scaling and stream scaling. Use UCLK dummy p-state WM for FCLK WM set C [Description] For DCN32/321 program dummy UCLK P-state watermark into FCLK watermark set C register. Reviewed-by:
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Leo (Hanghong) Ma authored
[Why] We want to get the visual confirm color of the bottom-most pipe for test automation. [How] Save the visual confirm color to plane_state before program to MPC; Reviewed-by:
Leo (Hanghong) Ma <hanghong.ma@amd.com> Tested-by:
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sunliming authored
Fixes the following smatch warning: drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dmub_srv.c:311 dc_dmub_srv_p_state_delegate() warn: variable dereferenced before check 'dc' (see line 309) Reported-by:
kernel test robot <lkp@intel.com> Reported-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
sunliming <sunliming@kylinos.cn> Signed-off-by:
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- 25 Aug, 2022 1 commit
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Alvin Lee authored
[Description] Uncomment scaling cmd assignment since FW headers are now promoted. Reviewed-by:
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- 16 Aug, 2022 1 commit
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Alvin Lee authored
[Description] For SubVP scaling cases, we must include the scaling info as part of the cmd. This is required when converting OTG line to HUBP line for the MALL_START_LINE programming. Reviewed-by:
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- 10 Aug, 2022 1 commit
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Alvin Lee authored
[Description] SUBVP_START_LINE must be aligned to 2 swaths, so add 16 lines of margin so the start line can be adjusted by up to 16 lines for alignment purposes in FW. Reviewed-by:
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