1. 23 Jun, 2021 36 commits
  2. 10 Jun, 2021 1 commit
    • Stephen Boyd's avatar
      drm/msm/dsi: Stash away calculated vco frequency on recalc · 170b7635
      Stephen Boyd authored
      A problem was reported on CoachZ devices where the display wouldn't come
      up, or it would be distorted. It turns out that the PLL code here wasn't
      getting called once dsi_pll_10nm_vco_recalc_rate() started returning the
      same exact frequency, down to the Hz, that the bootloader was setting
      instead of 0 when the clk was registered with the clk framework.
      
      After commit 001d8dc3 ("drm/msm/dsi: remove temp data from global
      pll structure") we use a hardcoded value for the parent clk frequency,
      i.e.  VCO_REF_CLK_RATE, and we also hardcode the value for FRAC_BITS,
      instead of getting it from the config structure. This combination of
      changes to the recalc function allows us to properly calculate the
      frequency of the PLL regardless of whether or not the PLL has been
      clk_prepare()d or clk_set_rate()d. That's a good improvement.
      
      Unfortunately, this means that now we won't call down into the PLL clk
      driver when we call clk_set_rate() because the frequency calculated in
      the framework matches the frequency that is set in hardware. If the rate
      is the same as what we want it should be OK to not call the set_rate PLL
      op. The real problem is that the prepare op in this driver uses a
      private struct member to stash away the vco frequency so that it can
      call the set_rate op directly during prepare. Once the set_rate op is
      never called because recalc_rate told us the rate is the same, we don't
      set this private struct member before the prepare op runs, so we try to
      call the set_rate function directly with a frequency of 0. This
      effectively kills the PLL and configures it for a rate that won't work.
      Calling set_rate from prepare is really quite bad and will confuse any
      downstream clks about what the rate actually is of their parent. Fixing
      that will be a rather large change though so we leave that to later.
      
      For now, let's stash away the rate we calculate during recalc so that
      the prepare op knows what frequency to set, instead of 0. This way
      things keep working and the display can enable the PLL properly. In the
      future, we should remove that code from the prepare op so that it
      doesn't even try to call the set rate function.
      
      Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
      Cc: Abhinav Kumar <abhinavk@codeaurora.org>
      Fixes: 001d8dc3 ("drm/msm/dsi: remove temp data from global pll structure")
      Signed-off-by: default avatarStephen Boyd <swboyd@chromium.org>
      Link: https://lore.kernel.org/r/20210608195519.125561-1-swboyd@chromium.orgSigned-off-by: default avatarRob Clark <robdclark@chromium.org>
      170b7635
  3. 08 Jun, 2021 3 commits