- 22 Jan, 2015 2 commits
-
-
Olof Johansson authored
Merge tag 'renesas-dt2-for-v3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt Merge "Second Round of Renesas ARM Based SoC DT Updates for v3.20" from Simon Horman: * Support Renesas memory controllers * Add SRC interrupt number on r8a779~ and r8a7791 SoCs * Fix MSTP8 input clocks on r8a7791 SoC * Add PM domain support to r8a7740 * Add DT bindings for the R-Mobile System Controller * Use Add sh73a0-specific FSI2 compatible property * tag 'renesas-dt2-for-v3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: PM / Domains: R-Mobile SYSC: Document SH-Mobile AG5 (sh73a0) binding ARM: shmobile: sh73a0 dtsi: Add memory-controller nodes ARM: shmobile: r8a7740 dtsi: Add memory-controller node ARM: shmobile: r8a73a4 dtsi: Add memory-controller nodes ARM: shmobile: Add DT bindings for Renesas memory controllers ARM: shmobile: r8a7791: add SRC interrupt number on DTSI ARM: shmobile: r8a7790: add SRC interrupt number on DTSI ARM: shmobile: r8a7791: fix MSTP8 input clocks ARM: shmobile: r8a7740 dtsi: Add PM domain support PM / Domains: Add DT bindings for the R-Mobile System Controller ARM: shmobile: sh73a0 dtsi: Add SoC-specific FSI2 compatible property Signed-off-by: Olof Johansson <olof@lixom.net>
-
Olof Johansson authored
Merge tag 'omap-for-v3.20/dt-pt1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt Merge "omap device tree changes for v3.20" from Tony Lindgren: Device tree changes for omaps. Mostly to add support for new am437x-idk and update am437x-sk boards. Also enabling new devices for multiple boards. * tag 'omap-for-v3.20/dt-pt1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (21 commits) ARM: dts: omap3-gta04: Add handling for tv output ARM: dts: cm-t3x: add NAND support ARM: dts: am57xx-beagle-x15: Add GPIO controlled fan node ARM: dts: am437x-idk: add gpio-based power key ARM: dts: N950/N9: add twl_power ARM: dts: am437x-sk: add power button binding ARM: dts: add support for AM437x IDK ARM: dts: am437x-gp-evm: add VPFE device tree data ARM: dts: am437x-sk-evm: add VPFE device tree data ARM: dts: am43x-epos-evm: add VPFE device tree data ARM: dts: am4372: add VPFE DT node entries ARM: dts: DRA7X: drop id property in pcie_phy ARM: dts: omap3-n900: cleanup english ARM: dts: am57xx-beagle-x15: Add dual ethernet ARM: dts: am437x-sk: remove DSS pulls ARM: dts: am437x-sk: remove internal i2c pullups ARM: dts: am437x-sk: add explicit pinmux for both USB instances ARM: dts: am437x-sk: remove ethernet pulls ARM: dts: am437x-sk: add explicit MMC0 pinmux ARM: dts: am437x-sk: remove internal pulls from QSPI ... Signed-off-by: Olof Johansson <olof@lixom.net>
-
- 21 Jan, 2015 2 commits
-
-
git://git.stlinux.com/devel/kernel/linux-stiOlof Johansson authored
Merge "STi DT updates for v3.20, round 1" from Maxime Coquelin: Highlights: ----------- - Add USB support for STiH410 & STiH407 - Add DRM DT nodes for STiH410 & STiH407 - Add STiH418 SoC support - Add DT nodes for MiPHY28lp PHY * tag 'sti-dt-for-v3.20-1' of git://git.stlinux.com/devel/kernel/linux-sti: ARM: DT: STi: STiH407: Add DT node for MiPHY28lp ARM: dts: STiH418: Add B2199 board support ARM: dts: Add STiH418 SoC support ARM: DT: STiH410: Add DRM dt nodes ARM: DT: STiH407: Add DRM dt nodes ARM: STi: DT: STiH410: Add DT nodes for the ehci and ohci usb controllers. ARM: STi: DT: STiH410: Add usb2 picophy dt nodes ARM: STi: DT: STiH407: Add usb2 picophy dt nodes Signed-off-by: Olof Johansson <olof@lixom.net>
-
Wang Long authored
Add dts file for Hisilicon hip01 ca9x2 board Signed-off-by: Wang Long <long.wanglong@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com> [olof: Folded in smp enable-method from a different patch] Signed-off-by: Olof Johansson <olof@lixom.net>
-
- 20 Jan, 2015 6 commits
-
-
Olof Johansson authored
Merge tag 'renesas-dt-cleanups2-for-v3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt Merge "Second Round of Renesas ARM Based SoC DT Cleanups for v3.20" from Simon Horman: Second Round of Renesas ARM Based SoC DT Cleanups for v3.20 * Tidy up #sound-dai-cells settings * Drop "renesas,rcar_sound" compatible value * tag 'renesas-dt-cleanups2-for-v3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: r8a7791: tidyup #sound-dai-cells settings ARM: shmobile: r8a7790: tidyup #sound-dai-cells settings ARM: shmobile: r8a7791 dtsi: Drop "renesas,rcar_sound" compatible value ARM: shmobile: r8a7790 dtsi: Drop "renesas,rcar_sound" compatible value Signed-off-by: Olof Johansson <olof@lixom.net>
-
Olof Johansson authored
The file is roughly sorted alphabetically (with some exceptions where old options have been split in two), so alphascale should go at the top instead of at the bottom. Also linewrap like other entries have been lately. Signed-off-by: Olof Johansson <olof@lixom.net>
-
Olof Johansson authored
* asm/dt: add Alphascale to vendor-prefixes.txt ARM: add alphascale,acc.txt bindings documentation ARM: dts: add DT for Alphascale ASM9260 SoC
-
Oleksij Rempel authored
this company already provided some products, so it make sense to add them to vendor-prefixes.txt list Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Olof Johansson <olof@lixom.net>
-
Oleksij Rempel authored
ACC is for AlphaScale Clock Controller. Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Signed-off-by: Olof Johansson <olof@lixom.net>
-
Oleksij Rempel authored
for now it is wary basic SoC description with most important IPs needed to make this device work Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Signed-off-by: Olof Johansson <olof@lixom.net>
-
- 19 Jan, 2015 2 commits
-
-
git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91Olof Johansson authored
Merge "at91: dt for 3.20 #1" from Nicolas Ferre: First batch of DT changes for 3.20: - little typo and a LED declared - addition of the Special Function Registers (SFR) + its binding - RTC & SRAM nodes - the at91sam9xe has its own .dtsi now. Not combined with at91sam9260 anymore - addition of the Image Sensor Interface (ISI) DT part and supported sensors * tag 'at91-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91: ARM: at91: dts: sama5d3: add ov2640 camera sensor support ARM: at91: dts: sama5d3: change name of pinctrl of ISI_MCK ARM: at91: dts: sama5d3: change name of pinctrl_isi_{power,reset} ARM: at91: dts: sama5d3: move the isi mck pin to mb ARM: at91: dts: sama5d3: add missing pins of isi ARM: at91: dts: sama5d3: split isi pinctrl ARM: at91: dts: sama5d3: add isi clock ARM: at91/dt: ethernut5: use at91sam9xe.dtsi ARM: at91/dt: Add a dtsi for at91sam9xe ARM: at91/dt: add SRAM nodes ARM: at91/dt: at91rm9200ek: enable RTC ARM: at91/dt: rm9200: add RTC node ARM: at91/dt: at91sam9n12: Add RTC node ARM: at91: sama5d4: Add SFR ARM: at91: sama5d3: Add SFR ARM: at91: Add Special Function Registers binding documentation ARM: at91/dt: sam9263: Fix typo: ac91_clk -> ac97_clk ARM: at91/dt: sama5d3: enable D2 as the heartbeat LED Signed-off-by: Olof Johansson <olof@lixom.net>
-
Olof Johansson authored
Merge tag 'atlas7-init-dts-for-3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/baohua/linux into next/dt Merge "CSR atlas7 init dts for 3.20" from Barry Song: Drop Marco and add init dts stuff for Atlas7 CSR Marco SoC has never shipped to customers that could be interested in mainline support. and new Atlas7 is a replacement SoC that is in development. So we drop Marco dts stuff, and add dts stuff for Atlas7. * tag 'atlas7-init-dts-for-3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/baohua/linux: ARM: dts: add init dts file for CSR atlas7 SoC ARM: dts: drop MARCO platform DT stuff Signed-off-by: Olof Johansson <olof@lixom.net>
-
- 16 Jan, 2015 6 commits
-
-
Gabriel FERNANDEZ authored
The MiPHY28lp is a Generic PHY which can serve various SATA, PCIe or USB3 devices. The two first ports can be use for either; both SATA, both PCIe or one of each in any configuration. The Third port is only for USB3. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
-
Maxime COQUELIN authored
B2199 HDK is the reference board for STiH418 SoC. It has the following characteristics: - 3GB DDR3 - 8GB eMMC / SD-Card slot - 32MB NOR Flash - 1 x Gbit Ethernet - 1 x USB3.0 port - 2 x USB2.0 ports - 1 x Sata or Mini-PCIe port - 1 x WiFi 802.11ac (Quantenna) - 1 x HDMI out - 1 x HDMI in - 1 x SPDIF Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
-
Maxime COQUELIN authored
The STiH418 is advanced UHD 60fps AVC processor with 3D graphic acceleration and quad-core ARM Cortex A9 CPU. Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
-
Gabriel FERNANDEZ authored
This patch adds the DRM/KMS dt nodes. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> Acked-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
-
Gabriel FERNANDEZ authored
This patch adds the DRM/KMS dt nodes. This node can't be in stih407-family.dtsi file because in the future we will integrate a new stih418-b2199 board. It's a stih407 family board with different drm/kms dt nodes. That is why i created the stih407.dtsi file. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> Acked-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
-
Geert Uytterhoeven authored
SH-Mobile AG5 (sh73a0) can be handled by the existing bindings. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
-
- 15 Jan, 2015 19 commits
-
-
Josh Wu authored
According to v4l2 dt document, we add: a camera host: ISI port. a i2c camera sensor: ov2640 port. to sama5d3xmb.dtsi. The ov2640 node defines the pinctrls, clocks and refer to isi port. The ISI node also has a reference to the ov2640 port. Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
-
Josh Wu authored
For sama5d3xmb board, the pins: pinctrl_isi_pck_as_mck is pck1, and used to provide MCK for camera sensor. We change its name to: pinctrl_pck1_as_isi_mck. As we want camera sensor instead of ISI to configure the pck1 (ISI_MCK) pin. So we remove this pinctrl from ISI DT node. It will be added in sensor's DT node. Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
-
Josh Wu authored
For sama5d3xmb board, the pins: pinctrl_isi_{power,reset} is used to power-down or reset camera sensor. So we should let camera sensor instead of ISI to configure the pins. This patch will change pinctrl name from pinctrl_isi_{power,reset} to pinctrl_sensor_{power,reset}. And remove these two pinctrl from ISI's DT node. We will add these two pinctrl to sensor's DT node. Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
-
Bo Shen authored
The mck is decided by the board design, move it to mb related dtsi file. Signed-off-by: Bo Shen <voice.shen@atmel.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
-
Bo Shen authored
The ISI has 12 data lines, add the missing two data lines. Signed-off-by: Bo Shen <voice.shen@atmel.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
-
Bo Shen authored
As the ISI has 12 data lines, however we only use 8 data lines with sensor module. So, split the data line into two groups which make it can be choosed depends on the hardware design. Signed-off-by: Bo Shen <voice.shen@atmel.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
-
Josh Wu authored
Add ISI peripheral clock in sama5d3.dtsi. Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
-
Alexandre Belloni authored
The ethernut5 is actually based on an at91sam9xe, use the correct dts include. Cc: Martin Reimann <martin.reimann@egnite.de> Cc: Tim Schendekehl <tim.schendekehl@egnite.de> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
-
Alexandre Belloni authored
at91sam9xe is slightly different from at91sam9260, in particular it has a different SRAM size and location. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
-
Alexandre Belloni authored
Add nodes for the SRAM available on atmel SoCs For the at91sam9260 and the at91sam9g20, address mirroring is used to create a single contiguous SRAM range instead of declaring two separate banks. Also remove leftover TODOs in the sam9g45 file Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> [nicolas.ferre@atmel.com: correct at91sam9rl sram size => 0x10000] Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
-
Alexandre Belloni authored
Enable the RTC on the at91rm9200ek. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
-
Alexandre Belloni authored
Add a node for the RTC available on at91rm9200. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
-
Alexandre Belloni authored
Add node for the RTC available on the at91sam9n12. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
-
Alexandre Belloni authored
The sama4d4 has Special Function Registers that allow to manage DDR, OHCI, EBI and AIC interrupt redirection. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> [nicolas.ferre@atmel.com: reg size: 0x60] Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
-
Alexandre Belloni authored
The sama5d3 has Special Function Registers that allow to manage OHCI, EBI and the UTMI clock. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> [nicolas.ferre@atmel.com: reg size: 0x60] Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
-
Alexandre Belloni authored
The special function registers gather some registers that allow to tweak features provided by IPs controlled through another register range. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> [nicolas.ferre@atmel.com: reg size: 0x60] Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
-
Alexander Stein authored
That clock should be called ac97_clk. Signed-off-by: Alexander Stein <alexanders83@web.de> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
-
Josh Wu authored
This D2 led is available for all sama5d3x-ek board. So make it a heartbeat LED. Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
-
git://git.infradead.org/linux-mvebuOlof Johansson authored
Merge "mvebu: dt for v3.20" from Andrew Lunn: mvebu dt changes for v3.20 (part #1) - Add Armada 388 General Purpose Development Board support - Add Device Tree description of the Armada 388 SoC - Document the Device Tree binding for the Armada 388 SoC - a38x: Add missing labels - a38x: Add more pinctrl functions - Add Armada 385 Access Point Development Board support - Add a number of pinctrl functions - A38x: Remove redundant pinctrl informations - a38x: Fix node names - Add support for Seagate BlackArmor NAS220 - kirkwood: enable phy driver for SATA controller on 88f6192 - gpio_poweroff support for Iomega ix2-200 - Use all remaining MTD space foor rootfs of Iomega ix2-200 * tag 'mvebu-dt-3.20' of git://git.infradead.org/linux-mvebu: ARM: mvebu: Add Armada 388 General Purpose Development Board support ARM: mvebu: Add Device Tree description of the Armada 388 SoC ARM: mvebu: Document the Device Tree binding for the Armada 388 SoC ARM: mvebu: a38x: Add missing labels ARM: mvebu: a38x: Add more pinctrl functions ARM: mvebu: Add Armada 385 Access Point Development Board support ARM: mvebu: Add a number of pinctrl functions ARM: mvebu: A38x: Remove redundant pinctrl informations ARM: mvebu: a38x: Fix node names Kirkwood: add support for Seagate BlackArmor NAS220 ARM: dts: kirkwood: enable phy driver for SATA controller on 88f6192 ARM: dts: add gpio_poweroff support for Iomega ix2-200 ARM: dts: use all remaining MTD space foor rootfs of Iomega ix2-200 Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Olof Johansson <olof@lixom.net>
-
- 14 Jan, 2015 3 commits
-
-
Geert Uytterhoeven authored
Add device nodes for the two SDRAM Bus State Controllers. The SBSCs are located in the A4BC0 resp. A4BC1 PM domains, which must not be powered down, else the system will crash. References to the A4BC0 and A4BC1 PM domains will be added later. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
-
Geert Uytterhoeven authored
Add a device node for the DDR3 Bus State Controller (DBSC3). The DBSC3 is located in the A4S PM domain, which must not be powered down, else the system will crash. This has no visible effect for now, as A4S was never turned off anyway because its child PM domain A3SM contains the CPU core. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
-
Geert Uytterhoeven authored
Add device nodes for the two DDR Bus State Controllers (DBSC). The DBSCs are located in the A3BC PM domain, which must not be powered down, else the system will crash. A reference to the A3BC PM domain will be added later. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
-