Add COMPILE_TEST support to the AT91 PIO4 pinctrl driver for better compile
testing coverage.
Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
Link: https://lore.kernel.org/r/1590234326-2194-2-git-send-email-yangtiezhu@loongson.cnSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

When call function devm_platform_ioremap_resource(), we should use IS_ERR()
to check the return value and return PTR_ERR() if failed.

Fixes: 4b024225 ("pinctrl: use devm_platform_ioremap_resource() to simplify code")
Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
Link: https://lore.kernel.org/r/1590234326-2194-1-git-send-email-yangtiezhu@loongson.cnSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Merge tag 'sh-pfc-for-v5.8-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: sh-pfc: Updates for v5.8 (take two)

  - Add support for the new RZ/G1H (r8a7742) SoC,
  - Minor fixes and improvements.

Change "PIN CONTROLLER - RENESAS" section from Maintained to Supported.
This brings it in line with my other "+renesas" entries.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20200518081836.23890-1-geert+renesas@glider.be

Merge tag 'samsung-pinctrl-5.8' of https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel

Samsung pinctrl drivers changes for v5.8

Two fixes for S5Pv210 pinctrl driver: setting proper external interrupt
wakeup mask and restoring external interrupt mask value after system
suspend.

This adds documentation for the "compatible" value designated for Sparx5
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Link: https://lore.kernel.org/r/20200513125532.24585-8-lars.povlsen@microchip.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

This fixes a problem with using the GPIO as an interrupt on Jaguar2
(and similar), as the register layout of the platforms with 64 GPIO's
are pairwise, such that the original offset must be multiplied with
the platform stride.

Fixes: da801ab5 pinctrl: ocelot: add MSCC Jaguar2 support.
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Link: https://lore.kernel.org/r/20200513125532.24585-4-lars.povlsen@microchip.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

This patch removes the instance number from the "miim", "reco_clk" and
"sfp" pin function.

The change needed is to prepare the driver for adding new platforms
with more of these instances. The instance number is also redundant,
as this is implicit for each pin.
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Link: https://lore.kernel.org/r/20200513125532.24585-3-lars.povlsen@microchip.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

This fixes the situation where the GPIO controller is not
used as an interrupt controller as well.

Previously, the driver would silently fail to register even the
GPIO's. With this change, the driver will only register as an
interrupt controller if a parent interrupt is provided.
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Link: https://lore.kernel.org/r/20200513125532.24585-2-lars.povlsen@microchip.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

The Rockchip dtsi and dts files have been bulk-converted for the
remaining raw gpio numbers into their descriptive counterparts and
also got rid of the unhelpful RK_FUNC_x -> x and RK_GPIOx -> x
mappings, so update the example as well.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20200512203524.7317-2-jbx6244@gmail.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Currently the AMD pin controller driver supports ACPI platform only.
Make the PINCTRL_AMD config symbol depend on ACPI, to avoid asking the
user about it when configuring a kernel without ACPI support.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20200507113751.24213-1-geert+renesas@glider.beSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

The Equilibrium pin controller is only present on Intel Lightning
Mountain SoCs.  Add an architecture dependency to the
PINCTRL_EQUILIBRIUM config symbol, to avoid asking the user about it
when configuring a kernel for a non-x86 architecture.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20200507113626.24026-2-geert+renesas@glider.beSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Merge tag 'intel-pinctrl-v5.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel

intel-pinctrl for v5.8-1

* Introduce GPIO driver for Jasper Lake
* Fix long standing bug in Sunrisepoint-H PAD locking code
* Enable pin configuration setting for GPIO chip for Baytrail
* Work around race condition in Cherriview hardware when handle IRQ
* Clean up Cherryview code to be closer to other drivers

The following is an automated git shortlog grouped by driver:

baytrail:
 -  Use platform_get_irq_optional() explicitly
 -  Enable pin configuration setting for GPIO chip

cannonlake:
 -  Use generic flag for special GPIO base treatment

cherryview:
 -  Add missing spinlock usage in chv_gpio_irq_handler
 -  Use GENMASK() consistently
 -  Re-use data structures from pinctrl-intel.h (part 2)

icelake:
 -  Use generic flag for special GPIO base treatment

intel:
 -  Move npins closer to pin_base in struct intel_community
 -  Update description in struct intel_community
 -  Add Intel Jasper Lake pin controller support
 -  Introduce new flag to force GPIO base to be 0
 -  Introduce common flags for GPIO mapping scheme

lynxpoint:
 -  Use platform_get_irq_optional() explicitly

sunrisepoint:
 -  Fix PAD lock register offset for SPT-H

tigerlake:
 -  Use generic flag for special GPIO base treatment

rza1_swio_pin relates to the swio flag instead of the bidir flag.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Link: https://lore.kernel.org/r/20200507074516.29903-1-geert+renesas@glider.be

Renesas RZ/G1H (R8A7742) is pin compatible with R-Car H2 (R8A7790),
however it doesn't have several automotive specific peripherals. Add
automotive-specific pin groups/functions along with common pin
groups/functions for supporting both r8a7790 and r8a7742 SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1588542414-14826-3-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Document PFC support for the RZ/G1H (R8A7742) SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1588542414-14826-2-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

In function rockchip_dt_node_to_map, a new_map variable is
allocated by:

new_map = devm_kcalloc(pctldev->dev, map_num, sizeof(*new_map),
		       GFP_KERNEL);

This uses devres and attaches new_map to the pinctrl driver.
This cause a leak since new_map is not released when the probed
driver is removed. Fix it by using kcalloc to allocate new_map
and free it in `rockchip_dt_free_map`
Signed-off-by: Dafna Hirschfeld <dafna.hirschfeld@collabora.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20200506100903.15420-1-dafna.hirschfeld@collabora.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

The function rockchip_pinctrl_parse_dt returns -EINVAL if
allocation fails. Change the return error to -ENOMEM
Signed-off-by: Dafna Hirschfeld <dafna.hirschfeld@collabora.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20200506101424.15691-1-dafna.hirschfeld@collabora.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Kbuild warns when this file is built as a loadable module:

WARNING: modpost: missing MODULE_LICENSE() in drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.o
see include/linux/module.h for more information

Add the missing license/author/description tags.

Fixes: 8174a851 ("pinctrl: mediatek: make MediaTek pinctrl v2 driver ready for buidling loadable module")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20200505140848.554957-1-arnd@arndb.deSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

These are called when a GPIO is to be used as IRQ.

Without these custom callbacks, when an interrupt is requested directly
and not through gpiod_to_irq(), the request fails because the GPIO is
not necesarily in input mode. These callbacks simply enforce that the
requested GPIO is in input mode.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20200503164549.163884-1-paul@crapouillou.netSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Mark pin_cfg as const, allowing the compiler to put the struct in
.rodata instead of .data.
Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com>
Link: https://lore.kernel.org/r/20200425203813.6442-1-rikard.falkeborn@gmail.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Merge tag 'sh-pfc-for-v5.8-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: sh-pfc: Updates for v5.8

  - Fix SWIO pins on RZ/A1L,
  - Add missing bindings to MAINTAINERS.

The Hulk robot reports these build warnings:

drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c:899:20: warning:
‘sbag_groups’ defined but not used [-Wunused-const-variable=]
 DB8500_FUNC_GROUPS(sbag, "sbag_oc2_1", "sbag_oc4_1");
                    ^
drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c:570:23: warning:
‘ipgpio6_c_2_pins’ defined but not used [-Wunused-const-variable=]
 static const unsigned ipgpio6_c_2_pins[] = { DB8500_PIN_G3 };
                       ^~~~~~~~~~~~~~~~
drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c:472:23: warning:
‘mc1dir_a_1_pins’ defined but not used [-Wunused-const-variable=]
 static const unsigned mc1dir_a_1_pins[] = { DB8500_PIN_AH13,
DB8500_PIN_AG12,
                       ^~~~~~~~~~~~~~~
drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c:453:23: warning:
‘modem_a_1_pins’ defined but not used [-Wunused-const-variable=]
 static const unsigned modem_a_1_pins[] = { DB8500_PIN_D22,
DB8500_PIN_C23,
                       ^~~~~~~~~~~~~~
drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c:430:23: warning:
‘kpskaskb_a_1_pins’ defined but not used [-Wunused-const-variable=]
 static const unsigned kpskaskb_a_1_pins[] = { DB8500_PIN_D17,
DB8500_PIN_D16 };
                       ^~~~~~~~~~~~~~~~~

They are just very old bugs in seldomly used pin groups.
Fix the problem by using the pins and referencing the
function.
Reported-by: Hulk Robot <hulkci@huawei.com>
Reported-by: Jason Yan <yanaijie@huawei.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

The Hulk robot reports an usused varible:

drivers/pinctrl/nomadik/pinctrl-ab8505.c:137:23: warning:
‘gpio50_a_1_pins’ defined but not used [-Wunused-const-variable=]
 static const unsigned gpio50_a_1_pins[] = { AB8505_PIN_L4 };
                       ^~~~~~~~~~~~~~~

This variable actually should be used. Probably an oversight
by the driver author.

Cc: Patrice Chotard <patrice.chotard@st.com>
Reported-by: Hulk Robot <hulkci@huawei.com>
Reported-by: Jason Yan <yanaijie@huawei.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

The 'pwm37' is not added to bm1880_pctrl_groups, which triggers a gcc
build warning:

drivers/pinctrl/pinctrl-bm1880.c:263:27: warning: ‘pwm37_pins’ defined
but not used [-Wunused-const-variable=]
 static const unsigned int pwm37_pins[] = { 110 };
Signed-off-by: Jason Yan <yanaijie@huawei.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20200428115543.33379-1-yanaijie@huawei.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Pin direction is not used to set pin configuration.

Fixes: a502b343 ("pinctrl: stmfx: update pinconf settings")
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Link: https://lore.kernel.org/r/20200422072513.8352-1-amelie.delaunay@st.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

use codespell to fix lots of typos over frontends.
Signed-off-by: Dejin Zheng <zhengdejin5@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
CC: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20200421142402.9524-1-zhengdejin5@gmail.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Use gpiochip_generic_config for the gpio_chip's set_config callback so
GPIO flags like GPIO_PULL_UP or GPIO_PULL_DOWN can be used in the board
.dts descriptions.
This is required for some Meson8m2 boards where GPIO_BSD_EN provides the
"MUTE" signal and requires enabling the internal pull-up resistor.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20200417183349.1283092-3-martin.blumenstingl@googlemail.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Implement the get_direction callback so we read the direction from the
actual GPIO controller register. This is recommended by the gpio_chip
kernel doc.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20200417183349.1283092-2-martin.blumenstingl@googlemail.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Currently, for EINT_TYPE GPIOs, the CON and FLTCON registers
are saved and restored over a suspend/resume cycle.  However, the
EINT_MASK registers are not.

On S5PV210 at the very least, these registers are not retained over
suspend, leading to the interrupts remaining masked upon resume and
therefore no interrupts being triggered for the device.  There should
be no effect on any SoCs that do retain these registers as theoretically
we would just be re-writing what was already there.

Fixes: 7ccbc60c ("pinctrl: exynos: Handle suspend/resume of GPIO EINT registers")
Cc: <stable@vger.kernel.org>
Signed-off-by: Jonathan Bakker <xc-racer2@live.ca>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>

Add initial Qualcomm SM8250 pinctrl driver to support pin configuration
with pinctrl framework for SM8250 SoC.
Signed-off-by: Rishabh Bhatnagar <rishabhb@codeaurora.org>
Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
Link: https://lore.kernel.org/r/1586477057-7636-2-git-send-email-vnkgutta@codeaurora.org
[bjorn: Regrouped functions, upstream tiles implementation, dropped
        downstream-only features]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20200417061907.1226490-3-bjorn.andersson@linaro.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Add device tree binding Documentation details for Qualcomm SM8250
pinctrl driver.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20200417061907.1226490-2-bjorn.andersson@linaro.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

It's common across the drivers to use the (pin_base, npins) pair to describe
community characteristics. Thus, move them in the struct intel_community
to be closer to each other.

While at it, add a blank line to cut driver usable fields from what core
reserves for itself.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>

It appears that most of the drivers, that are using struct intel_community,
utilize gpps rather than gpp_size. Update comment accordingly.

While here, correct the description of gpp_size, i.e. remove double space
and drop redundant 'etc.' part.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>

The "PIN CONTROLLER - RENESAS" section lacks the related DT bindings.
Add them.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/20200417141003.22816-1-geert+renesas@glider.be

The rza1l_swio_entries referred to the wrong array rza1h_swio_pins,
which was intended to be rza1l_swio_pins. So let's fix it.

This is detected by the following gcc warning:

drivers/pinctrl/pinctrl-rza1.c:401:35: warning: ‘rza1l_swio_pins’
defined but not used [-Wunused-const-variable=]
 static const struct rza1_swio_pin rza1l_swio_pins[] = {
                                   ^~~~~~~~~~~~~~~

Fixes: 039bc58e ("pinctrl: rza1: Add support for RZ/A1L")
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Jason Yan <yanaijie@huawei.com>
Link: https://lore.kernel.org/r/20200417111604.19143-1-yanaijie@huawei.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

According to Braswell NDA Specification Update (#557593),
concurrent read accesses may result in returning 0xffffffff and write
instructions may be dropped. We have an established format for the
commit references, i.e.
cdca06e4 ("pinctrl: baytrail: Add missing spinlock usage in
byt_gpio_irq_handler")

Fixes: 0bd50d71 ("pinctrl: cherryview: prevent concurrent access to GPIO controllers")
Signed-off-by: Grace Kao <grace.kao@intel.com>
Reported-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

Fix the following build warning:

WARNING: modpost: missing MODULE_LICENSE() in
drivers/pinctrl/pinctrl-mcp23s08.o
see include/linux/module.h for more information
Signed-off-by: Jason Yan <yanaijie@huawei.com>
Link: https://lore.kernel.org/r/20200417092125.12513-1-yanaijie@huawei.comReported-by: Randy Dunlap <rdunlap@infradead.org>
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

Remove duplicated include.

Fixes: 13bec8d4 ("pinctrl: qcom: use scm_call to route GPIO irq to Apps")
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20200408070504.134847-1-yuehaibing@huawei.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

There is no need to repeat functionality of platform_get_irq_optional()
in the driver. Replace it with explicit call to the helper.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>