- 21 Nov, 2012 7 commits
-
-
Hauke Mehrtens authored
Register a GPIO driver to access the GPIOs provided by the chip. The GPIOs of the SoC should always start at 0 and the other GPIOs could start at a random position. There is just one SoC in a system and when they start at 0 the number is predictable. Signed-off-by:
Hauke Mehrtens <hauke@hauke-m.de> Patchwork: http://patchwork.linux-mips.org/patch/4591Acked-by:
Florian Fainelli <florian@openwrt.org>
-
Hauke Mehrtens authored
The GPIOs are access through some registers in the chip common core or over extif. We need locking around these GPIO accesses, all GPIOs are accessed through the same registers and parallel writes will cause problems. Signed-off-by:
-
Hauke Mehrtens authored
Add functions to access the GPIO registers for pullup and pulldown. These are needed for handling gpio registration. Signed-off-by:
-
Hauke Mehrtens authored
Register a GPIO driver to access the GPIOs provided by the chip. The GPIOs of the SoC should always start at 0 and the other GPIOs could start at a random position. There is just one SoC in a system and when they start at 0 the number is predictable. Signed-off-by:
-
Hauke Mehrtens authored
Add description to the function. Signed-off-by:
-
Hauke Mehrtens authored
Add functions to access the GPIO registers for pullup and pulldown. These are needed for handling gpio registration. Signed-off-by:
-
Hauke Mehrtens authored
The GPIOs are access through some registers in the chip common core. We need locking around these GPIO accesses, all GPIOs are accessed through the same registers and parallel writes will cause problems. Signed-off-by:
-
- 20 Nov, 2012 3 commits
-
-
Gabor Juhos authored
Signed-off-by:
Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4223Signed-off-by:
John Crispin <blogic@openwrt.org>
-
Jayachandran C authored
Use the nlm_set_pic_extra_ack() call to setup the extra interrupt ACK needed by XLR PCI and XLS PCIe. Simplify the code by adding nlm_pci_link_to_irq(). Signed-off-by:
Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4561Signed-off-by:
-
Florian Fainelli authored
BCM6345 has an intermediate 16-bits wide test control register between the peripheral identifier register, and its clock control register is only 16-bits wide contrary to other platforms where it is 32-bits wide. By shifting all clocks bits by 16-bits to the left we ensure they get written to the proper clock control register, without adding specific BCM6345 handling in the clock code. Signed-off-by:
-
- 11 Nov, 2012 6 commits
-
-
John Crispin authored
The internal GPHYs need a firmware blob to function properly. This patch adds the code needed to request the blob and load it to the PHY. Signed-off-by:
-
John Crispin authored
The XRX200 family of SoCs has embedded gigabit PHYs. This patch adds code to boot them up. Signed-off-by:
-
John Crispin authored
Signed-off-by:
-
John Crispin authored
Print the hardware revision and port/channel info when starting the dma core. Signed-off-by:
-
John Crispin authored
The XRX200 SoC family has a different register layout for reading the boot selection bits. Signed-off-by:
-
John Crispin authored
The bootmem was incorrectly freed resulting in lots of dangling pointers. Additionally we should use of_platform_populate() as the Documentaion tells us to do so. Signed-off-by:
-
- 09 Nov, 2012 24 commits
-
-
Kelvin Cheung authored
Fix a typo in the code. Signed-off-by:
Kelvin Cheung <keguang.zhang@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4434Signed-off-by:
-
Kelvin Cheung authored
Update stmmac_mdio_bus_data accordingly due to the upstream change. Signed-off-by:
-
Kelvin Cheung authored
Improve ls1x_serial_setup(). Signed-off-by:
-
Kelvin Cheung authored
Use common clock infrastructure instead of private APIs. 1. Enable COMMON_CLK in the Kconfig. 2. Remove private clock APIs, which are replaced by the code in drivers/clk/clk-ls1x.c. 3. Modify header file for drivers/clk/clk-ls1x.c. Signed-off-by:
-
Ganesan Ramalingam authored
On XLR/XLS, the cpu cores communicate with fast on-chip devices (e.g. network accelerator, security engine etc.) using the Fast Messaging Network(FMN). The FMN queues and credits needs to be configured and intialized before it can be used. The co-processor 2 on XLR/XLS CPU cores has registers for FMN access, and the XLR/XLS has custom instructions for sending and loading messages. The FMN can deliver also per-cpu interrupts when messages are available at the CPU. This patch adds FMN initialization, adds interrupt setup and handling, and also provides support for sending and receiving FMN messages. Signed-off-by:
Ganesan Ramalingam <ganesanr@broadcom.com> Signed-off-by:
-
Jayachandran C authored
Create struct nlm_pic_irq for interrupts handled by the PIC. This simplifies IRQ handling for multi-SoC as well as the single SoC cases. Also split the setup of percpu and PIC interrupts so that we can configure the PIC interrupts for every node. Signed-off-by:
-
Jayachandran C authored
There can be 1, 2 or 4 SoCs(nodes) in a multi-chip XLP board. Add an option for multi-chip boards in case of XLP, and make the number of nodes configurable. Signed-off-by:
-
Jayachandran C authored
Upto 4 Netlogic XLP SoCs can be connected over ICI links to form a coherent multi-node system. Each SoC has its own set of on-chip devices including PIC. To support this, add a per SoC stucture and use it for the PIC and SYS block addresses instead of using global variables. Signed-off-by:
-
Jayachandran C authored
Initial code to support more than 32 cpus. The platform CPU mask is updated from 32-bit mask to cpumask_t. Convert places that use cpu_/cpus_ functions to use cpumask_* functions. Signed-off-by:
-
Jayachandran C authored
Remove unused and trivial PIC accesss functions, update nlm_pic_send_ipi() and nlm_set_irt_to_cpu() to use similar logic, and use correct type for reg in nlm_pic_disable_irt(). Signed-off-by:
-
Jayachandran C authored
The cpuid was not passed into early_init_secondary even though the comment indicated that it will be. Fix this. Signed-off-by:
-
Jayachandran C authored
Used the hardware thread id passed in while writing to IRT in nlm_pic_init_irt() Signed-off-by:
-
Jayachandran C authored
Fix Kconfig for both XLR and XLP to select ZONE_DMA32 (instead of ZONE_DMA) in case of 64-bit compilation. This can be used for devices that can only do DMA to 32-bit address. ZONE_DMA is not useful on XLR or XLP. Signed-off-by:
-
Jayachandran C authored
At this point early printk is available, so debugging device tree issues is easier. Signed-off-by:
-
Jayachandran C authored
Enable Speculative Unmap Enable bit, which will enable speculative L2 cache requests for unmapped memory. This should give better performance for kernel code/data which is in KSEG0 Signed-off-by:
-
Jayachandran C authored
This allows us to use the r2 optimized code from kernel headers while compilation. Disable PGD_C0_CONTEXT option for XLP, which does not work. Signed-off-by:
-
Zi Shen Lim authored
Add support for XLP performance counters register in perf. Update mips/Kconfig so that perf events can be selected for XLP. Signed-off-by:
Zi Shen Lim <zlim@netlogicmicro.com> Signed-off-by:
-
Madhusudan Bhat authored
Add support for XLR and XLS processors in MIPS Oprofile code. These processors are multi-threaded and have two counters per core. Each counter can track either all the events in the core (global mode), or events in just one thread. We use the counters in the global mode, and use only the first thread in each core to handle the configuration etc. Signed-off-by:
Madhusudan Bhat <mbhat@netlogicmicro.com> Signed-off-by:
-
Jonas Gorski authored
Refactor nvram related functions into its own unit for easier expansion and exposure of the values to other drivers. Signed-off-by:
Jonas Gorski <jonas.gorski@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4516Signed-off-by:
-
Jonas Gorski authored
Use the new reset helper where appropriate. Signed-off-by:
-
Jonas Gorski authored
Add a reset helper for resetting the different cores. Signed-off-by:
-
Jonas Gorski authored
The softreset register description for BCM6358 was missing, so add it. Signed-off-by:
-
Jonas Gorski authored
Add a PCIe clock and use that instead of directly touching the clock control register. While at it, fail if there is no such clock. Signed-off-by:
-
Hauke Mehrtens authored
There are bcma based devices like the Linksys E2000 out there, which do have one ieee80211 core, but no PCIe core and they are using no prefixes for the sprom. In addition some values like boardtype are stored without a prefix for the main SoC chip also when they have an additional PCIe wifi chip with an own boardtype var on some devices. The Ethernet addresses are now also read out correctly without a prefix so calling bcm47xx_fill_sprom_ethernet is not needed any more. Signed-off-by:
-
