- 26 May, 2023 11 commits
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Dario Binacchi authored
The previous setting was related to the overall dimension and not to the active display area. In the "PHYSICAL SPECIFICATIONS" section, the datasheet shows the following parameters: ---------------------------------------------------------- | Item | Specifications | unit | ---------------------------------------------------------- | Display area | 98.7 (W) x 57.5 (H) | mm | ---------------------------------------------------------- | Overall dimension | 105.5(W) x 67.2(H) x 4.96(D) | mm | ---------------------------------------------------------- Fixes: 966fea78 ("drm/panel: simple: Add support for Ampire AM-480272H3TMQW-T01H") Signed-off-by:
Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by:
Neil Armstrong <neil.armstrong@linaro.org> [narmstrong: fixed Fixes commit id length] Signed-off-by:
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Geert Uytterhoeven authored
Add support for the Ampire AM-800480L1TMQW-T00H 5" WVGA TFT LCD panel. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by:
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Geert Uytterhoeven authored
Document support for the Ampire AM-800480L1TMQW-T00H 5" WVGA TFT LCD panel. Signed-off-by:
Conor Dooley <conor.dooley@microchip.com> Signed-off-by:
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Adam Ford authored
In the event a device is connected to the samsung-dsim controller that doesn't support the burst-clock, the driver is able to get the requested pixel clock from the attached device or bridge. In these instances, the samsung,burst-clock-frequency isn't needed, so remove it from the required list. The pll-clock frequency can be set by the device tree entry for samsung,pll-clock-frequency, but in some cases, the pll-clock may have the same clock rate as sclk_mipi clock. If they are equal, this flag is not needed since the driver will use the sclk_mipi rate as a fallback. Signed-off-by:
Adam Ford <aford173@gmail.com> Signed-off-by:
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Adam Ford authored
The high-speed clock is hard-coded to the burst-clock frequency specified in the device tree. However, when using devices like certain bridge chips without burst mode and varying resolutions and refresh rates, it may be necessary to set the high-speed clock dynamically based on the desired pixel clock for the connected device. This also removes the need to set a clock speed from the device tree for non-burst mode operation, since the pixel clock rate is the rate requested from the attached device like a bridge chip. This should have no impact for people using burst-mode and setting the burst clock rate is still required for those users. If the burst clock is not present, change the error message to dev_info indicating the clock use the pixel clock. Signed-off-by:
Chen-Yu Tsai <wenst@chromium.org> Tested-by:
Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by:
Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by:
Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # imx8mm-icore Signed-off-by:
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Adam Ford authored
The DPHY timings are currently hard coded. Since the input clock can be variable, the phy timings need to be variable too. To facilitate this, we need to cache the hs_clock based on what is generated from the PLL. The phy_mipi_dphy_get_default_config_for_hsclk function configures the DPHY timings in pico-seconds, and a small macro converts those timings into clock cycles based on the hs_clk. Signed-off-by:
Lucas Stach <l.stach@pengutronix.de> Tested-by:
Michael Walle <michael@walle.cc> Tested-by:
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Adam Ford authored
In order to support variable DPHY timings, it's necessary to enable GENERIC_PHY_MIPI_DPHY so phy_mipi_dphy_get_default_config can be used to determine the nominal values for a given resolution and refresh rate. Signed-off-by:
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Adam Ford authored
Make the pll-clock-frequency optional. If it's present, use it to maintain backwards compatibility with existing hardware. If it is absent, read clock rate of "sclk_mipi" to determine the rate. Since it can be optional, change the message from an error to dev_info. Signed-off-by:
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Adam Ford authored
According to Table 13-45 of the i.MX8M Mini Reference Manual, the min and max values for M and the frequency range for the VCO_out calculator were incorrect. This information was contradicted in other parts of the mini, nano and plus manuals. After reaching out to my NXP Rep, when confronting him about discrepencies in the Nano manual, he responded with: "Yes it is definitely wrong, the one that is part of the NOTE in MIPI_DPHY_M_PLLPMS register table against PMS_P, PMS_M and PMS_S is not correct. I will report this to Doc team, the one customer should be take into account is the Table 13-40 DPHY PLL Parameters and the Note above." These updated values also match what is used in the NXP downstream kernel. To fix this, make new variables to hold the min and max values of m and the minimum value of VCO_out, and update the PMS calculator to use these new variables instead of using hard-coded values to keep the backwards compatibility with other parts using this driver. Fixes: 4d562c70 ("drm: bridge: samsung-dsim: Add i.MX8M Mini/Nano support") Signed-off-by:
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Lucas Stach authored
Scale the blanking packet sizes to match the ratio between HS clock and DPI interface clock. The controller seems to do internal scaling to the number of active lanes, so we don't take those into account. Signed-off-by:
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Rob Clark authored
Fixes undefined symbol when PROC_FS is not enabled. Reported-by:
kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202305251510.U0R2as7k-lkp@intel.com/ Fixes: 376c25f8 ("drm/amdgpu: Switch to fdinfo helper") Signed-off-by:
Rob Clark <robdclark@chromium.org> Reviewed-by: <alexander.deucher@amd.com> Signed-off-by:
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- 25 May, 2023 3 commits
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Frieder Schrempf authored
The datasheet describes the following initialization flow including minimum delay times between each step: 1. DSI data lanes need to be in LP-11 and the clock lane in HS mode 2. toggle EN signal 3. initialize registers 4. enable PLL 5. soft reset 6. enable DSI stream 7. check error status register To meet this requirement we need to make sure the host bridge's pre_enable() is called first by using the pre_enable_prev_first flag. Furthermore we need to split enable() into pre_enable() which covers steps 2-5 from above and enable() which covers step 7 and is called after the host bridge's enable(). Signed-off-by:
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Frieder Schrempf authored
According to the documentation [1] the proper enable flow is: 1. Enable DSI link and keep data lanes in LP-11 (stop state) 2. Disable stop state to bring data lanes into HS mode Currently we do this all at once within enable(), which doesn't allow to meet the requirements of some downstream bridges. To fix this we now enable the DSI in pre_enable() and force it into stop state using the FORCE_STOP_STATE bit in the ESCMODE register until enable() is called where we reset the bit. We currently do this only for i.MX8M as Exynos uses a different init flow where samsung_dsim_init() is called from samsung_dsim_host_transfer(). [1] https://docs.kernel.org/gpu/drm-kms-helpers.html#mipi-dsi-bridge-operationSigned-off-by:
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Alexander Stein authored
This map was created from register map from datasheet (section 5.1.2). Unused registers are stated by address, so they show up in debugfs as well. Signed-off-by:
Alexander Stein <alexander.stein@ew.tq-group.com> Reviewed-by:
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- 24 May, 2023 14 commits
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Rob Clark authored
The restriction about no whitespace, etc, really only applies to the usage of strings in keys. Values can contain anything (other than newline). Signed-off-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Acked-by:
Dave Airlie <airlied@redhat.com> Signed-off-by:
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Rob Clark authored
Use the new helper to export stats about memory usage. v2: Drop unintended hunk v3: Rebase Signed-off-by:
Emil Velikov <emil.l.velikov@gmail.com> Acked-by:
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Rob Clark authored
Add support to dump GEM stats to fdinfo. v2: Fix typos, change size units to match docs, use div_u64 v3: Do it in core v4: more kerneldoc v5: doc fixes v6: Actually use u64, bit more comment docs Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by:
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Rob Clark authored
v2: Rebase on drm-misc-next Signed-off-by:
Christian König <christian.koenig@amd.com> Acked-by:
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Rob Clark authored
Now that we have a common helper, use it. v2: Rebase on drm-misc-next Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Acked-by:
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Rob Clark authored
Handle a bit of the boiler-plate in a single case, and make it easier to add some core tracked stats. This also ensures consistent behavior across drivers for standardised fields. v2: Update drm-usage-stats.rst, 64b client-id, rename drm_show_fdinfo v3: Rebase on drm-misc-next Reviewed-by:
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Rob Clark authored
Fix a couple missing ':'s. Signed-off-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by:
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Geert Uytterhoeven authored
The LCD Controller supported by the drm-shmob driver is present on SuperH SH-Mobile SoCs, and on Renesas ARM SH/R-Mobile SoCs. Unfortunately its config option is not visible on either, so the user can never enable the support. Fix this by dropping the dependency on ARM (for SuperH), and by widening the dependency range to ARCH_RENESAS (for ARM). Signed-off-by:
Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
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Geert Uytterhoeven authored
Set up generic fbdev emulation, to enable support for the Linux console. Use 16 as the preferred depth, as that is a good compromise between colorfulness and resource utilization, and the default of the fbdev driver. Suggested-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by:
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Geert Uytterhoeven authored
The SH-Mobile DRM driver uses the legacy drm_crtc_init(), which advertizes only the formats in safe_modeset_formats[] (XR24 and AR24) as being supported. Switch to drm_crtc_init_with_planes(), and advertize all supported (A)RGB modes, so we can use RGB565 as the default mode for the console. Signed-off-by:
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Geert Uytterhoeven authored
DRM_FORMAT_XRGB8888 aka XR24 is the modus francus of DRM, and should be supported by all drivers. The handling for DRM_FORMAT_XRGB8888 is similar to DRM_FORMAT_ARGB8888, just ignore the alpha channel. Signed-off-by:
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Geert Uytterhoeven authored
Replace the printing of hexadecimal fourcc format codes by pretty-printed format names, using the "%p4cc" format specifier. Signed-off-by:
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Azeem Shaikh authored
strlcpy() reads the entire source buffer first. This read may exceed the destination size limit. This is both inefficient and can lead to linear read overflows if a source string is not NUL-terminated [1]. In an effort to remove strlcpy() completely [2], replace strlcpy() here with strscpy(). No return values were used, so direct replacement is safe. [1] https://www.kernel.org/doc/html/latest/process/deprecated.html#strlcpy [2] https://github.com/KSPP/linux/issues/89Signed-off-by:
Azeem Shaikh <azeemshaikh38@gmail.com> Reviewed-by:
Kees Cook <keescook@chromium.org> Signed-off-by:
Sumit Semwal <sumit.semwal@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20230523021943.2406847-1-azeemshaikh38@gmail.com
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Artur Weber authored
Fixes compilation issues with older GCC versions and Clang after changes introduced in commit 6810bb39 ("drm/panel: Add Samsung S6D7AA0 panel controller driver"). Tested with GCC 13.1.1, GCC 6.4.0 and Clang 16.0.3. Fixes the following errors with Clang: drivers/gpu/drm/panel/panel-samsung-s6d7aa0.c:312:14: error: initializer element is not a compile-time constant .drm_mode = s6d7aa0_lsl080al02_mode, ^~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/panel/panel-samsung-s6d7aa0.c:415:14: error: initializer element is not a compile-time constant .drm_mode = s6d7aa0_lsl080al03_mode, ^~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/panel/panel-samsung-s6d7aa0.c:443:14: error: initializer element is not a compile-time constant .drm_mode = s6d7aa0_ltl101at01_mode, ^~~~~~~~~~~~~~~~~~~~~~~ 3 errors generated. Fixes the following errors with GCC: drivers/gpu/drm/panel/panel-samsung-s6d7aa0.c:312:14: error: initializer element is not constant .drm_mode = s6d7aa0_lsl080al02_mode, ^~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/panel/panel-samsung-s6d7aa0.c:312:14: note: (near initialization for 's6d7aa0_lsl080al02_desc.drm_mode') drivers/gpu/drm/panel/panel-samsung-s6d7aa0.c:415:14: error: initializer element is not constant .drm_mode = s6d7aa0_lsl080al03_mode, ^~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/panel/panel-samsung-s6d7aa0.c:415:14: note: (near initialization for 's6d7aa0_lsl080al03_desc.drm_mode') drivers/gpu/drm/panel/panel-samsung-s6d7aa0.c:443:14: error: initializer element is not constant .drm_mode = s6d7aa0_ltl101at01_mode, ^~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/panel/panel-samsung-s6d7aa0.c:443:14: note: (near initialization for 's6d7aa0_ltl101at01_desc.drm_mode') Reported-by:
Nathan Chancellor <nathan@kernel.org> Link: https://lore.kernel.org/lkml/20230523180212.GA1401867@dev-arch.thelio-3990XReported-by:
kernelci.org bot <bot@kernelci.org> Link: https://lore.kernel.org/llvm/646c6def.a70a0220.58c1a.903d@mx.google.com Fixes: 6810bb39 ("drm/panel: Add Samsung S6D7AA0 panel controller driver") Signed-off-by:
Artur Weber <aweber.kernel@gmail.com> Acked-by:
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- 23 May, 2023 4 commits
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Azeem Shaikh authored
strlcpy() reads the entire source buffer first. This read may exceed the destination size limit. This is both inefficient and can lead to linear read overflows if a source string is not NUL-terminated [1]. In an effort to remove strlcpy() completely [2], replace strlcpy() here with strscpy(). No return values were used, so direct replacement is safe. [1] https://www.kernel.org/doc/html/latest/process/deprecated.html#strlcpy [2] https://github.com/KSPP/linux/issues/89Signed-off-by:
Robert Foss <rfoss@kernel.org> Signed-off-by:
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Nícolas F. R. A. Prado authored
During probe, the driver registers i2c dummy devices and populates the aux bus, which registers a device for the panel. After doing that, the driver can still defer probe if needed. This ordering of operations is troublesome however, because the deferred probe work will retry probing all pending devices every time a new device is registered. Therefore, if modules need to be loaded in order to satisfy the dependencies for this driver to complete probe, the kernel will stall, since it'll keep trying to probe the anx7625 driver, but never succeed, given that modules would only be loaded after the deferred probe work completes. Two changes are required to avoid this issue: * Move of_find_mipi_dsi_host_by_node(), which can defer probe, to before anx7625_register_i2c_dummy_clients() and devm_of_dp_aux_populate_ep_devices(), which register devices. * Make use of the done_probing callback when populating the aux bus, so that the bridge registration is only done after the panel is probed. This is required because the panel might need to defer probe, but the aux bus population needs the i2c dummy devices working, so this call couldn't just be moved to an earlier point in probe. One caveat is that if the panel is described outside the aux bus, the probe loop issue can still happen, but we don't have a way to avoid it in that case since there's no callback available. With this patch applied, it's possible to boot on mt8192-asurada-spherion with CONFIG_DRM_ANALOGIX_ANX7625=y CONFIG_MTK_MMSYS=m CONFIG_BACKLIGHT_PWM=y and also with CONFIG_DRM_ANALOGIX_ANX7625=y CONFIG_MTK_MMSYS=y CONFIG_BACKLIGHT_PWM=m Fixes: adca62ec ("drm/bridge: anx7625: Support reading edid through aux channel") Fixes: 26933299 ("drm/bridge: anx7625: Return -EPROBE_DEFER if the dsi host was not found") Reported-by:
Nícolas F. R. A. Prado <nfraprado@collabora.com> Reviewed-by:
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Thomas Zimmermann authored
The fbdev framebuffer is in system memory. Store the address in the field 'screen_buffer'. Fixes the following sparse warning. ../drivers/gpu/drm/msm/msm_fbdev.c:124:26: warning: incorrect type in assignment (different address spaces) ../drivers/gpu/drm/msm/msm_fbdev.c:124:26: expected char [noderef] __iomem *screen_base ../drivers/gpu/drm/msm/msm_fbdev.c:124:26: got void * Signed-off-by:
Javier Martinez Canillas <javierm@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230522191701.13406-1-tzimmermann@suse.de
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Thomas Zimmermann authored
The fbdev framebuffer is I/O memory, so clear it with fb_memset_io(). Fixes the following sparse warning: ../drivers/gpu/drm/gma500/fbdev.c:234:20: warning: incorrect type in argument 1 (different address spaces) ../drivers/gpu/drm/gma500/fbdev.c:234:20: expected void *s ../drivers/gpu/drm/gma500/fbdev.c:234:20: got char [noderef] __iomem *screen_base Signed-off-by:
Patrik Jakobsson <patrik.r.jakobsson@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230522190637.7039-1-tzimmermann@suse.de
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- 22 May, 2023 8 commits
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Tom Rix authored
smatch reports drivers/gpu/drm/nouveau/nvkm/subdev/gsp/ga102.c:49:1: warning: symbol 'ga102_gsps' was not declared. Should it be static? This variable is only used in its defining file, so it should be static Signed-off-by:
Tom Rix <trix@redhat.com> Reviewed-by:
Karol Herbst <kherbst@redhat.com> Signed-off-by:
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Krzysztof Kozlowski authored
Statically allocated array of pointers to hwmon_channel_info can be made const for safety. Reviewed-by:
Lyude Paul <lyude@redhat.com> Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
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Arnd Bergmann authored
nv50_display_create() is declared in another header, along with a couple of declarations that are now outdated: drivers/gpu/drm/nouveau/dispnv50/disp.c:2517:1: error: no previous prototype for 'nv50_display_create' Fixes: ba801ef0 ("drm/nouveau/kms: display destroy/init/fini hooks can be static") Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Reviewed-by:
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Marek Vasut authored
Implement support for DSI clock and data lane DN/DP polarity swap by means of decoding 'lane-polarities' DT property. The controller does support DN/DP swap of clock lane and all data lanes, the controller does not support polarity swap of individual data lane bundles, add a check which verifies all data lanes have the same polarity. This has been validated on an imx8mm board that actually has the MIPI DSI clock lanes inverted. Signed-off-by:
Marek Vasut <marex@denx.de> Signed-off-by:
Fabio Estevam <festevam@denx.de> Reviewed-by:
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Fabio Estevam authored
The Samsung DSIM IP block allows the inversion of the clock and data lanes. Add an optional property called 'lane-polarities' that describes the polarities of the MIPI DSI clock and data lanes. This property is useful for properly describing the hardware when the board designer decided to switch the polarities of the MIPI DSI clock and/or data lanes. Signed-off-by:
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Artur Weber authored
Add myself as maintainer of the Samsung S6D7AA0 panel driver. Signed-off-by:
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Artur Weber authored
Initial driver for S6D7AA0-controlled panels. Currently, the following panels are supported: - S6D7AA0-LSL080AL02 (Samsung Galaxy Tab 3 8.0) - S6D7AA0-LSL080AL03 (Samsung Galaxy Tab A 8.0 2015) - S6D7AA0-LTL101AT01 (Samsung Galaxy Tab A 9.7 2015) It should be possible to extend this driver to work with other panels using this IC. Tested-by: Nikita Travkin <nikita@trvn.ru> #ltl101at01 Signed-off-by:
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Artur Weber authored
Add bindings for the S6D7AA0 LCD panel controller, including the S6D7AA0-LSL080AL02 panel used in the Samsung Galaxy Tab 3 8.0 family of tablets, and the S6D7AA0-LSL080AL03 and S6D7AA0-LTL101AT01 panels used in the Samsung Galaxy Tab A 8.0 and 9.7 2015. Signed-off-by:
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