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  1. 25 Oct, 2010 1 commit
  3. 22 Oct, 2010 14 commits
    • Erik Gilling's avatar
      spi: add spi_tegra driver · 0c03a1dd
      Erik Gilling authored 
      v2 changes:
  from Thierry Reding:
    * add "select TEGRA_SYSTEM_DMA" to Kconfig
  from Grant Likely:
    * add oneline description to header
    * inline references to DRIVER_NAME
    * inline references to BUSY_TIMEOUT
    * open coded bytes_per_word()
    * spi_readl/writel -> spi_tegra_readl/writel
    * move transfer validation to spi_tegra_transfer
    * don't request_mem_region iomem as platform bus does that for us
    * __exit -> __devexit

v3 changes:
  from Russell King:
    * put request_mem_region back int
  from Grant Likely:
    * remove #undef DEBUG
    * add SLINK_ to register bit defines
    * remove unused bytes_per_word
    * make spi_tegra_readl/writel static linine
    * various refactoring for clarity
    * mark err if BSY bit is not cleared after 1000 retries
    * move spinlock to protect setting of RDY bit
    * subsys_initcall -> module_init

v3 changes:
  from Grant Likely:
    * update spi_tegra to use PTR_ERRless dma API

v4 changes:
  from Grant Likely:
    * remove empty spi_tegra_cleanup fucntion
    * allow device ids of -1
Signed-off-by: default avatarErik Gilling <konkers@android.com>
Acked-by: default avatarGrant Likely <grant.likely@secretlab.ca>
Cc: Thierry Reding <thierry.reding@avionic-design.de>
Cc: Russell King <linux@arm.linux.org.uk>

spi: tegra: cleanups from upstream review

Change-Id: Icecf7e64efcb39de072a15234ba1faa4bad40d25
Signed-off-by: default avatarErik Gilling <konkers@android.com>
      0c03a1dd
    • Mike Rapoport's avatar
      tegra: harmony: enable PCI Express · f2a44393
      Mike Rapoport authored 
      Signed-off-by: default avatarMike Rapoport <mike@compulab.co.il>
CC: Olof Johansson <olof@lixom.net>
CC: Gary King <GKing@nvidia.com>
Signed-off-by: default avatarColin Cross <ccross@android.com>
      f2a44393
    • Mike Rapoport's avatar
      tegra: add PCI Express support · 77ffc146
      Mike Rapoport authored 
      Change-Id: Ibd0bcd46895eb88952b9db29e1f68572d39aae01
Signed-off-by: default avatarMike Rapoport <mike@compulab.co.il>
Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
CC: Russell King <linux@arm.linux.org.uk>
CC: Gary King <GKing@nvidia.com>
Signed-off-by: default avatarColin Cross <ccross@android.com>
      77ffc146
    • Mike Rapoport's avatar
      tegra: add PCI Express clocks · 8d685bc5
      Mike Rapoport authored 
      Signed-off-by: default avatarMike Rapoport <mike@compulab.co.il>
CC: Gary King <GKing@nvidia.com>
Signed-off-by: default avatarColin Cross <ccross@android.com>
      8d685bc5
    • Colin Cross's avatar
      [ARM] tegra: Add APB DMA support · 4de3a8fa
      Colin Cross authored 
      The APB DMA block handles DMA transfers to and from some peripherals
in the Tegra SOC.  It reads from sequential addresses on the memory
bus, and writes repeatedly to the same address on the APB bus.

Two transfer modes are supported, oneshot for transferring a known
size to or from a peripheral, and continuous for streaming data.
In continuous mode, a callback occurs when the buffer is half full
to allow the existing data to be handled and a new request queued.x

v2 changes:
	dma API no longer uses PTR_ERR
Signed-off-by: default avatarErik Gilling <konkers@android.com>
Signed-off-by: default avatarColin Cross <ccross@android.com>
      4de3a8fa
    • Colin Cross's avatar
      [ARM] tegra: Add cpufreq support · 7056d423
      Colin Cross authored 
      Implement cpufreq support for the Tegra SOC.  DVFS is handled by the
core virtual cpu clock.  The frequencies of the two cores are tied
together, the highest frequency requested by either core determines
the actual frequency.
Signed-off-by: default avatarColin Cross <ccross@android.com>
      7056d423
    • Colin Cross's avatar
      [ARM] tegra: common: Update common clock init table · 8486bddc
      Colin Cross authored 
      Renames clocks in the clock init table to match the datasheet names
Signed-off-by: default avatarColin Cross <ccross@android.com>
      8486bddc
    • Colin Cross's avatar
      [ARM] tegra: clock: Add dvfs support, bug fixes, and cleanups · 71fc84cc
      Colin Cross authored 
      - Add drivers to clock lookup table
- Add new pll_m entries
- Support I2C U16 divider
- Fix rate reporting on 32.768kHz clock
- Call propagate rate only if set_rate succeeds
- Add support for audio_sync clock
- Add 24MHz to PLLA frequency list
- Correct i2s1/2/spdifout mux
- Add suspend support
- Fix enable/disable parent clocks in set_parent
- Add max_rate parameter to all clocks
- DVFS support
- Add virtual cpu clock with dvfs
- Support clk_round_rate
- Fix requesting very high periph frequencies
- Add quirks for PLLU:
   PLLU is slightly different from the rest of the PLLs.  The
   lock enable bit is at bit 22 instead of 18 in the MISC
   register, and the post divider field is a single bit with
   reversed values from other PLLs.
- Simplify recalculating clock rates
- Fix UART divider flags
- Remove unused clock ops
Signed-off-by: default avatarColin Cross <ccross@android.com>
      71fc84cc
    • Colin Cross's avatar
      [ARM] tegra: Add support for reading fuses · 73625e3e
      Colin Cross authored 
      The Tegra SOC contains fuses to identify the CPU type and
bin, and a unique id.  The CPU info is required to determine
the correct voltages for each cpu and core frequency.
Signed-off-by: default avatarColin Cross <ccross@android.com>
      73625e3e
    • Colin Cross's avatar
      [ARM] tegra: gpio: Add suspend and wake support · 2e47b8b3
      Colin Cross authored 
      Includes checkpatch fixes and TEGRA_NR_GPIOS changes from
Mike Rapoport <mike@compulab.co.il>
Signed-off-by: default avatarColin Cross <ccross@android.com>
      2e47b8b3
    • Colin Cross's avatar
      [ARM] tegra: pinmux: add safe values, move tegra2, add suspend · c5f04b8d
      Colin Cross authored 
      - the reset values for some pin groups in the tegra pin mux can result in
functional errors due to conflicting with actively-configured pin groups
muxing from the same controller. this change adds a known safe, non-
conflicting mux for every pin group, which can be used on platforms
where the pin group is not routed to any peripheral

- also add each pin group's I/O voltage rail, to enable platform code to
map from the pin groups used by each interface to the regulators used
for dynamic voltage control

- add routines to individually configure the tristate, pin mux and pull-
ups for a pingroup_config array, so that it is possible to program
individual values at run-time without modifying other values.
this allows driver power-management code to reprogram individual
interfaces into lower power states during idle / suspend, or to
reprogram the pin mux to support multiple physical busses per
internal controller (e.g., sharing a single I2C or SPI controller
across multiple pin groups)

- move chip-specific data like pingroups and drive-pingroups
out of the common code and into chip-specific code

- fix debug output for group with no pullups

- add a TEGRA_MUX_SAFE function.  Setting a pingroup to TEGRA_MUX_SAFE
will automatically select a mux setting that is guaranteed not to
conflict with any of the hardware blocks.
Signed-off-by: default avatarGary King <gking@nvidia.com>
      c5f04b8d
    • Gary King's avatar
      [ARM] tegra: add suspend and mirror irqs to legacy controller · 460907bc
      Gary King authored 
      mirror IRQ enable and disable operations on the legacy PPI system
interrupt controller, since the legacy controller is responsible
for responding to wakeup interrupts when the CPU is in LP2 idle mode

save the irq controller state on suspend and restore on resume
Signed-off-by: default avatarGary King <gking@nvidia.com>
      460907bc
    • Colin Cross's avatar
      [ARM] tegra: Add legacy irq support · 8726e4f5
      Colin Cross authored 
      The "legacy irq controller" duplicates the functionality of the GIC,
but remains powered during the cpu suspend and idle modes that power
down the CPU and the GIC.
Signed-off-by: default avatarColin Cross <ccross@android.com>
      8726e4f5
    • Colin Cross's avatar
      [ARM] tegra: update iomap · c231d697
      Colin Cross authored 
      Add missing io address map entries from datasheet.
Add the IRAM area to the statically mapped io regions.
Correct the onewire, USB, and statmon addresses
Signed-off-by: default avatarColin Cross <ccross@android.com>
      c231d697
  5. 21 Oct, 2010 25 commits
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