- 23 Feb, 2023 2 commits
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Miquel Raynal authored
NAND core changes: * Check the data only read pattern only once * Prepare the late addition of supported operation checks * Support for sequential cache reads * Fix nand_chip kdoc Raw NAND changes: * Fsl_elbc: Propagate HW ECC settings to HW * Marvell: Add missing layouts * Pasemi: Don't use static data to track per-device state * Sunxi: - Fix the size of the last OOB region - Remove an unnecessary check - Remove an unnecessary check - Clean up chips after failed init - Precompute the ECC_CTL register value - Embed sunxi_nand_hw_ecc by value - Update OOB layout to match hardware * tmio_nand: Remove driver * vf610_nfc: Use regular comments for functions SPI-NAND changes: * Add support for AllianceMemory AS5F34G04SND * Macronix: use scratch buffer for DMA operation NAND ECC changes: * Mediatek: - Add ECC support fot MT7986 IC - Add compatible for MT7986 - dt-bindings: Split ECC engine with rawnand controller
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Miquel Raynal authored
SPI NOR changes: * small fixes on core and spansion driver.
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- 06 Feb, 2023 7 commits
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Francesco Dolcini authored
Add a mechanism to handle the case in which partitions are present as direct child of the nand controller node and #size-cells is set to <0>. This could happen if the nand-controller node in the DTS is supposed to have #size-cells set to 0, but for some historical reason/bug it was set to 1 in the past, and the firmware (e.g. U-Boot) is adding the partition as direct children of the nand-controller defaulting to #size-cells being to 1. This prevents a real boot failure on colibri-imx7 that happened during v6.1 development cycles. Link: https://lore.kernel.org/all/Y4dgBTGNWpM6SQXI@francesco-nb.int.toradex.com/ Link: https://lore.kernel.org/all/20221202071900.1143950-1-francesco@dolcini.it/Signed-off-by:
Francesco Dolcini <francesco.dolcini@toradex.com> Signed-off-by:
Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20230124104444.330913-1-francesco@dolcini.it
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Samuel Holland authored
The value computed by this function never changes for a given chip. Compute the whole register value once up front, instead of every time the ECC engine is enabled. Signed-off-by:
Samuel Holland <samuel@sholland.org> Signed-off-by:
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Samuel Holland authored
The sunxi_nand_hw_ecc object is not shared, and it has the same lifetime as the sunxi_nand_chip which points to it, so we can embed it in the outer structure instead of using a pointer. This removes an unnecessary memory allocation and simplifies the error handling code. Signed-off-by:
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Samuel Holland authored
When using the hardware ECC engine, the OOB data is made available in the NFC_REG_USER_DATA registers, as one 32-bit word per ECC step. Any additional bytes are only accessible through raw reads and software descrambling. For efficiency, and to match the vendor driver, ignore these extra bytes when using hardware ECC. Note that until commit 34569d86 ("mtd: rawnand: sunxi: Fix the size of the last OOB region"), this extra free area was reported with length zero, so this is not a functional change for any stable kernel user. Signed-off-by:
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Tudor Ambarus authored
Merge 'mtd/fixes-for-6.2-rc4' into spi-nor/next to fix conflict on include headers in drivers/mtd/spi-nor/core.c. Signed-off-by:Tudor Ambarus <tudor.ambarus@linaro.org>
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Tudor Ambarus authored
Sort headers alphabetically - it helps locating duplicates, and makes it easier to figure out where to insert new headers. Alphabetic order should also prove that each header is self-contained, i.e. can be included without prerequisites. Link: https://lore.kernel.org/r/20230202144628.14443-1-tudor.ambarus@linaro.orgSigned-off-by:
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Louis Rannou authored
spi_nor_set_erase_type() was used either to set or to mask out an erase type. When we used it to mask out an erase type a shift-out-of-bounds was hit: UBSAN: shift-out-of-bounds in drivers/mtd/spi-nor/core.c:2237:24 shift exponent 4294967295 is too large for 32-bit type 'int' The setting of the size_{shift, mask} and of the opcode are unnecessary when the erase size is zero, as throughout the code just the erase size is considered to determine whether an erase type is supported or not. Setting the opcode to 0xFF was wrong too as nobody guarantees that 0xFF is an unused opcode. Thus when masking out an erase type, just set the erase size to zero. This will fix the shift-out-of-bounds. Fixes: 5390a8df ("mtd: spi-nor: add support to non-uniform SFDP SPI NOR flash memories") Cc: stable@vger.kernel.org Reported-by:Alexander Stein <Alexander.Stein@tq-group.com> Signed-off-by:
Louis Rannou <lrannou@baylibre.com> Tested-by:
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- 03 Feb, 2023 3 commits
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Xiangsheng Hou authored
Add ECC support fot MT7986 IC, and change err_mask value with GENMASK macro. Signed-off-by:
Xiangsheng Hou <xiangsheng.hou@mediatek.com> Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by:
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Xiangsheng Hou authored
Add dt-bindings documentation of ECC for MediaTek MT7986 SoC platform. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
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Xiangsheng Hou authored
Split MediaTek ECC engine with rawnand controller and convert to YAML schema. Signed-off-by:
kernel test robot <lkp@intel.com> Signed-off-by:
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- 30 Jan, 2023 3 commits
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Pali Rohár authored
It is possible that current chip->ecc.engine_type value does not match to configured HW value (if HW ECC checking and generating is enabled or not). This can happen with old U-Boot bootloader version which either does not initialize NAND (and let it in some default unusable state) or initialize NAND with different parameters than what is specified in kernel DTS file. So if kernel chose to use some chip->ecc.engine_type settings (e.g. from DTS file) then do not depend on bootloader HW configuration and configures HW ECC settings according to chip->ecc.engine_type value. BR_DECC must be set to BR_DECC_CHK_GEN when HW is doing ECC (both generating and checking), or to BR_DECC_OFF when HW is not doing ECC. This change fixes usage of SW ECC support in case bootloader explicitly enabled HW ECC support and kernel DTS file has specified to use SW ECC. (Of course this works only in case when NAND is not a boot device and both bootloader and kernel are loaded from different location, e.g. FLASH NOR.) Fixes: f6424c22 ("mtd: rawnand: fsl_elbc: Make SW ECC work") Signed-off-by:
Pali Rohár <pali@kernel.org> Signed-off-by:
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Mario Kicherer authored
Add support for AllianceMemory AS5F34G04SND SPI NAND flash Datasheet: - https://www.alliancememory.com/wp-content/uploads/pdf/flash/AllianceMemory_SPI_NAND_Flash_July2020_Rev1.0.pdfSigned-off-by:
Mario Kicherer <dev@kicherer.org> Reviewed-by:
Dhruva Gole <d-gole@ti.com> Signed-off-by:
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Rob Herring authored
The 'partition' node name pattern is missing start and end anchors, so anything is allowed before or after the regex pattern. There's no in tree users needing that, so add anchors to the pattern. Signed-off-by:
Rob Herring <robh@kernel.org> Reviewed-by:
Pratyush Yadav <ptyadav@amazon.de> Reviewed-by:
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- 26 Jan, 2023 4 commits
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Miquel Raynal authored
The INFO() macro defines an ID array and a couple of geometry properties. Right now all its lines are duplicated twice because of the INFO6() macro (for extended IDs) and soon as well we will need to add a geometry parameter to include the number of banks. In order to limit the code duplication, let's create a number of intermediate macros which will facilitate defining high-level INFOX() macros. There is no functional change. Signed-off-by:
Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20221215081241.407098-2-miquel.raynal@bootlin.comSigned-off-by:
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Tudor Ambarus authored
Cypress defines two flavors of configuration registers, volatile and non volatile, and both use the same bit fields. Rename the bitfields in the configuration registers so that they can be used for both flavors. Signed-off-by:
Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by:
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Tudor Ambarus authored
CFR5[6] is reserved bit and must be always 1. Set it to comply with flash requirements. While fixing SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_{EN, DS} definition, stop using magic numbers and describe the missing bit fields in CFR5 register. This is useful for both readability and future possible addition of Octal STR mode support. Fixes: c3266af1 ("mtd: spi-nor: spansion: add support for Cypress Semper flash") Cc: stable@vger.kernel.org Reported-by: -
Zeng Heng authored
spi-nor/core.c needs to include linux/delay.h, or it would raise below compile warning: drivers/mtd/spi-nor/core.c: In function ‘spi_nor_soft_reset’: drivers/mtd/spi-nor/core.c:2779:2: error: implicit declaration of function ‘usleep_range’ [-Werror=implicit-function-declaration] 2779 | usleep_range(SPI_NOR_SRST_SLEEP_MIN, SPI_NOR_SRST_SLEEP_MAX); | ^~~~~~~~~~~~ Fixes: d73ee753 ("mtd: spi-nor: core: perform a Soft Reset on shutdown") Signed-off-by:Zeng Heng <zengheng4@huawei.com> Signed-off-by:
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- 23 Jan, 2023 2 commits
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Daniel Golle authored
The mx35lf1ge4ab_get_eccsr() function uses an SPI DMA operation to read the eccsr, hence the buffer should not be on stack. Since commit 38058322 ("spi: spi-mem: Add extra sanity checks on the op param") the kernel emmits a warning and blocks such operations. Use the scratch buffer to get eccsr instead of trying to directly read into a stack-allocated variable. Signed-off-by:
Daniel Golle <daniel@makrotopia.org> Reviewed-by:
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Miquel Raynal authored
Describe the continuous read nand_chip fields to avoid the following htmldocs warning: include/linux/mtd/rawnand.h:1325: warning: Function parameter or member 'cont_read' not described in 'nand_chip' Reported-by:
Stephen Rothwell <sfr@canb.auug.org.au> Fixes: 003fe4b9 ("mtd: rawnand: Support for sequential cache reads") Signed-off-by:
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- 13 Jan, 2023 4 commits
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Randy Dunlap authored
These comments are not quite in kernel-doc format and they don't need to be, so just use "/*" comment markers for them. This prevents these kernel-doc warnings: drivers/mtd/nand/raw/vf610_nfc.c:210: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * Read accessor for internal SRAM buffer drivers/mtd/nand/raw/vf610_nfc.c:245: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * Write accessor for internal SRAM buffer Signed-off-by:
Randy Dunlap <rdunlap@infradead.org> Cc: Stefan Agner <stefan@agner.ch> Cc: Miquel Raynal <miquel.raynal@bootlin.com> Cc: Richard Weinberger <richard@nod.at> Cc: Vignesh Raghavendra <vigneshr@ti.com> Cc: linux-mtd@lists.infradead.org Signed-off-by:
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JaimeLiao authored
Add support for sequential cache reads for controllers using the generic core helpers for their fast read/write helpers. Sequential reads may reduce the overhead when accessing physically continuous data by loading in cache the next page while the previous page gets sent out on the NAND bus. The ONFI specification provides the following additional commands to handle sequential cached reads: * 0x31 - READ CACHE SEQUENTIAL: Requires the NAND chip to load the next page into cache while keeping the current cache available for host reads. * 0x3F - READ CACHE END: Tells the NAND chip this is the end of the sequential cache read, the current cache shall remain accessible for the host but no more internal cache loading operation is required. On the bus, a multi page read operation is currently handled like this: 00 -- ADDR1 -- 30 -- WAIT_RDY (tR+tRR) -- DATA1_IN 00 -- ADDR2 -- 30 -- WAIT_RDY (tR+tRR) -- DATA2_IN 00 -- ADDR3 -- 30 -- WAIT_RDY (tR+tRR) -- DATA3_IN Sequential cached reads may instead be achieved with: 00 -- ADDR1 -- 30 -- WAIT_RDY (tR) -- \ 31 -- WAIT_RDY (tRCBSY+tRR) -- DATA1_IN \ 31 -- WAIT_RDY (tRCBSY+tRR) -- DATA2_IN \ 3F -- WAIT_RDY (tRCBSY+tRR) -- DATA3_IN Below are the read speed test results with regular reads and sequential cached reads, on NXP i.MX6 VAR-SOM-SOLO in mapping mode with a NAND chip characterized with the following timings: * tR: 20 µs * tRCBSY: 5 µs * tRR: 20 ns and the following geometry: * device size: 2 MiB * eraseblock size: 128 kiB * page size: 2 kiB ============= Normal read @ 33MHz ================= mtd_speedtest: eraseblock read speed is 15633 KiB/s mtd_speedtest: page read speed is 15515 KiB/s mtd_speedtest: 2 page read speed is 15398 KiB/s =================================================== ========= Sequential cache read @ 33MHz =========== mtd_speedtest: eraseblock read speed is 18285 KiB/s mtd_speedtest: page read speed is 15875 KiB/s mtd_speedtest: 2 page read speed is 16253 KiB/s =================================================== We observe an overall speed improvement of about 5% when reading 2 pages, up to 15% when reading an entire block. This is due to the ~14us gain on each additional page read (tR - (tRCBSY + tRR)). Co-developed-by:
JaimeLiao <jaimeliao.tw@gmail.com> Tested-by:
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Miquel Raynal authored
Add an empty envelope just to show how to add additional checks for new operations. This is going to be used for sequential cached reads, which require the page size to be known (and the discovery to be over), hence the "late" designation. Signed-off-by:
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Miquel Raynal authored
Instead of checking if a pattern is supported each time we need it, let's create a bitfield that only the core would be allowed to fill at startup time. The core and the individual drivers may then use it in order to check what operation they should use. This bitfield is supposed to grow over time. Signed-off-by:
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- 07 Jan, 2023 3 commits
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Arnd Bergmann authored
With the TMIO MFD drivers gone, the NAND support is also obsolete and can be removed. Cc: Miquel Raynal <miquel.raynal@bootlin.com> Cc: Richard Weinberger <richard@nod.at> Cc: Vignesh Raghavendra <vigneshr@ti.com> Cc: linux-mtd@lists.infradead.org Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
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Uwe Kleine-König authored
Up to now the pasemi nand driver only supported a single device instance. However the check for that was racy because two parallel calls of pasemi_nand_probe() could pass the check if (pasemi_nand_mtd) return -ENODEV; before any of them assigns a non-NULL value to it. So rework the driver to make use of per-device driver data. As an intended side effect the driver can bind more than one device and also gets rid of the check if (!pasemi_nand_mtd) return 0; in the remove callback that could only ever trigger after the above race happened. Signed-off-by:
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by:
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Tudor Ambarus authored
My professional email will change and the microchip one will bounce after mid-november of 2022. Update the MAINTAINERS file, the YAML bindings, MODULE_AUTHOR entries and author mentions, and add an entry in the .mailmap file. Signed-off-by:
Tudor Ambarus <tudor.ambarus@microchip.com> Acked-by:
Mark Brown <broonie@kernel.org> Acked-by:
Nicolas Ferre <nicolas.ferre@microchip.com> Acked-by:
Herbert Xu <herbert@gondor.apana.org.au> Acked-by:
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- 02 Jan, 2023 9 commits
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Arnd Bergmann authored
Building with -Werror=override-init reveals that two patches added the same device ID table to this driver: drivers/mtd/devices/mtd_dataflash.c:946:27: error: initialized field overwritten [-Werror=override-init] 946 | .id_table = dataflash_spi_ids, | ^~~~~~~~~~~~~~~~~ drivers/mtd/devices/mtd_dataflash.c:946:27: note: (near initialization for 'dataflash_driver.id_table') Remove one of the copies. Fixes: 27a030e8 ("mtd: dataflash: Add device-tree SPI IDs") Fixes: ac4f8348 ("mtd: dataflash: Add SPI ID table") Signed-off-by: -
Samuel Holland authored
The previous code assigned to the wrong structure member. Fixes: c66811e6 ("mtd: nand: sunxi: switch to mtd_ooblayout_ops") Signed-off-by:
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Samuel Holland authored
Each chip is required to have a unique CS number ("reg" property) in the range 0-7, so there is no need to separately count the number of chips. Signed-off-by: -
Samuel Holland authored
sunxi_nand->nsels cannot be zero, so the second check implies the first. Signed-off-by:
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Samuel Holland authored
If a chip fails to initialize, we need to clean up any chips that were already initialized/registered. Fixes: 1fef62c1 ("mtd: nand: add sunxi NAND flash controller support") Signed-off-by:
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Aviram Dali authored
A missing layouts were added to the driver to support NAND flashes with ECC layouts of 12 or 16 with page sized of 2048, 4096 or 8192. Usually theses are rare layouts, but in Marvell AC5 driver, the ECC level is set according to the spare area, so we may use these layouts more frequently. Signed-off-by:
Aviram Dali <aviramd@marvell.com> Signed-off-by:
Vadym Kochan <vadym.kochan@plvision.eu> Signed-off-by:
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Arnd Bergmann authored
When MTD or MTD_CFI_GEOMETRY is disabled, the spi-intel driver fails to build, as it includes the shared CFI header: include/linux/mtd/cfi.h:62:2: error: #warning No CONFIG_MTD_CFI_Ix selected. No NOR chip support can work. [-Werror=cpp] 62 | #warning No CONFIG_MTD_CFI_Ix selected. No NOR chip support can work. linux/mtd/spi-nor.h does not actually need to include cfi.h, so remove the inclusion here to fix the warning. This uncovers a missing #include in spi-nor/core.c so add that there to prevent a different build issue. Fixes: e23e5a05 ("mtd: spi-nor: intel-spi: Convert to SPI MEM") Signed-off-by:
Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by:
Tokunori Ikegami <ikegami.t@gmail.com> Acked-by:
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Mikhail Zhilkin authored
This fixes the following compile error on mips architecture with clang version 16.0.0 reported by the 0-DAY CI Kernel Test Service: ld.lld: error: undefined symbol: __udivdi3 referenced by scpart.c mtd/parsers/scpart.o:(scpart_parse) in archive drivers/built-in.a As a workaround this makes 'offs' a 32-bit type. This is enough, because the mtd containing partition table practically does not exceed 1 MB. We can revert this when the [Link] has been resolved. Link: https://github.com/ClangBuiltLinux/linux/issues/1635 Fixes: 9b78ef0c ("mtd: parsers: add support for Sercomm partitions") Reported-by:
Mikhail Zhilkin <csharper2005@gmail.com> Signed-off-by:
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Yuan Can authored
The parts needs to be freed with all its elements, otherwise it will be leaked. Fixes: 00a35880 ("mtd: parsers: add TP-Link SafeLoader partitions table parser") Signed-off-by:
Yuan Can <yuancan@huawei.com> Reviewed-by:
Dan Carpenter <error27@gmail.com> Signed-off-by:
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- 01 Jan, 2023 3 commits
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Linus Torvalds authored
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git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds authored
Pull perf fixes from Borislav Petkov: - Pass only an initialized perf event attribute to the LSM hook - Fix a use-after-free on the perf syscall's error path - A potential integer overflow fix in amd_core_pmu_init() - Fix the cgroup events tracking after the context handling rewrite - Return the proper value from the inherit_event() function on error * tag 'perf_urgent_for_v6.2_rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: perf/core: Call LSM hook after copying perf_event_attr perf: Fix use-after-free in error path perf/x86/amd: fix potential integer overflow on shift of a int perf/core: Fix cgroup events tracking perf core: Return error pointer if inherit_event() fails to find pmu_ctx
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git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds authored
Pull x86 fixes from Borislav Petkov: - Two fixes to correct how kprobes handles INT3 now that they're added by other functionality like the rethunks and not only kgdb - Remove __init section markings of two functions which are referenced by a function in the .text section * tag 'x86_urgent_for_v6.2_rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/kprobes: Fix optprobe optimization check with CONFIG_RETHUNK x86/kprobes: Fix kprobes instruction boudary check with CONFIG_RETHUNK x86/calldepth: Fix incorrect init section references
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