- 12 Mar, 2020 3 commits
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Veerabhadrarao Badiganti authored
Remove the redundant _mem suffix for SDHC reg names. For SDcard instance, no need supply reg names since hc reg map is accessed with index. So remove reg names for SDcard. Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org> Link: https://lore.kernel.org/r/1583946863-24308-2-git-send-email-vbadigan@codeaurora.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Veerabhadrarao Badiganti authored
Enabling CQE support for eMMC by supplying the correct reg name and flag which indicates CQE support. Also remove the redundant _mem suffix for reg names. Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org> Link: https://lore.kernel.org/r/1583946863-24308-1-git-send-email-vbadigan@codeaurora.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Srinivas Kandagatla authored
Add fastrpc device node for adsp with one compute bank. Tested-by: Loic Poulain <loic.poulain@linaro.org> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Link: https://lore.kernel.org/r/20200310175452.7503-1-srinivas.kandagatla@linaro.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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- 10 Mar, 2020 1 commit
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Venkata Narendra Kumar Gutta authored
Add sm8250 devicetree file for SM8250 SoC and SM8250 MTP platform. This file adds the basic nodes like cpu, psci and other required configuration for booting up to the serial console. Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20200310050910.506854-1-vkoul@kernel.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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- 09 Mar, 2020 1 commit
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Bjorn Andersson authored
Disable Coresight funnel 4 and 5, for now, as these causes the MTP to crash when clock late_initcall disables unused clocks. Reviewed-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20200308055445.1992189-1-bjorn.andersson@linaro.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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- 07 Mar, 2020 2 commits
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Srinivas Kandagatla authored
This patch adds support UART0, I2C0, I2C1 and SPI0 available on Low Speed expansion connector. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Link: https://lore.kernel.org/r/20200305145344.14670-5-srinivas.kandagatla@linaro.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Loic Poulain authored
As specified in the smd-rpm-regulator binding and confirmed by the pm8616 device specification, there is no vdd_l5. l5 vdd comes from vdd_l4_l5_l6. Fix that (though it does not cause any issue since the supply is not requested). Signed-off-by: Loic Poulain <loic.poulain@linaro.org> Link: https://lore.kernel.org/r/1583516368-29593-1-git-send-email-loic.poulain@linaro.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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- 06 Mar, 2020 7 commits
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Rajeshwari authored
To enable kernel critical shutdown feature added critical trip point to all non CPU sensors to perform shutdown in orderly manner. Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Rajeshwari <rkambl@codeaurora.org> Link: https://lore.kernel.org/r/1583394547-12779-2-git-send-email-rkambl@codeaurora.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Amit Kucheria authored
"arm,armv8" compatible should only be used for software models. Replace it with the real cpu type. Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Link: https://lore.kernel.org/r/0535d640e9cd01887b5532f893ce4d61feca6d6d.1583445235.git.amit.kucheria@linaro.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Sibi Sankar authored
Add Operation State Manager (OSM) L3 interconnect provider on SC7180 SoCs. Acked-by: Georgi Djakov <georgi.djakov@linaro.org> Reviewed-by: Evan Green <evgreen@chromium.org> Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/20200227105632.15041-8-sibis@codeaurora.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Sibi Sankar authored
Add Operation State Manager (OSM) L3 interconnect provider on SDM845 SoCs. Acked-by: Georgi Djakov <georgi.djakov@linaro.org> Reviewed-by: Evan Green <evgreen@chromium.org> Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/20200227105632.15041-7-sibis@codeaurora.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Odelu Kukatla authored
Add the DT nodes for the network-on-chip interconnect buses found on sc7180-based platforms. Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org> Link: https://lore.kernel.org/r/1582646384-1458-4-git-send-email-okukatla@codeaurora.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Bjorn Andersson authored
With support for the MSM8996 UFS PHY added to the common QMP driver, migrate the DTS to use the common QMP binding. Reviewed-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20200125001234.435384-1-bjorn.andersson@linaro.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Bjorn Andersson authored
The CLKREF clocks in GCC are parented by RPM_SMD_LN_BB_CLK, through the CXO2 pad. Wire this up so that this is properly enabled when need by the various PHYs. Reviewed-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20200106080546.3192125-3-bjorn.andersson@linaro.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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- 05 Mar, 2020 2 commits
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David Dai authored
Add the DT nodes for each of the Network-On-Chip interconnect buses found on SDM845 based platform and redefine the rsc_hlos child node as a bcm-voter device to better represent the hardware. Reviewed-by: Evan Green <evgreen@chromium.org> Acked-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: David Dai <daidavid1@codeaurora.org> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org> Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/20200209183411.17195-7-sibis@codeaurora.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Douglas Anderson authored
This is just like commit a1875bf9 ("arm64: dts: qcom: sdm845: Add unit name to soc node") but for sc7180. For reference, the warning being fixed was: Warning (unit_address_vs_reg): /soc: node has a reg or ranges property, but no unit name Reviewed-by: Stephen Boyd <swboyd@chromium.org> Fixes: 90db71e4 ("arm64: dts: sc7180: Add minimal dts/dtsi files for SC7180 soc") Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20200304105638.1.I9ea0d337fcb927f52a28b20613b2377b6249c222@changeidSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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- 28 Feb, 2020 6 commits
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Amit Kucheria authored
The qcom-tsens binding requires a SoC-specific and a TSENS family-specific binding to be specified in the compatible string. Since them family-specific binding is not listed in the .dtsi file, we see the following warnings in 'make dtbs_check'. Fix them. /home/amit/work/builds/build-aarch64/arch/arm64/boot/dts/qcom/msm8996-mtp.dt.yaml: thermal-sensor@4a9000: compatible: ['qcom,msm8996-tsens'] is not valid under any of the given schemas (Possible causes of the failure): /home/amit/work/builds/build-aarch64/arch/arm64/boot/dts/qcom/msm8996-mtp.dt.yaml: thermal-sensor@4a9000: compatible: ['qcom,msm8996-tsens'] is too short /home/amit/work/builds/build-aarch64/arch/arm64/boot/dts/qcom/msm8996-mtp.dt.yaml: thermal-sensor@4a9000: compatible:0: 'qcom,msm8996-tsens' is not one of ['qcom,msm8916-tsens', 'qcom,msm8974-tsens'] /home/amit/work/builds/build-aarch64/arch/arm64/boot/dts/qcom/msm8996-mtp.dt.yaml: thermal-sensor@4a9000: compatible:0: 'qcom,msm8996-tsens' is not one of ['qcom,msm8976-tsens', 'qcom,qcs404-tsens'] /home/amit/work/builds/build-aarch64/arch/arm64/boot/dts/qcom/msm8996-mtp.dt.yaml: thermal-sensor@4ad000: compatible: ['qcom,msm8996-tsens'] is not valid under any of the given schemas (Possible causes of the failure): /home/amit/work/builds/build-aarch64/arch/arm64/boot/dts/qcom/msm8996-mtp.dt.yaml: thermal-sensor@4ad000: compatible: ['qcom,msm8996-tsens'] is too short /home/amit/work/builds/build-aarch64/arch/arm64/boot/dts/qcom/msm8996-mtp.dt.yaml: thermal-sensor@4ad000: compatible:0: 'qcom,msm8996-tsens' is not one of ['qcom,msm8916-tsens', 'qcom,msm8974-tsens'] /home/amit/work/builds/build-aarch64/arch/arm64/boot/dts/qcom/msm8996-mtp.dt.yaml: thermal-sensor@4ad000: compatible:0: 'qcom,msm8996-tsens' is not one of ['qcom,msm8976-tsens', 'qcom,qcs404-tsens'] Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/ebaa801adade53c567857db2f74af7d2e00f935b.1582871139.git.amit.kucheria@linaro.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Amit Kucheria authored
The qcom-tsens binding requires a SoC-specific and a TSENS family-specific binding to be specified in the compatible string. Since them family-specific binding is not listed in the .dtsi file, we see the following warnings in 'make dtbs_check'. Fix them. /home/amit/work/builds/build-aarch64/arch/arm64/boot/dts/qcom/msm8916-mtp.dt.yaml: thermal-sensor@4a9000: compatible: ['qcom,msm8916-tsens'] is not valid under any of the given schemas (Possible causes of the failure): /home/amit/work/builds/build-aarch64/arch/arm64/boot/dts/qcom/msm8916-mtp.dt.yaml: thermal-sensor@4a9000: compatible: ['qcom,msm8916-tsens'] is too short /home/amit/work/builds/build-aarch64/arch/arm64/boot/dts/qcom/msm8916-mtp.dt.yaml: thermal-sensor@4a9000: compatible:0: 'qcom,msm8916-tsens' is not one of ['qcom,msm8976-tsens', 'qcom,qcs404-tsens'] /home/amit/work/builds/build-aarch64/arch/arm64/boot/dts/qcom/msm8916-mtp.dt.yaml: thermal-sensor@4a9000: compatible:0: 'qcom,msm8916-tsens' is not one of ['qcom,msm8996-tsens', 'qcom,msm8998-tsens', 'qcom,sdm845-tsens'] Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/8cea8c0036703bcc4dd2b87a8ca3913c4a28d16e.1582871139.git.amit.kucheria@linaro.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Bjorn Andersson authored
Bring in the Truly display and enable the DSI channels to make the mdss/gpu probe, even though we're lacking LABIB, preventing us from seeing anything on the screen. Tested-by: Vivek Gautam <vivek.gautam@codeaurora.org> Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Link: https://lore.kernel.org/r/20190513210747.22429-1-bjorn.andersson@linaro.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Sivaprakash Murugesan authored
add i2c, spi, crypto, rng, watchdog, peripheral nodes, also add support for wcss Q6 remoteproc driver and enable hw mutex, smem, mailbox, smp2p and rpmsg drivers Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Link: https://lore.kernel.org/r/1582199446-29890-1-git-send-email-sivaprak@codeaurora.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Matthias Kaehlcke authored
Per convention device nodes for SC7180 should be ordered by address. This is currently not the case for the venus node, move it to the correct position. Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Link: https://lore.kernel.org/r/20200227092649.v3.1.I15e0f7eff0c67a2b49d4992f9d80fc1d2fdadf63@changeidSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Stanimir Varbanov authored
Move all pmdomain and clock resources to Venus DT node. And make possible to support dynamic core assignment on v4. Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org> Link: https://lore.kernel.org/r/20200106154929.4331-12-stanimir.varbanov@linaro.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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- 26 Feb, 2020 7 commits
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Harigovindan P authored
Add display, DSI hardware DT nodes for sc7180. Tested-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Co-developed-by: Kalyan Thota <kalyan_t@codeaurora.org> Signed-off-by: Kalyan Thota <kalyan_t@codeaurora.org> Signed-off-by: Harigovindan P <harigovi@codeaurora.org> Link: https://lore.kernel.org/r/1580825707-27115-1-git-send-email-harigovi@codeaurora.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Sandeep Maheswaram authored
The phy reset entries were incorrect.so swapped them. Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> Link: https://lore.kernel.org/r/1581506488-26881-5-git-send-email-sanm@codeaurora.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Dikshita Agarwal authored
This adds Venus firmware subnode for non-TZ platform. Reviewed-by: Stanimir Varbanov <stanimir.varbanov@linaro.org> Signed-off-by: Dikshita Agarwal <dikshita@codeaurora.org> Link: https://lore.kernel.org/r/1579006416-11599-5-git-send-email-dikshita@codeaurora.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Dikshita Agarwal authored
This adds Venus video codec DT node for sc7180. Reviewed-by: Stanimir Varbanov <stanimir.varbanov@linaro.org> Signed-off-by: Dikshita Agarwal <dikshita@codeaurora.org> Link: https://lore.kernel.org/r/1579006416-11599-2-git-send-email-dikshita@codeaurora.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Rajendra Nayak authored
SC7180 has 2 big cores and 6 LITTLE ones in a single cluster with shared L3. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Link: https://lore.kernel.org/r/1578393926-5052-3-git-send-email-rnayak@codeaurora.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Rajendra Nayak authored
Specify the relative CPU capacity of all SC7180 cpu cores. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Link: https://lore.kernel.org/r/1578393926-5052-2-git-send-email-rnayak@codeaurora.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Rajendra Nayak authored
Add dynamic power coefficients for Silver and Gold CPUs on SC7180 SoC. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Link: https://lore.kernel.org/r/1578393926-5052-1-git-send-email-rnayak@codeaurora.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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- 25 Feb, 2020 11 commits
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Sricharan R authored
Add initial device tree support for the Qualcomm IPQ6018 SoC and CP01 evaluation board. Co-developed-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Co-developed-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Link: https://lore.kernel.org/r/1579439601-14810-5-git-send-email-sricharan@codeaurora.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Sricharan R authored
Document the new ipq6018 SOC/board device tree bindings. Co-developed-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org> Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org> Co-developed-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Link: https://lore.kernel.org/r/1579439601-14810-4-git-send-email-sricharan@codeaurora.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Taniya Das authored
Add the display, video & graphics clock controller nodes supported on SC7180. NOTE: the dispcc needs input clocks from various PHYs that aren't in the device tree yet. For now we'll leave these stubbed out with <0>, which is apparently the magic way to do this. These clocks aren't really "optional" and this stubbing out method is apparently the best way to handle it. Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20200203103049.v4.15.I1a4b93fb005791e29a9dcf288fc8bd459a555a59@changeidSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Douglas Anderson authored
We're transitioning over to requiring the Qualcomm Video Clock Controller to specify all the input clocks. Let's add the one input clock for the videocc for sdm845. NOTE: Until the Linux driver for sdm845's video is updated, this clock will not actually be used in Linux. It will continue to use global clock names to match things up. Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20200203103049.v4.14.Id0599319487f075808baba7cba02c4c3c486dc80@changeidSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Douglas Anderson authored
We're transitioning over to requiring the Qualcomm GPU Clock Controller to specify all the input clocks. Let's add them for sdm845. As part of this we've decided that the xo clock should be referred to in the bindings as "bi_tcxo". Change the dts. NOTE: Until the Linux driver for sdm845's gpucc is updated, these clocks will not actually be used in Linux. It will continue to use global clock names to match things up. Of course, Linux didn't use the old "xo" clock anyway. Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20200203103049.v4.8.If8596faf02408cef4bb9f52296b911eb9ba49287@changeidSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Douglas Anderson authored
We're transitioning over to requiring the Qualcomm Display Clock Controller to specify all the input clocks. Let's add them for sdm845. NOTES: - Until the Linux driver for sdm845's dispcc is updated, these clocks will not actually be used in Linux. It will continue to use global clock names to match things up. - Although the clocks from the DP PHY are required, the DP PHY isn't represented in the dts yet. Apparently the magic for this is just to use <0>. Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20200203103049.v4.3.Ie80fa74e1774f4317d80d70d30ef4b78f16cc8df@changeidSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Douglas Anderson authored
As per the bindings, the SDHCI controller should have a SoC-specific compatible string in addition to the generic version-based one. Add it. Reviewed-by: Vinod Koul <vkoul@kernel.org> Fixes: 7241ab94 ("arm64: dts: qcom: qcs404: Add sdcc1 node") Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20200127082331.1.I402470e4a162d69fde47ee2ea708b15bde9751f9@changeidSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Christian Lamparter authored
This patch adds the gpio-ranges property to almost all of the Qualcomm ARM platforms that utilize the pinctrl-msm framework. The gpio-ranges property is part of the gpiolib subsystem. As a result, the binding text is available in section "2.1 gpio- and pin-controller interaction" of Documentation/devicetree/bindings/gpio/gpio.txt For more information please see the patch titled: "pinctrl: msm: fix gpio-hog related boot issues" from this series. Reported-by: Sven Eckelmann <sven.eckelmann@openmesh.com> Tested-by: Sven Eckelmann <sven.eckelmann@openmesh.com> [ipq4019] Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Christian Lamparter <chunkeey@gmail.com> Tested-by: Robert Marko <robert.marko@sartura.hr> [ipq4019] Cc: Luka Perkov <luka.perkov@sartura.hr> Signed-off-by: Robert Marko <robert.marko@sartura.hr> Link: https://lore.kernel.org/r/20200108125455.308969-2-robert.marko@sartura.hrSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Stephen Boyd authored
Some platforms don't want to use the pmic power key as the power key event. Add a label so platforms can easily reference and mark this node as status = "disabled". Reviewed-by: Douglas Anderson <dianders@chromium.org> Cc: Kiran Gunda <kgunda@codeaurora.org> Cc: Rajendra Nayak <rnayak@codeaurora.org> Cc: Douglas Anderson <dianders@chromium.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20200115025314.3054-1-swboyd@chromium.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Alexandre Courbot authored
Cheza boards require this node to probe, so add it. Reviewed-by: Stanimir Varbanov <stanimir.varbanov@linaro.org> Signed-off-by: Alexandre Courbot <acourbot@chromium.org> Link: https://lore.kernel.org/r/20200108032623.113921-1-acourbot@chromium.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Bjorn Andersson authored
Enable the two PCIe controllers found on the Dragonboard845c. Tested-by: Julien Massot <jmassot@softbankrobotics.com> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20191107002247.1127689-4-bjorn.andersson@linaro.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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