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Commit 06e78df3 authored by Olof Johansson's avatar Olof Johansson
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Merge tag 'imx-dt64-5.5' of... 

Merge tag 'imx-dt64-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt

i.MX arm64 device tree changes for 5.5:
 - Add the initial support for a new arm64 family SoC from NXP:
   S32V234 ("Treerunner") vision microprocessors which are targeted for
   high-performance, computationally intensive vision and sensor fusion
   applications that require automotive safety levels.
 - New board support: i.MX8MN LPDDR4 EVK, i.MX8QXP Colibri and
   S32V234 EVB.
 - A series of patch from Andrey Smirnov to improve zii-ultra support by
   fixing regulator and adding accelerometer, switch watchdog.
 - Add system counter device and enable cpuidle support for i.MX8MN.
 - Move usdhc clocks assignment from SoC to board level DTS for
   i.MX8 based boards.
 - Add PCA6416 on I2C3 bus for imx8mm-evk, and enable SCU key for
   imx8qxp-mek board.
 - Enable GPU passive throttling on i.MX8MQ SoC, and add DDR PMU device
   for i.MX8MN.
 - A series from Fabio Estevam to fix DTC W=1 warnings for LS1028A device.
 - Update the clock providers for the Mali DP500 and '#clock-cells' of
   DPCLK node for LS1028A SoC.
 - Misc small updates on various boards.

* tag 'imx-dt64-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (40 commits)
  arm64: dts: imx8mn-evk: Remove invalid Atheros properties
  arm64: dts: freescale: add initial support for colibri imx8x
  arm64: dts: ls1028a: Fix tmu unit address
  arm64: dts: ls1028a: Move thermal-zone out of SoC
  arm64: dts: ls1028a-qds: Remove unnecessary #address-cells/#size-cells
  arm64: dts: imx8mn: Remove duplicated machine compatible
  arm64: dts: imx8mm: Remove duplicated machine compatible
  arm64: dts: imx8mq-evk: Add remote control
  arm64: dts: imx8mn: Add LPDDR4 EVK board support
  arm64: dts: imx8mn: Create EVK dtsi file for common use
  arm64: dts: imx8mn: Move usdhc clocks assignment to board DT
  arm64: dts: imx8mm: Move usdhc clocks assignment to board DT
  arm64: dts: imx8mq: Move usdhc clocks assignment to board DT
  arm64: dts: imx8qxp: Move usdhc clocks assignment to board DT
  arm64: dts: fsl: Add device tree for S32V234-EVB
  arm64: dts: imx8mm-evk: Assigned clocks for audio plls
  arm64: dts: zii-ultra: Add node for switch watchdog
  arm64: dts: zii-ultra: Add node for accelerometer
  arm64: dts: zii-ultra: Fix regulator-3p3-main's name
  arm64: dts: zii-ultra: Fix regulator-vsd-3v3's vin-supply
  ...

Link: https://lore.kernel.org/r/20191105150315.15477-5-shawnguo@kernel.orgSigned-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 405b7b27 227125fe
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Showing with 1432 additions and 384 deletions
arch/arm64/boot/dts/freescale/Makefile
View file @ 06e78df3
......@@ -22,6 +22,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-hummingboard-pulse.dtb
......@@ -31,4 +32,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mq-pico-pi.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
View file @ 06e78df3
......@@ -194,8 +194,6 @@ sgtl5000: audio-codec@a {
};
fpga@66 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,ls1028aqds-fpga", "fsl,fpga-qixis-i2c",
"simple-mfd";
reg = <0x66>;
......
arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
View file @ 06e78df3
......@@ -184,3 +184,7 @@ &sai4 {
&sata {
status = "okay";
};
&usb1 {
dr_mode = "otg";
};
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
View file @ 06e78df3
......@@ -82,22 +82,8 @@ osc_27m: clock-osc-27m {
dpclk: clock-controller@f1f0000 {
compatible = "fsl,ls1028a-plldig";
reg = <0x0 0xf1f0000 0x0 0xffff>;
#clock-cells = <1>;
clocks = <&osc_27m>;
};
aclk: clock-axi {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <650000000>;
clock-output-names= "aclk";
};
pclk: clock-apb {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <650000000>;
clock-output-names= "pclk";
clocks = <&osc_27m>;
};
reboot {
......@@ -142,6 +128,37 @@ its: gic-its@6020000 {
};
};
thermal-zones {
core-cluster {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 0>;
trips {
core_cluster_alert: core-cluster-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
core_cluster_crit: core-cluster-crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&core_cluster_alert>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
soc: soc {
compatible = "simple-bus";
#address-cells = <2>;
......@@ -542,7 +559,7 @@ sai4: audio-controller@f130000 {
status = "disabled";
};
tmu: tmu@1f00000 {
tmu: tmu@1f80000 {
compatible = "fsl,qoriq-tmu";
reg = <0x0 0x1f80000 0x0 0x10000>;
interrupts = <0 23 0x4>;
......@@ -594,37 +611,6 @@ tmu: tmu@1f00000 {
#thermal-sensor-cells = <1>;
};
thermal-zones {
core-cluster {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 0>;
trips {
core_cluster_alert: core-cluster-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
core_cluster_crit: core-cluster-crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&core_cluster_alert>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
pcie@1f0000000 { /* Integrated Endpoint Root Complex */
compatible = "pci-host-ecam-generic";
reg = <0x01 0xf0000000 0x0 0x100000>;
......@@ -679,7 +665,8 @@ malidp0: display@f080000 {
interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
<0 223 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "DE", "SE";
clocks = <&dpclk 0>, <&aclk>, <&aclk>, <&pclk>;
clocks = <&dpclk>, <&clockgen 2 2>, <&clockgen 2 2>,
<&clockgen 2 2>;
clock-names = "pxlclk", "mclk", "aclk", "pclk";
arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
arm,malidp-arqos-value = <0xd000d000>;
......
arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
View file @ 06e78df3
......@@ -122,6 +122,10 @@ qflash1: flash@1 {
};
};
&usb1 {
dr_mode = "otg";
};
#include "fsl-ls1046-post.dtsi"
&fman0 {
......
arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
View file @ 06e78df3
......@@ -95,5 +95,6 @@ &usb0 {
};
&usb1 {
dr_mode = "otg";
status = "okay";
};
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
View file @ 06e78df3
......@@ -586,6 +586,7 @@ esdhc0: esdhc@2140000 {
reg = <0x0 0x2140000 0x0 0x10000>;
interrupts = <0 28 0x4>; /* Level high type */
clocks = <&clockgen 4 1>;
dma-coherent;
voltage-ranges = <1800 1800 3300 3300>;
sdhci,auto-cmd12;
little-endian;
......@@ -598,6 +599,7 @@ esdhc1: esdhc@2150000 {
reg = <0x0 0x2150000 0x0 0x10000>;
interrupts = <0 63 0x4>; /* Level high type */
clocks = <&clockgen 4 1>;
dma-coherent;
voltage-ranges = <1800 1800 3300 3300>;
sdhci,auto-cmd12;
broken-cd;
......
arch/arm64/boot/dts/freescale/imx8mm-evk.dts
View file @ 06e78df3
......@@ -62,6 +62,8 @@ sound-wm8524 {
cpudai: simple-audio-card,cpu {
sound-dai = <&sai3>;
dai-tdm-slot-num = <2>;
dai-tdm-slot-width = <32>;
};
simple-audio-card,codec {
......@@ -94,68 +96,6 @@ ethphy0: ethernet-phy@0 {
};
};
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
status = "okay";
};
&snvs_pwrkey {
status = "okay";
};
&uart2 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&usbotg1 {
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
usb-role-switch;
status = "okay";
port {
usb1_drd_sw: endpoint {
remote-endpoint = <&typec1_dr_sw>;
};
};
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
bus-width = <4>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
......@@ -306,6 +246,86 @@ typec1_con: connector {
};
};
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
pca6416: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
};
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
status = "okay";
};
&snvs_pwrkey {
status = "okay";
};
&uart2 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&usbotg1 {
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
usb-role-switch;
status = "okay";
port {
usb1_drd_sw: endpoint {
remote-endpoint = <&typec1_dr_sw>;
};
};
};
&usdhc2 {
assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
bus-width = <4>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&usdhc3 {
assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
......@@ -355,6 +375,13 @@ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
>;
};
pinctrl_pmic: pmicirq {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
......
arch/arm64/boot/dts/freescale/imx8mm.dtsi
View file @ 06e78df3
......@@ -12,7 +12,6 @@
#include "imx8mm-pinfunc.h"
/ {
compatible = "fsl,imx8mm";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
......@@ -426,7 +425,7 @@ gpr: iomuxc-gpr@30340000 {
};
ocotp: ocotp-ctrl@30350000 {
compatible = "fsl,imx8mm-ocotp", "fsl,imx7d-ocotp", "syscon";
compatible = "fsl,imx8mm-ocotp", "syscon";
reg = <0x30350000 0x10000>;
clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>;
/* For nvmem subnodes */
......@@ -479,14 +478,18 @@ clk: clock-controller@30380000 {
<&clk IMX8MM_CLK_AUDIO_AHB>,
<&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,
<&clk IMX8MM_SYS_PLL3>,
<&clk IMX8MM_VIDEO_PLL1>;
<&clk IMX8MM_VIDEO_PLL1>,
<&clk IMX8MM_AUDIO_PLL1>,
<&clk IMX8MM_AUDIO_PLL2>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>,
<&clk IMX8MM_SYS_PLL1_800M>;
assigned-clock-rates = <0>,
<400000000>,
<400000000>,
<750000000>,
<594000000>;
<594000000>,
<393216000>,
<361267200>;
};
src: reset-controller@30390000 {
......@@ -698,8 +701,6 @@ usdhc1: mmc@30b40000 {
<&clk IMX8MM_CLK_NAND_USDHC_BUS>,
<&clk IMX8MM_CLK_USDHC1_ROOT>;
clock-names = "ipg", "ahb", "per";
assigned-clocks = <&clk IMX8MM_CLK_USDHC1>;
assigned-clock-rates = <400000000>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
bus-width = <4>;
......@@ -728,8 +729,6 @@ usdhc3: mmc@30b60000 {
<&clk IMX8MM_CLK_NAND_USDHC_BUS>,
<&clk IMX8MM_CLK_USDHC3_ROOT>;
clock-names = "ipg", "ahb", "per";
assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
assigned-clock-rates = <400000000>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
bus-width = <4>;
......
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
View file @ 06e78df3
......@@ -6,205 +6,18 @@
/dts-v1/;
#include "imx8mn.dtsi"
#include "imx8mn-evk.dtsi"
/ {
model = "NXP i.MX8MNano DDR4 EVK board";
compatible = "fsl,imx8mn-ddr4-evk", "fsl,imx8mn";
chosen {
stdout-path = &uart2;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&A53_0 {
cpu-supply = <&buck2_reg>;
};
&iomuxc {
pinctrl-names = "default";
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
>;
};
pinctrl_pmic: pmicirq {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
fsl,pins = <
MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
>;
};
pinctrl_usdhc2_gpio: usdhc2grpgpio {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
fsl,pins = <
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
fsl,pins = <
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
at803x,led-act-blind-workaround;
at803x,eee-disabled;
at803x,vddio-1p8v;
};
};
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic@4b {
compatible = "rohm,bd71847";
reg = <0x4b>;
......@@ -309,40 +122,10 @@ ldo6_reg: LDO6 {
};
};
&snvs_pwrkey {
status = "okay";
};
&uart2 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
bus-width = <4>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
&iomuxc {
pinctrl_pmic: pmicirq {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
>;
};
};
arch/arm64/boot/dts/freescale/imx8mn-evk.dts 0 → 100644
View file @ 06e78df3
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2019 NXP
*/
/dts-v1/;
#include "imx8mn.dtsi"
#include "imx8mn-evk.dtsi"
/ {
model = "NXP i.MX8MNano EVK board";
compatible = "fsl,imx8mn-evk", "fsl,imx8mn";
};
&A53_0 {
/delete-property/operating-points-v2;
};
&A53_1 {
/delete-property/operating-points-v2;
};
&A53_2 {
/delete-property/operating-points-v2;
};
&A53_3 {
/delete-property/operating-points-v2;
};
arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi 0 → 100644
View file @ 06e78df3
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2019 NXP
*/
#include "imx8mn.dtsi"
/ {
chosen {
stdout-path = &uart2;
};
gpio-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_led>;
status {
label = "yellow:status";
gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
};
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
};
&snvs_pwrkey {
status = "okay";
};
&uart2 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&usdhc2 {
assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
bus-width = <4>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&usdhc3 {
assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
>;
};
pinctrl_gpio_led: gpioledgrp {
fsl,pins = <
MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
fsl,pins = <
MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
>;
};
pinctrl_usdhc2_gpio: usdhc2grpgpio {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
fsl,pins = <
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
fsl,pins = <
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
};
arch/arm64/boot/dts/freescale/imx8mn.dtsi
View file @ 06e78df3
......@@ -11,7 +11,6 @@
#include "imx8mn-pinfunc.h"
/ {
compatible = "fsl,imx8mn";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
......@@ -43,6 +42,19 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;
idle-states {
entry-method = "psci";
cpu_pd_wait: cpu-pd-wait {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010033>;
local-timer-stop;
entry-latency-us = <1000>;
exit-latency-us = <700>;
min-residency-us = <2700>;
};
};
A53_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
......@@ -54,6 +66,7 @@ A53_0: cpu@0 {
operating-points-v2 = <&a53_opp_table>;
nvmem-cells = <&cpu_speed_grade>;
nvmem-cell-names = "speed_grade";
cpu-idle-states = <&cpu_pd_wait>;
};
A53_1: cpu@1 {
......@@ -65,6 +78,7 @@ A53_1: cpu@1 {
enable-method = "psci";
next-level-cache = <&A53_L2>;
operating-points-v2 = <&a53_opp_table>;
cpu-idle-states = <&cpu_pd_wait>;
};
A53_2: cpu@2 {
......@@ -76,6 +90,7 @@ A53_2: cpu@2 {
enable-method = "psci";
next-level-cache = <&A53_L2>;
operating-points-v2 = <&a53_opp_table>;
cpu-idle-states = <&cpu_pd_wait>;
};
A53_3: cpu@3 {
......@@ -87,6 +102,7 @@ A53_3: cpu@3 {
enable-method = "psci";
next-level-cache = <&A53_L2>;
operating-points-v2 = <&a53_opp_table>;
cpu-idle-states = <&cpu_pd_wait>;
};
A53_L2: l2-cache0 {
......@@ -320,7 +336,7 @@ gpr: iomuxc-gpr@30340000 {
};
ocotp: ocotp-ctrl@30350000 {
compatible = "fsl,imx8mn-ocotp", "fsl,imx7d-ocotp", "syscon";
compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon";
reg = <0x30350000 0x10000>;
clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>;
#address-cells = <1>;
......@@ -371,7 +387,7 @@ clk: clock-controller@30380000 {
};
src: reset-controller@30390000 {
compatible = "fsl,imx8mn-src", "syscon";
compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon";
reg = <0x30390000 0x10000>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
#reset-cells = <1>;
......@@ -428,6 +444,14 @@ pwm4: pwm@30690000 {
#pwm-cells = <2>;
status = "disabled";
};
system_counter: timer@306a0000 {
compatible = "nxp,sysctr-timer";
reg = <0x306a0000 0x20000>;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc_24m>;
clock-names = "per";
};
};
aips3: bus@30800000 {
......@@ -573,8 +597,6 @@ usdhc1: mmc@30b40000 {
<&clk IMX8MN_CLK_NAND_USDHC_BUS>,
<&clk IMX8MN_CLK_USDHC1_ROOT>;
clock-names = "ipg", "ahb", "per";
assigned-clocks = <&clk IMX8MN_CLK_USDHC1>;
assigned-clock-rates = <400000000>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
bus-width = <4>;
......@@ -603,8 +625,6 @@ usdhc3: mmc@30b60000 {
<&clk IMX8MN_CLK_NAND_USDHC_BUS>,
<&clk IMX8MN_CLK_USDHC3_ROOT>;
clock-names = "ipg", "ahb", "per";
assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
assigned-clock-rates = <400000000>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
bus-width = <4>;
......@@ -738,6 +758,12 @@ gic: interrupt-controller@38800000 {
interrupt-controller;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
ddr-pmu@3d800000 {
compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu";
reg = <0x3d800000 0x400000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
};
};
usbphynop1: usbphynop1 {
......
arch/arm64/boot/dts/freescale/imx8mq-evk.dts
View file @ 06e78df3
......@@ -48,6 +48,15 @@ buck2_reg: regulator-buck2 {
gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
states = <1000000 0x0
900000 0x1>;
regulator-boot-on;
regulator-always-on;
};
ir-receiver {
compatible = "gpio-ir-receiver";
gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ir>;
};
wm8524: audio-codec {
......@@ -115,15 +124,6 @@ ethphy0: ethernet-phy@0 {
};
};
&sai2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai2>;
assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_SAI2>;
assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL1_OUT>;
assigned-clock-rates = <0>, <24576000>;
status = "okay";
};
&gpio5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wifi_reset>;
......@@ -242,6 +242,29 @@ &pgc_gpu {
power-supply = <&sw1a_reg>;
};
&qspi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi>;
status = "okay";
n25q256a: flash@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q256a", "jedec,spi-nor";
spi-max-frequency = <29000000>;
};
};
&sai2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai2>;
assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_SAI2>;
assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL1_OUT>;
assigned-clock-rates = <0>, <24576000>;
status = "okay";
};
&snvs_pwrkey {
status = "okay";
};
......@@ -261,21 +284,9 @@ &usb_dwc3_1 {
status = "okay";
};
&qspi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi>;
status = "okay";
n25q256a: flash@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q256a", "jedec,spi-nor";
spi-max-frequency = <29000000>;
};
};
&usdhc1 {
assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
......@@ -289,6 +300,8 @@ &usdhc1 {
};
&usdhc2 {
assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
......@@ -340,6 +353,12 @@ MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
>;
};
pinctrl_ir: irgrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x4f
>;
};
pinctrl_pcie0: pcie0grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76
......
arch/arm64/boot/dts/freescale/imx8mq-hummingboard-pulse.dts
View file @ 06e78df3
......@@ -110,6 +110,8 @@ &uart3 { /* Mikrobus */
};
&usdhc2 {
assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
......
arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
View file @ 06e78df3
......@@ -780,6 +780,8 @@ &usb_dwc3_1 {
};
&usdhc1 {
assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
......@@ -790,6 +792,8 @@ &usdhc1 {
};
&usdhc2 {
assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
......
arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts
View file @ 06e78df3
......@@ -191,6 +191,8 @@ &uart2 {
};
&usdhc1 {
assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
assigned-clock-rates = <400000000>;
bus-width = <8>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
......
arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts
View file @ 06e78df3
......@@ -207,6 +207,8 @@ &uart1 { /* console */
};
&usdhc1 {
assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
......@@ -217,6 +219,8 @@ &usdhc1 {
};
&usdhc2 {
assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
......
arch/arm64/boot/dts/freescale/imx8mq-sr-som.dtsi
View file @ 06e78df3
......@@ -170,6 +170,8 @@ &uart4 { /* ublox BT */
};
&usdhc1 {
assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
......
arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi
View file @ 06e78df3
......@@ -62,7 +62,16 @@ reg_5p0_main: regulator-5p0-main {
reg_3p3_main: regulator-3p3-main {
compatible = "regulator-fixed";
vin-supply = <&reg_12p0_main>;
regulator-name = "3V3V_MAIN";
regulator-name = "3V3_MAIN";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_gen_3p3: regulator-gen-3p3 {
compatible = "regulator-fixed";
vin-supply = <&reg_3p3_main>;
regulator-name = "GEN_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
......@@ -72,7 +81,7 @@ reg_usdhc2_vmmc: regulator-vsd-3v3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2>;
compatible = "regulator-fixed";
vin-supply = <&reg_3p3_main>;
vin-supply = <&reg_gen_3p3>;
regulator-name = "3V3_SD";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
......@@ -253,6 +262,18 @@ &i2c1 {
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
accelerometer@1c {
compatible = "fsl,mma8451";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_accel>;
reg = <0x1c>;
interrupt-parent = <&gpio3>;
interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "INT2";
vdd-supply = <&reg_gen_3p3>;
vddio-supply = <&reg_gen_3p3>;
};
ucs1002: charger@32 {
compatible = "microchip,ucs1002";
pinctrl-names = "default";
......@@ -379,6 +400,11 @@ usbhub: usbhub@2c {
reg = <0x2c>;
reset-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
};
watchdog@38 {
compatible = "zii,rave-wdt";
reg = <0x38>;
};
};
&i2c4 {
......@@ -486,6 +512,8 @@ &pgc_vpu {
};
&usdhc1 {
assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
......@@ -499,6 +527,8 @@ &usdhc1 {
};
&usdhc2 {
assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
......@@ -513,6 +543,12 @@ &snvs_rtc {
};
&iomuxc {
pinctrl_accel: accelgrp {
fsl,pins = <
MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
......
arch/arm64/boot/dts/freescale/imx8mq.dtsi
View file @ 06e78df3
......@@ -235,12 +235,26 @@ gpu-thermal {
thermal-sensors = <&tmu 1>;
trips {
gpu_alert: gpu-alert {
temperature = <80000>;
hysteresis = <2000>;
type = "passive";
};
gpu-crit {
temperature = <90000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&gpu_alert>;
cooling-device =
<&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
vpu-thermal {
......@@ -854,8 +868,6 @@ usdhc1: mmc@30b40000 {
<&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
<&clk IMX8MQ_CLK_USDHC1_ROOT>;
clock-names = "ipg", "ahb", "per";
assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
assigned-clock-rates = <400000000>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step = <2>;
bus-width = <4>;
......@@ -949,6 +961,7 @@ gpu: gpu@38000000 {
<&clk IMX8MQ_CLK_GPU_AXI>,
<&clk IMX8MQ_CLK_GPU_AHB>;
clock-names = "core", "shader", "bus", "reg";
#cooling-cells = <2>;
assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>,
<&clk IMX8MQ_CLK_GPU_SHADER_SRC>,
<&clk IMX8MQ_CLK_GPU_AXI>,
......
arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts
View file @ 06e78df3
......@@ -133,6 +133,8 @@ ethphy0: ethernet-phy@0 {
&usdhc1 {
#address-cells = <1>;
#size-cells = <0>;
assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
bus-width = <4>;
......@@ -149,6 +151,8 @@ brcmf: wifi@1 {
/* SD */
&usdhc2 {
assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
bus-width = <4>;
......
arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dts 0 → 100644
View file @ 06e78df3
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright 2019 Toradex
*/
/dts-v1/;
#include "imx8qxp-colibri.dtsi"
#include "imx8qxp-colibri-eval-v3.dtsi"
/ {
model = "Toradex Colibri iMX8QXP/DX on Colibri Evaluation Board V3";
compatible = "toradex,colibri-imx8x-eval-v3",
"toradex,colibri-imx8x", "fsl,imx8qxp";
};
arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi 0 → 100644
View file @ 06e78df3
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright 2019 Toradex
*/
#include "dt-bindings/input/linux-event-codes.h"
/ {
aliases {
rtc0 = &rtc_i2c;
rtc1 = &rtc;
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpiokeys>;
wakeup {
label = "Wake-Up";
gpios = <&lsio_gpio3 10 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_WAKEUP>;
debounce-interval = <10>;
wakeup-source;
};
};
};
&adma_i2c1 {
status = "okay";
/* M41T0M6 real time clock on carrier board */
rtc_i2c: rtc@68 {
compatible = "st,m41t0";
reg = <0x68>;
};
};
/* Colibri UART_B */
&adma_lpuart0 {
status= "okay";
};
/* Colibri UART_C */
&adma_lpuart2 {
status= "okay";
};
/* Colibri UART_A */
&adma_lpuart3 {
status= "okay";
};
/* Colibri FastEthernet */
&fec1 {
status = "okay";
};
/* Colibri SD/MMC Card */
&usdhc2 {
status = "okay";
};
arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi 0 → 100644
View file @ 06e78df3
This diff is collapsed.
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
View file @ 06e78df3
......@@ -137,6 +137,8 @@ light-sensor@44 {
};
&usdhc1 {
assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
bus-width = <8>;
......@@ -147,6 +149,8 @@ &usdhc1 {
};
&usdhc2 {
assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
bus-width = <4>;
......@@ -234,3 +238,7 @@ IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
&adma_dsp {
status = "okay";
};
&scu_key {
status = "okay";
};
arch/arm64/boot/dts/freescale/imx8qxp.dtsi
View file @ 06e78df3
......@@ -8,6 +8,7 @@
#include <dt-bindings/clock/imx8-clock.h>
#include <dt-bindings/firmware/imx/rsrc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/pads-imx8qxp.h>
......@@ -174,6 +175,12 @@ pd: imx8qx-pd {
#power-domain-cells = <1>;
};
scu_key: scu-key {
compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
linux,keycodes = <KEY_POWER>;
status = "disabled";
};
rtc: rtc {
compatible = "fsl,imx8qxp-sc-rtc";
};
......@@ -361,8 +368,6 @@ usdhc1: mmc@5b010000 {
<&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>,
<&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>;
clock-names = "ipg", "per", "ahb";
assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>;
assigned-clock-rates = <200000000>;
power-domains = <&pd IMX_SC_R_SDHC_0>;
status = "disabled";
};
......@@ -376,8 +381,6 @@ usdhc2: mmc@5b020000 {
<&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>,
<&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>;
clock-names = "ipg", "per", "ahb";
assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>;
assigned-clock-rates = <200000000>;
power-domains = <&pd IMX_SC_R_SDHC_1>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
......@@ -393,8 +396,6 @@ usdhc3: mmc@5b030000 {
<&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>,
<&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>;
clock-names = "ipg", "per", "ahb";
assigned-clocks = <&clk IMX_CONN_SDHC2_CLK>;
assigned-clock-rates = <200000000>;
power-domains = <&pd IMX_SC_R_SDHC_2>;
status = "disabled";
};
......
arch/arm64/boot/dts/freescale/s32v234-evb.dts 0 → 100644
View file @ 06e78df3
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2015-2016 Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*/
/dts-v1/;
#include "s32v234.dtsi"
/ {
model = "NXP S32V234-EVB2 Board";
compatible = "fsl,s32v234-evb", "fsl,s32v234";
chosen {
stdout-path = "serial0:115200n8";
};
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
arch/arm64/boot/dts/freescale/s32v234.dtsi 0 → 100644
View file @ 06e78df3
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2015-2016 Freescale Semiconductor, Inc.
* Copyright 2016-2018 NXP
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
/memreserve/ 0x80000000 0x00010000;
/ {
compatible = "fsl,s32v234";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
serial0 = &uart0;
serial1 = &uart1;
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x80000000>;
next-level-cache = <&cluster0_l2_cache>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x80000000>;
next-level-cache = <&cluster0_l2_cache>;
};
cpu2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x100>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x80000000>;
next-level-cache = <&cluster1_l2_cache>;
};
cpu3: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x101>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x80000000>;
next-level-cache = <&cluster1_l2_cache>;
};
cluster0_l2_cache: l2-cache0 {
compatible = "cache";
};
cluster1_l2_cache: l2-cache1 {
compatible = "cache";
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>;
/* clock-frequency might be modified by u-boot, depending on the
* chip version.
*/
clock-frequency = <10000000>;
};
gic: interrupt-controller@7d001000 {
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0 0x7d001000 0 0x1000>,
<0 0x7d002000 0 0x2000>,
<0 0x7d004000 0 0x2000>,
<0 0x7d006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_HIGH)>;
};
soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges;
aips0: aips-bus@40000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
reg = <0x0 0x40000000 0x0 0x7d000>;
ranges;
uart0: serial@40053000 {
compatible = "fsl,s32v234-linflexuart";
reg = <0x0 0x40053000 0x0 0x1000>;
interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
};
aips1: aips-bus@40080000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
reg = <0x0 0x40080000 0x0 0x70000>;
ranges;
uart1: serial@400bc000 {
compatible = "fsl,s32v234-linflexuart";
reg = <0x0 0x400bc000 0x0 0x1000>;
interrupts = <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
};
};
};
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