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Commit 19c2d849 authored by Mark Brown's avatar Mark Brown
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Merge remote-tracking branches 'asoc/topic/mtk', 'asoc/topic/mxs',... 

Merge remote-tracking branches 'asoc/topic/mtk', 'asoc/topic/mxs', 'asoc/topic/mxs-sgtl5000', 'asoc/topic/nau8540' and 'asoc/topic/nau8824' into asoc-next
parents 5e1b9447 dc2a17f4 949293d4 d04c413f fe83b1b7 080f773d
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Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt
View file @ 19c2d849
...@@ -2,153 +2,143 @@ Mediatek AFE PCM controller for mt2701 ...@@ -2,153 +2,143 @@ Mediatek AFE PCM controller for mt2701
Required properties: Required properties:
- compatible = "mediatek,mt2701-audio"; - compatible = "mediatek,mt2701-audio";
- reg: register location and size
- interrupts: should contain AFE and ASYS interrupts - interrupts: should contain AFE and ASYS interrupts
- interrupt-names: should be "afe" and "asys" - interrupt-names: should be "afe" and "asys"
- power-domains: should define the power domain - power-domains: should define the power domain
- clocks: Must contain an entry for each entry in clock-names
See ../clocks/clock-bindings.txt for details
- clock-names: should have these clock names: - clock-names: should have these clock names:
"infra_sys_audio_clk", "infra_sys_audio_clk",
"top_audio_mux1_sel", "top_audio_mux1_sel",
"top_audio_mux2_sel", "top_audio_mux2_sel",
"top_audio_mux1_div", "top_audio_a1sys_hp",
"top_audio_mux2_div", "top_audio_a2sys_hp",
"top_audio_48k_timing", "i2s0_src_sel",
"top_audio_44k_timing", "i2s1_src_sel",
"top_audpll_mux_sel", "i2s2_src_sel",
"top_apll_sel", "i2s3_src_sel",
"top_aud1_pll_98M", "i2s0_src_div",
"top_aud2_pll_90M", "i2s1_src_div",
"top_hadds2_pll_98M", "i2s2_src_div",
"top_hadds2_pll_294M", "i2s3_src_div",
"top_audpll", "i2s0_mclk_en",
"top_audpll_d4", "i2s1_mclk_en",
"top_audpll_d8", "i2s2_mclk_en",
"top_audpll_d16", "i2s3_mclk_en",
"top_audpll_d24", "i2so0_hop_ck",
"top_audintbus_sel", "i2so1_hop_ck",
"clk_26m", "i2so2_hop_ck",
"top_syspll1_d4", "i2so3_hop_ck",
"top_aud_k1_src_sel", "i2si0_hop_ck",
"top_aud_k2_src_sel", "i2si1_hop_ck",
"top_aud_k3_src_sel", "i2si2_hop_ck",
"top_aud_k4_src_sel", "i2si3_hop_ck",
"top_aud_k5_src_sel", "asrc0_out_ck",
"top_aud_k6_src_sel", "asrc1_out_ck",
"top_aud_k1_src_div", "asrc2_out_ck",
"top_aud_k2_src_div", "asrc3_out_ck",
"top_aud_k3_src_div", "audio_afe_pd",
"top_aud_k4_src_div", "audio_afe_conn_pd",
"top_aud_k5_src_div", "audio_a1sys_pd",
"top_aud_k6_src_div", "audio_a2sys_pd",
"top_aud_i2s1_mclk", "audio_mrgif_pd";
"top_aud_i2s2_mclk", - assigned-clocks: list of input clocks and dividers for the audio system.
"top_aud_i2s3_mclk", See ../clocks/clock-bindings.txt for details.
"top_aud_i2s4_mclk", - assigned-clocks-parents: parent of input clocks of assigned clocks.
"top_aud_i2s5_mclk", - assigned-clock-rates: list of clock frequencies of assigned clocks.
"top_aud_i2s6_mclk",
"top_asm_m_sel", Must be a subnode of MediaTek audsys device tree node.
"top_asm_h_sel", See ../arm/mediatek/mediatek,audsys.txt for details about the parent node.
"top_univpll2_d4",
"top_univpll2_d2",
"top_syspll_d5";
Example: Example:
afe: mt2701-afe-pcm@11220000 { audsys: audio-subsystem@11220000 {
compatible = "mediatek,mt2701-audio"; compatible = "mediatek,mt2701-audsys", "syscon", "simple-mfd";
reg = <0 0x11220000 0 0x2000>, ...
<0 0x112A0000 0 0x20000>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, afe: audio-controller {
<GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; compatible = "mediatek,mt2701-audio";
interrupt-names = "afe", "asys"; interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_INFRA_AUDIO>, interrupt-names = "afe", "asys";
<&topckgen CLK_TOP_AUD_MUX1_SEL>, power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
<&topckgen CLK_TOP_AUD_MUX2_SEL>,
<&topckgen CLK_TOP_AUD_MUX1_DIV>, clocks = <&infracfg CLK_INFRA_AUDIO>,
<&topckgen CLK_TOP_AUD_MUX2_DIV>, <&topckgen CLK_TOP_AUD_MUX1_SEL>,
<&topckgen CLK_TOP_AUD_48K_TIMING>, <&topckgen CLK_TOP_AUD_MUX2_SEL>,
<&topckgen CLK_TOP_AUD_44K_TIMING>, <&topckgen CLK_TOP_AUD_48K_TIMING>,
<&topckgen CLK_TOP_AUDPLL_MUX_SEL>, <&topckgen CLK_TOP_AUD_44K_TIMING>,
<&topckgen CLK_TOP_APLL_SEL>, <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
<&topckgen CLK_TOP_AUD1PLL_98M>, <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
<&topckgen CLK_TOP_AUD2PLL_90M>, <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
<&topckgen CLK_TOP_HADDS2PLL_98M>, <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
<&topckgen CLK_TOP_HADDS2PLL_294M>, <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
<&topckgen CLK_TOP_AUDPLL>, <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
<&topckgen CLK_TOP_AUDPLL_D4>, <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
<&topckgen CLK_TOP_AUDPLL_D8>, <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
<&topckgen CLK_TOP_AUDPLL_D16>, <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
<&topckgen CLK_TOP_AUDPLL_D24>, <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
<&topckgen CLK_TOP_AUDINTBUS_SEL>, <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
<&clk26m>, <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
<&topckgen CLK_TOP_SYSPLL1_D4>, <&audsys CLK_AUD_I2SO1>,
<&topckgen CLK_TOP_AUD_K1_SRC_SEL>, <&audsys CLK_AUD_I2SO2>,
<&topckgen CLK_TOP_AUD_K2_SRC_SEL>, <&audsys CLK_AUD_I2SO3>,
<&topckgen CLK_TOP_AUD_K3_SRC_SEL>, <&audsys CLK_AUD_I2SO4>,
<&topckgen CLK_TOP_AUD_K4_SRC_SEL>, <&audsys CLK_AUD_I2SIN1>,
<&topckgen CLK_TOP_AUD_K5_SRC_SEL>, <&audsys CLK_AUD_I2SIN2>,
<&topckgen CLK_TOP_AUD_K6_SRC_SEL>, <&audsys CLK_AUD_I2SIN3>,
<&topckgen CLK_TOP_AUD_K1_SRC_DIV>, <&audsys CLK_AUD_I2SIN4>,
<&topckgen CLK_TOP_AUD_K2_SRC_DIV>, <&audsys CLK_AUD_ASRCO1>,
<&topckgen CLK_TOP_AUD_K3_SRC_DIV>, <&audsys CLK_AUD_ASRCO2>,
<&topckgen CLK_TOP_AUD_K4_SRC_DIV>, <&audsys CLK_AUD_ASRCO3>,
<&topckgen CLK_TOP_AUD_K5_SRC_DIV>, <&audsys CLK_AUD_ASRCO4>,
<&topckgen CLK_TOP_AUD_K6_SRC_DIV>, <&audsys CLK_AUD_AFE>,
<&topckgen CLK_TOP_AUD_I2S1_MCLK>, <&audsys CLK_AUD_AFE_CONN>,
<&topckgen CLK_TOP_AUD_I2S2_MCLK>, <&audsys CLK_AUD_A1SYS>,
<&topckgen CLK_TOP_AUD_I2S3_MCLK>, <&audsys CLK_AUD_A2SYS>,
<&topckgen CLK_TOP_AUD_I2S4_MCLK>, <&audsys CLK_AUD_AFE_MRGIF>;
<&topckgen CLK_TOP_AUD_I2S5_MCLK>,
<&topckgen CLK_TOP_AUD_I2S6_MCLK>, clock-names = "infra_sys_audio_clk",
<&topckgen CLK_TOP_ASM_M_SEL>, "top_audio_mux1_sel",
<&topckgen CLK_TOP_ASM_H_SEL>, "top_audio_mux2_sel",
<&topckgen CLK_TOP_UNIVPLL2_D4>, "top_audio_a1sys_hp",
<&topckgen CLK_TOP_UNIVPLL2_D2>, "top_audio_a2sys_hp",
<&topckgen CLK_TOP_SYSPLL_D5>; "i2s0_src_sel",
"i2s1_src_sel",
"i2s2_src_sel",
"i2s3_src_sel",
"i2s0_src_div",
"i2s1_src_div",
"i2s2_src_div",
"i2s3_src_div",
"i2s0_mclk_en",
"i2s1_mclk_en",
"i2s2_mclk_en",
"i2s3_mclk_en",
"i2so0_hop_ck",
"i2so1_hop_ck",
"i2so2_hop_ck",
"i2so3_hop_ck",
"i2si0_hop_ck",
"i2si1_hop_ck",
"i2si2_hop_ck",
"i2si3_hop_ck",
"asrc0_out_ck",
"asrc1_out_ck",
"asrc2_out_ck",
"asrc3_out_ck",
"audio_afe_pd",
"audio_afe_conn_pd",
"audio_a1sys_pd",
"audio_a2sys_pd",
"audio_mrgif_pd";
clock-names = "infra_sys_audio_clk", assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
"top_audio_mux1_sel", <&topckgen CLK_TOP_AUD_MUX2_SEL>,
"top_audio_mux2_sel", <&topckgen CLK_TOP_AUD_MUX1_DIV>,
"top_audio_mux1_div", <&topckgen CLK_TOP_AUD_MUX2_DIV>;
"top_audio_mux2_div", assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
"top_audio_48k_timing", <&topckgen CLK_TOP_AUD2PLL_90M>;
"top_audio_44k_timing", assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
"top_audpll_mux_sel", };
"top_apll_sel",
"top_aud1_pll_98M",
"top_aud2_pll_90M",
"top_hadds2_pll_98M",
"top_hadds2_pll_294M",
"top_audpll",
"top_audpll_d4",
"top_audpll_d8",
"top_audpll_d16",
"top_audpll_d24",
"top_audintbus_sel",
"clk_26m",
"top_syspll1_d4",
"top_aud_k1_src_sel",
"top_aud_k2_src_sel",
"top_aud_k3_src_sel",
"top_aud_k4_src_sel",
"top_aud_k5_src_sel",
"top_aud_k6_src_sel",
"top_aud_k1_src_div",
"top_aud_k2_src_div",
"top_aud_k3_src_div",
"top_aud_k4_src_div",
"top_aud_k5_src_div",
"top_aud_k6_src_div",
"top_aud_i2s1_mclk",
"top_aud_i2s2_mclk",
"top_aud_i2s3_mclk",
"top_aud_i2s4_mclk",
"top_aud_i2s5_mclk",
"top_aud_i2s6_mclk",
"top_asm_m_sel",
"top_asm_h_sel",
"top_univpll2_d4",
"top_univpll2_d2",
"top_syspll_d5";
}; };
Documentation/devicetree/bindings/sound/mxs-audio-sgtl5000.txt
View file @ 19c2d849
* Freescale MXS audio complex with SGTL5000 codec * Freescale MXS audio complex with SGTL5000 codec
Required properties: Required properties:
- compatible: "fsl,mxs-audio-sgtl5000" - compatible : "fsl,mxs-audio-sgtl5000"
- model: The user-visible name of this sound complex - model : The user-visible name of this sound complex
- saif-controllers: The phandle list of the MXS SAIF controller - saif-controllers : The phandle list of the MXS SAIF controller
- audio-codec: The phandle of the SGTL5000 audio codec - audio-codec : The phandle of the SGTL5000 audio codec
- audio-routing : A list of the connections between audio components.
Each entry is a pair of strings, the first being the
connection's sink, the second being the connection's
source. Valid names could be power supplies, SGTL5000
pins, and the jacks on the board:
Power supplies:
* Mic Bias
SGTL5000 pins:
* MIC_IN
* LINE_IN
* HP_OUT
* LINE_OUT
Board connectors:
* Mic Jack
* Line In Jack
* Headphone Jack
* Line Out Jack
* Ext Spk
Example: Example:
...@@ -14,4 +35,8 @@ sound { ...@@ -14,4 +35,8 @@ sound {
model = "imx28-evk-sgtl5000"; model = "imx28-evk-sgtl5000";
saif-controllers = <&saif0 &saif1>; saif-controllers = <&saif0 &saif1>;
audio-codec = <&sgtl5000>; audio-codec = <&sgtl5000>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
}; };
sound/soc/codecs/nau8540.c
View file @ 19c2d849
...@@ -233,6 +233,41 @@ static SOC_ENUM_SINGLE_DECL( ...@@ -233,6 +233,41 @@ static SOC_ENUM_SINGLE_DECL(
static const struct snd_kcontrol_new digital_ch1_mux = static const struct snd_kcontrol_new digital_ch1_mux =
SOC_DAPM_ENUM("Digital CH1 Select", digital_ch1_enum); SOC_DAPM_ENUM("Digital CH1 Select", digital_ch1_enum);
static int adc_power_control(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *k, int event)
{
struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
struct nau8540 *nau8540 = snd_soc_codec_get_drvdata(codec);
if (SND_SOC_DAPM_EVENT_ON(event)) {
msleep(300);
/* DO12 and DO34 pad output enable */
regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
NAU8540_I2S_DO12_TRI, 0);
regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
NAU8540_I2S_DO34_TRI, 0);
} else if (SND_SOC_DAPM_EVENT_OFF(event)) {
regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
NAU8540_I2S_DO12_TRI, NAU8540_I2S_DO12_TRI);
regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
NAU8540_I2S_DO34_TRI, NAU8540_I2S_DO34_TRI);
}
return 0;
}
static int aiftx_power_control(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *k, int event)
{
struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
struct nau8540 *nau8540 = snd_soc_codec_get_drvdata(codec);
if (SND_SOC_DAPM_EVENT_OFF(event)) {
regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0001);
regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0000);
}
return 0;
}
static const struct snd_soc_dapm_widget nau8540_dapm_widgets[] = { static const struct snd_soc_dapm_widget nau8540_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("MICBIAS2", NAU8540_REG_MIC_BIAS, 11, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("MICBIAS2", NAU8540_REG_MIC_BIAS, 11, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS1", NAU8540_REG_MIC_BIAS, 10, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("MICBIAS1", NAU8540_REG_MIC_BIAS, 10, 0, NULL, 0),
...@@ -247,14 +282,18 @@ static const struct snd_soc_dapm_widget nau8540_dapm_widgets[] = { ...@@ -247,14 +282,18 @@ static const struct snd_soc_dapm_widget nau8540_dapm_widgets[] = {
SND_SOC_DAPM_PGA("Frontend PGA3", NAU8540_REG_PWR, 14, 0, NULL, 0), SND_SOC_DAPM_PGA("Frontend PGA3", NAU8540_REG_PWR, 14, 0, NULL, 0),
SND_SOC_DAPM_PGA("Frontend PGA4", NAU8540_REG_PWR, 15, 0, NULL, 0), SND_SOC_DAPM_PGA("Frontend PGA4", NAU8540_REG_PWR, 15, 0, NULL, 0),
SND_SOC_DAPM_ADC("ADC1", NULL, SND_SOC_DAPM_ADC_E("ADC1", NULL,
NAU8540_REG_POWER_MANAGEMENT, 0, 0), NAU8540_REG_POWER_MANAGEMENT, 0, 0, adc_power_control,
SND_SOC_DAPM_ADC("ADC2", NULL, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
NAU8540_REG_POWER_MANAGEMENT, 1, 0), SND_SOC_DAPM_ADC_E("ADC2", NULL,
SND_SOC_DAPM_ADC("ADC3", NULL, NAU8540_REG_POWER_MANAGEMENT, 1, 0, adc_power_control,
NAU8540_REG_POWER_MANAGEMENT, 2, 0), SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_ADC("ADC4", NULL, SND_SOC_DAPM_ADC_E("ADC3", NULL,
NAU8540_REG_POWER_MANAGEMENT, 3, 0), NAU8540_REG_POWER_MANAGEMENT, 2, 0, adc_power_control,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_ADC_E("ADC4", NULL,
NAU8540_REG_POWER_MANAGEMENT, 3, 0, adc_power_control,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_PGA("ADC CH1", NAU8540_REG_ANALOG_PWR, 0, 0, NULL, 0), SND_SOC_DAPM_PGA("ADC CH1", NAU8540_REG_ANALOG_PWR, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("ADC CH2", NAU8540_REG_ANALOG_PWR, 1, 0, NULL, 0), SND_SOC_DAPM_PGA("ADC CH2", NAU8540_REG_ANALOG_PWR, 1, 0, NULL, 0),
...@@ -270,7 +309,8 @@ static const struct snd_soc_dapm_widget nau8540_dapm_widgets[] = { ...@@ -270,7 +309,8 @@ static const struct snd_soc_dapm_widget nau8540_dapm_widgets[] = {
SND_SOC_DAPM_MUX("Digital CH1 Mux", SND_SOC_DAPM_MUX("Digital CH1 Mux",
SND_SOC_NOPM, 0, 0, &digital_ch1_mux), SND_SOC_NOPM, 0, 0, &digital_ch1_mux),
SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT_E("AIFTX", "Capture", 0, SND_SOC_NOPM, 0, 0,
aiftx_power_control, SND_SOC_DAPM_POST_PMD),
}; };
static const struct snd_soc_dapm_route nau8540_dapm_routes[] = { static const struct snd_soc_dapm_route nau8540_dapm_routes[] = {
...@@ -575,7 +615,8 @@ static void nau8540_fll_apply(struct regmap *regmap, ...@@ -575,7 +615,8 @@ static void nau8540_fll_apply(struct regmap *regmap,
NAU8540_CLK_SRC_MASK | NAU8540_CLK_MCLK_SRC_MASK, NAU8540_CLK_SRC_MASK | NAU8540_CLK_MCLK_SRC_MASK,
NAU8540_CLK_SRC_MCLK | fll_param->mclk_src); NAU8540_CLK_SRC_MCLK | fll_param->mclk_src);
regmap_update_bits(regmap, NAU8540_REG_FLL1, regmap_update_bits(regmap, NAU8540_REG_FLL1,
NAU8540_FLL_RATIO_MASK, fll_param->ratio); NAU8540_FLL_RATIO_MASK | NAU8540_ICTRL_LATCH_MASK,
fll_param->ratio | (0x6 << NAU8540_ICTRL_LATCH_SFT));
/* FLL 16-bit fractional input */ /* FLL 16-bit fractional input */
regmap_write(regmap, NAU8540_REG_FLL2, fll_param->fll_frac); regmap_write(regmap, NAU8540_REG_FLL2, fll_param->fll_frac);
/* FLL 10-bit integer input */ /* FLL 10-bit integer input */
...@@ -596,13 +637,14 @@ static void nau8540_fll_apply(struct regmap *regmap, ...@@ -596,13 +637,14 @@ static void nau8540_fll_apply(struct regmap *regmap,
NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN | NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN |
NAU8540_FLL_FTR_SW_FILTER); NAU8540_FLL_FTR_SW_FILTER);
regmap_update_bits(regmap, NAU8540_REG_FLL6, regmap_update_bits(regmap, NAU8540_REG_FLL6,
NAU8540_SDM_EN, NAU8540_SDM_EN); NAU8540_SDM_EN | NAU8540_CUTOFF500,
NAU8540_SDM_EN | NAU8540_CUTOFF500);
} else { } else {
regmap_update_bits(regmap, NAU8540_REG_FLL5, regmap_update_bits(regmap, NAU8540_REG_FLL5,
NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN | NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN |
NAU8540_FLL_FTR_SW_MASK, NAU8540_FLL_FTR_SW_ACCU); NAU8540_FLL_FTR_SW_MASK, NAU8540_FLL_FTR_SW_ACCU);
regmap_update_bits(regmap, regmap_update_bits(regmap, NAU8540_REG_FLL6,
NAU8540_REG_FLL6, NAU8540_SDM_EN, 0); NAU8540_SDM_EN | NAU8540_CUTOFF500, 0);
} }
} }
...@@ -617,17 +659,22 @@ static int nau8540_set_pll(struct snd_soc_codec *codec, int pll_id, int source, ...@@ -617,17 +659,22 @@ static int nau8540_set_pll(struct snd_soc_codec *codec, int pll_id, int source,
switch (pll_id) { switch (pll_id) {
case NAU8540_CLK_FLL_MCLK: case NAU8540_CLK_FLL_MCLK:
regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3, regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
NAU8540_FLL_CLK_SRC_MASK, NAU8540_FLL_CLK_SRC_MCLK); NAU8540_FLL_CLK_SRC_MASK | NAU8540_GAIN_ERR_MASK,
NAU8540_FLL_CLK_SRC_MCLK | 0);
break; break;
case NAU8540_CLK_FLL_BLK: case NAU8540_CLK_FLL_BLK:
regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3, regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
NAU8540_FLL_CLK_SRC_MASK, NAU8540_FLL_CLK_SRC_BLK); NAU8540_FLL_CLK_SRC_MASK | NAU8540_GAIN_ERR_MASK,
NAU8540_FLL_CLK_SRC_BLK |
(0xf << NAU8540_GAIN_ERR_SFT));
break; break;
case NAU8540_CLK_FLL_FS: case NAU8540_CLK_FLL_FS:
regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3, regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
NAU8540_FLL_CLK_SRC_MASK, NAU8540_FLL_CLK_SRC_FS); NAU8540_FLL_CLK_SRC_MASK | NAU8540_GAIN_ERR_MASK,
NAU8540_FLL_CLK_SRC_FS |
(0xf << NAU8540_GAIN_ERR_SFT));
break; break;
default: default:
...@@ -710,9 +757,24 @@ static void nau8540_init_regs(struct nau8540 *nau8540) ...@@ -710,9 +757,24 @@ static void nau8540_init_regs(struct nau8540 *nau8540)
regmap_update_bits(regmap, NAU8540_REG_CLOCK_CTRL, regmap_update_bits(regmap, NAU8540_REG_CLOCK_CTRL,
NAU8540_CLK_ADC_EN | NAU8540_CLK_I2S_EN, NAU8540_CLK_ADC_EN | NAU8540_CLK_I2S_EN,
NAU8540_CLK_ADC_EN | NAU8540_CLK_I2S_EN); NAU8540_CLK_ADC_EN | NAU8540_CLK_I2S_EN);
/* ADC OSR selection, CLK_ADC = Fs * OSR */ /* ADC OSR selection, CLK_ADC = Fs * OSR;
* Channel time alignment enable.
*/
regmap_update_bits(regmap, NAU8540_REG_ADC_SAMPLE_RATE, regmap_update_bits(regmap, NAU8540_REG_ADC_SAMPLE_RATE,
NAU8540_ADC_OSR_MASK, NAU8540_ADC_OSR_64); NAU8540_CH_SYNC | NAU8540_ADC_OSR_MASK,
NAU8540_CH_SYNC | NAU8540_ADC_OSR_64);
/* PGA input mode selection */
regmap_update_bits(regmap, NAU8540_REG_FEPGA1,
NAU8540_FEPGA1_MODCH2_SHT | NAU8540_FEPGA1_MODCH1_SHT,
NAU8540_FEPGA1_MODCH2_SHT | NAU8540_FEPGA1_MODCH1_SHT);
regmap_update_bits(regmap, NAU8540_REG_FEPGA2,
NAU8540_FEPGA2_MODCH4_SHT | NAU8540_FEPGA2_MODCH3_SHT,
NAU8540_FEPGA2_MODCH4_SHT | NAU8540_FEPGA2_MODCH3_SHT);
/* DO12 and DO34 pad output disable */
regmap_update_bits(regmap, NAU8540_REG_PCM_CTRL1,
NAU8540_I2S_DO12_TRI, NAU8540_I2S_DO12_TRI);
regmap_update_bits(regmap, NAU8540_REG_PCM_CTRL2,
NAU8540_I2S_DO34_TRI, NAU8540_I2S_DO34_TRI);
} }
static int __maybe_unused nau8540_suspend(struct snd_soc_codec *codec) static int __maybe_unused nau8540_suspend(struct snd_soc_codec *codec)
......
sound/soc/codecs/nau8540.h
View file @ 19c2d849
...@@ -100,9 +100,13 @@ ...@@ -100,9 +100,13 @@
#define NAU8540_CLK_MCLK_SRC_MASK 0xf #define NAU8540_CLK_MCLK_SRC_MASK 0xf
/* FLL1 (0x04) */ /* FLL1 (0x04) */
#define NAU8540_ICTRL_LATCH_SFT 10
#define NAU8540_ICTRL_LATCH_MASK (0x7 << NAU8540_ICTRL_LATCH_SFT)
#define NAU8540_FLL_RATIO_MASK 0x7f #define NAU8540_FLL_RATIO_MASK 0x7f
/* FLL3 (0x06) */ /* FLL3 (0x06) */
#define NAU8540_GAIN_ERR_SFT 12
#define NAU8540_GAIN_ERR_MASK (0xf << NAU8540_GAIN_ERR_SFT)
#define NAU8540_FLL_CLK_SRC_SFT 10 #define NAU8540_FLL_CLK_SRC_SFT 10
#define NAU8540_FLL_CLK_SRC_MASK (0x3 << NAU8540_FLL_CLK_SRC_SFT) #define NAU8540_FLL_CLK_SRC_MASK (0x3 << NAU8540_FLL_CLK_SRC_SFT)
#define NAU8540_FLL_CLK_SRC_MCLK (0 << NAU8540_FLL_CLK_SRC_SFT) #define NAU8540_FLL_CLK_SRC_MCLK (0 << NAU8540_FLL_CLK_SRC_SFT)
...@@ -127,6 +131,7 @@ ...@@ -127,6 +131,7 @@
/* FLL6 (0x9) */ /* FLL6 (0x9) */
#define NAU8540_DCO_EN (0x1 << 15) #define NAU8540_DCO_EN (0x1 << 15)
#define NAU8540_SDM_EN (0x1 << 14) #define NAU8540_SDM_EN (0x1 << 14)
#define NAU8540_CUTOFF500 (0x1 << 13)
/* PCM_CTRL0 (0x10) */ /* PCM_CTRL0 (0x10) */
#define NAU8540_I2S_BP_SFT 7 #define NAU8540_I2S_BP_SFT 7
...@@ -146,6 +151,7 @@ ...@@ -146,6 +151,7 @@
#define NAU8540_I2S_DF_PCM_AB 0x3 #define NAU8540_I2S_DF_PCM_AB 0x3
/* PCM_CTRL1 (0x11) */ /* PCM_CTRL1 (0x11) */
#define NAU8540_I2S_DO12_TRI (0x1 << 15)
#define NAU8540_I2S_LRC_DIV_SFT 12 #define NAU8540_I2S_LRC_DIV_SFT 12
#define NAU8540_I2S_LRC_DIV_MASK (0x3 << NAU8540_I2S_LRC_DIV_SFT) #define NAU8540_I2S_LRC_DIV_MASK (0x3 << NAU8540_I2S_LRC_DIV_SFT)
#define NAU8540_I2S_DO12_OE (0x1 << 4) #define NAU8540_I2S_DO12_OE (0x1 << 4)
...@@ -156,6 +162,7 @@ ...@@ -156,6 +162,7 @@
#define NAU8540_I2S_BLK_DIV_MASK 0x7 #define NAU8540_I2S_BLK_DIV_MASK 0x7
/* PCM_CTRL1 (0x12) */ /* PCM_CTRL1 (0x12) */
#define NAU8540_I2S_DO34_TRI (0x1 << 15)
#define NAU8540_I2S_DO34_OE (0x1 << 11) #define NAU8540_I2S_DO34_OE (0x1 << 11)
#define NAU8540_I2S_TSLOT_L_MASK 0x3ff #define NAU8540_I2S_TSLOT_L_MASK 0x3ff
...@@ -165,6 +172,7 @@ ...@@ -165,6 +172,7 @@
#define NAU8540_TDM_TX_MASK 0xf #define NAU8540_TDM_TX_MASK 0xf
/* ADC_SAMPLE_RATE (0x3A) */ /* ADC_SAMPLE_RATE (0x3A) */
#define NAU8540_CH_SYNC (0x1 << 14)
#define NAU8540_ADC_OSR_MASK 0x3 #define NAU8540_ADC_OSR_MASK 0x3
#define NAU8540_ADC_OSR_256 0x3 #define NAU8540_ADC_OSR_256 0x3
#define NAU8540_ADC_OSR_128 0x2 #define NAU8540_ADC_OSR_128 0x2
...@@ -183,6 +191,18 @@ ...@@ -183,6 +191,18 @@
#define NAU8540_PRECHARGE_DIS (0x1 << 13) #define NAU8540_PRECHARGE_DIS (0x1 << 13)
#define NAU8540_GLOBAL_BIAS_EN (0x1 << 12) #define NAU8540_GLOBAL_BIAS_EN (0x1 << 12)
/* FEPGA1 (0x69) */
#define NAU8540_FEPGA1_MODCH2_SHT_SFT 7
#define NAU8540_FEPGA1_MODCH2_SHT (0x1 << NAU8540_FEPGA1_MODCH2_SHT_SFT)
#define NAU8540_FEPGA1_MODCH1_SHT_SFT 3
#define NAU8540_FEPGA1_MODCH1_SHT (0x1 << NAU8540_FEPGA1_MODCH1_SHT_SFT)
/* FEPGA2 (0x6A) */
#define NAU8540_FEPGA2_MODCH4_SHT_SFT 7
#define NAU8540_FEPGA2_MODCH4_SHT (0x1 << NAU8540_FEPGA2_MODCH4_SHT_SFT)
#define NAU8540_FEPGA2_MODCH3_SHT_SFT 3
#define NAU8540_FEPGA2_MODCH3_SHT (0x1 << NAU8540_FEPGA2_MODCH3_SHT_SFT)
/* System Clock Source */ /* System Clock Source */
enum { enum {
......
sound/soc/codecs/nau8824.c
View file @ 19c2d849
...@@ -43,7 +43,7 @@ static bool nau8824_is_jack_inserted(struct nau8824 *nau8824); ...@@ -43,7 +43,7 @@ static bool nau8824_is_jack_inserted(struct nau8824 *nau8824);
/* the parameter threshold of FLL */ /* the parameter threshold of FLL */
#define NAU_FREF_MAX 13500000 #define NAU_FREF_MAX 13500000
#define NAU_FVCO_MAX 124000000 #define NAU_FVCO_MAX 100000000
#define NAU_FVCO_MIN 90000000 #define NAU_FVCO_MIN 90000000
/* scaling for mclk from sysclk_src output */ /* scaling for mclk from sysclk_src output */
...@@ -811,7 +811,8 @@ static void nau8824_eject_jack(struct nau8824 *nau8824) ...@@ -811,7 +811,8 @@ static void nau8824_eject_jack(struct nau8824 *nau8824)
NAU8824_JD_SLEEP_MODE, NAU8824_JD_SLEEP_MODE); NAU8824_JD_SLEEP_MODE, NAU8824_JD_SLEEP_MODE);
/* Close clock for jack type detection at manual mode */ /* Close clock for jack type detection at manual mode */
nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0); if (dapm->bias_level < SND_SOC_BIAS_PREPARE)
nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0);
} }
static void nau8824_jdet_work(struct work_struct *work) static void nau8824_jdet_work(struct work_struct *work)
...@@ -843,6 +844,11 @@ static void nau8824_jdet_work(struct work_struct *work) ...@@ -843,6 +844,11 @@ static void nau8824_jdet_work(struct work_struct *work)
event_mask |= SND_JACK_HEADSET; event_mask |= SND_JACK_HEADSET;
snd_soc_jack_report(nau8824->jack, event, event_mask); snd_soc_jack_report(nau8824->jack, event, event_mask);
/* Enable short key press and release interruption. */
regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING,
NAU8824_IRQ_KEY_RELEASE_DIS |
NAU8824_IRQ_KEY_SHORT_PRESS_DIS, 0);
nau8824_sema_release(nau8824); nau8824_sema_release(nau8824);
} }
...@@ -850,15 +856,15 @@ static void nau8824_setup_auto_irq(struct nau8824 *nau8824) ...@@ -850,15 +856,15 @@ static void nau8824_setup_auto_irq(struct nau8824 *nau8824)
{ {
struct regmap *regmap = nau8824->regmap; struct regmap *regmap = nau8824->regmap;
/* Enable jack ejection, short key press and release interruption. */ /* Enable jack ejection interruption. */
regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING_1, regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING_1,
NAU8824_IRQ_INSERT_EN | NAU8824_IRQ_EJECT_EN, NAU8824_IRQ_INSERT_EN | NAU8824_IRQ_EJECT_EN,
NAU8824_IRQ_EJECT_EN); NAU8824_IRQ_EJECT_EN);
regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING, regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING,
NAU8824_IRQ_EJECT_DIS | NAU8824_IRQ_KEY_RELEASE_DIS | NAU8824_IRQ_EJECT_DIS, 0);
NAU8824_IRQ_KEY_SHORT_PRESS_DIS, 0);
/* Enable internal VCO needed for interruptions */ /* Enable internal VCO needed for interruptions */
nau8824_config_sysclk(nau8824, NAU8824_CLK_INTERNAL, 0); if (nau8824->dapm->bias_level < SND_SOC_BIAS_PREPARE)
nau8824_config_sysclk(nau8824, NAU8824_CLK_INTERNAL, 0);
regmap_update_bits(regmap, NAU8824_REG_ENA_CTRL, regmap_update_bits(regmap, NAU8824_REG_ENA_CTRL,
NAU8824_JD_SLEEP_MODE, 0); NAU8824_JD_SLEEP_MODE, 0);
} }
......
sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.h
View file @ 19c2d849
...@@ -21,16 +21,15 @@ struct mtk_base_afe; ...@@ -21,16 +21,15 @@ struct mtk_base_afe;
int mt2701_init_clock(struct mtk_base_afe *afe); int mt2701_init_clock(struct mtk_base_afe *afe);
int mt2701_afe_enable_clock(struct mtk_base_afe *afe); int mt2701_afe_enable_clock(struct mtk_base_afe *afe);
void mt2701_afe_disable_clock(struct mtk_base_afe *afe); int mt2701_afe_disable_clock(struct mtk_base_afe *afe);
int mt2701_turn_on_a1sys_clock(struct mtk_base_afe *afe); int mt2701_afe_enable_i2s(struct mtk_base_afe *afe, int id, int dir);
void mt2701_turn_off_a1sys_clock(struct mtk_base_afe *afe); void mt2701_afe_disable_i2s(struct mtk_base_afe *afe, int id, int dir);
int mt2701_afe_enable_mclk(struct mtk_base_afe *afe, int id);
void mt2701_afe_disable_mclk(struct mtk_base_afe *afe, int id);
int mt2701_turn_on_a2sys_clock(struct mtk_base_afe *afe); int mt2701_enable_btmrg_clk(struct mtk_base_afe *afe);
void mt2701_turn_off_a2sys_clock(struct mtk_base_afe *afe); void mt2701_disable_btmrg_clk(struct mtk_base_afe *afe);
int mt2701_turn_on_afe_clock(struct mtk_base_afe *afe);
void mt2701_turn_off_afe_clock(struct mtk_base_afe *afe);
void mt2701_mclk_configuration(struct mtk_base_afe *afe, int id, int domain, void mt2701_mclk_configuration(struct mtk_base_afe *afe, int id, int domain,
int mclk); int mclk);
......
sound/soc/mediatek/mt2701/mt2701-afe-common.h
View file @ 19c2d849
...@@ -16,6 +16,7 @@ ...@@ -16,6 +16,7 @@
#ifndef _MT_2701_AFE_COMMON_H_ #ifndef _MT_2701_AFE_COMMON_H_
#define _MT_2701_AFE_COMMON_H_ #define _MT_2701_AFE_COMMON_H_
#include <sound/soc.h> #include <sound/soc.h>
#include <linux/clk.h> #include <linux/clk.h>
#include <linux/regmap.h> #include <linux/regmap.h>
...@@ -25,16 +26,7 @@ ...@@ -25,16 +26,7 @@
#define MT2701_STREAM_DIR_NUM (SNDRV_PCM_STREAM_LAST + 1) #define MT2701_STREAM_DIR_NUM (SNDRV_PCM_STREAM_LAST + 1)
#define MT2701_PLL_DOMAIN_0_RATE 98304000 #define MT2701_PLL_DOMAIN_0_RATE 98304000
#define MT2701_PLL_DOMAIN_1_RATE 90316800 #define MT2701_PLL_DOMAIN_1_RATE 90316800
#define MT2701_AUD_AUD_MUX1_DIV_RATE (MT2701_PLL_DOMAIN_0_RATE / 2) #define MT2701_I2S_NUM 4
#define MT2701_AUD_AUD_MUX2_DIV_RATE (MT2701_PLL_DOMAIN_1_RATE / 2)
enum {
MT2701_I2S_1,
MT2701_I2S_2,
MT2701_I2S_3,
MT2701_I2S_4,
MT2701_I2S_NUM,
};
enum { enum {
MT2701_MEMIF_DL1, MT2701_MEMIF_DL1,
...@@ -62,60 +54,23 @@ enum { ...@@ -62,60 +54,23 @@ enum {
}; };
enum { enum {
MT2701_IRQ_ASYS_START, MT2701_IRQ_ASYS_IRQ1,
MT2701_IRQ_ASYS_IRQ1 = MT2701_IRQ_ASYS_START,
MT2701_IRQ_ASYS_IRQ2, MT2701_IRQ_ASYS_IRQ2,
MT2701_IRQ_ASYS_IRQ3, MT2701_IRQ_ASYS_IRQ3,
MT2701_IRQ_ASYS_END, MT2701_IRQ_ASYS_END,
}; };
/* 2701 clock def */ enum audio_base_clock {
enum audio_system_clock_type { MT2701_INFRA_SYS_AUDIO,
MT2701_AUD_INFRA_SYS_AUDIO, MT2701_TOP_AUD_MCLK_SRC0,
MT2701_AUD_AUD_MUX1_SEL, MT2701_TOP_AUD_MCLK_SRC1,
MT2701_AUD_AUD_MUX2_SEL, MT2701_TOP_AUD_A1SYS,
MT2701_AUD_AUD_MUX1_DIV, MT2701_TOP_AUD_A2SYS,
MT2701_AUD_AUD_MUX2_DIV, MT2701_AUDSYS_AFE,
MT2701_AUD_AUD_48K_TIMING, MT2701_AUDSYS_AFE_CONN,
MT2701_AUD_AUD_44K_TIMING, MT2701_AUDSYS_A1SYS,
MT2701_AUD_AUDPLL_MUX_SEL, MT2701_AUDSYS_A2SYS,
MT2701_AUD_APLL_SEL, MT2701_BASE_CLK_NUM,
MT2701_AUD_AUD1PLL_98M,
MT2701_AUD_AUD2PLL_90M,
MT2701_AUD_HADDS2PLL_98M,
MT2701_AUD_HADDS2PLL_294M,
MT2701_AUD_AUDPLL,
MT2701_AUD_AUDPLL_D4,
MT2701_AUD_AUDPLL_D8,
MT2701_AUD_AUDPLL_D16,
MT2701_AUD_AUDPLL_D24,
MT2701_AUD_AUDINTBUS,
MT2701_AUD_CLK_26M,
MT2701_AUD_SYSPLL1_D4,
MT2701_AUD_AUD_K1_SRC_SEL,
MT2701_AUD_AUD_K2_SRC_SEL,
MT2701_AUD_AUD_K3_SRC_SEL,
MT2701_AUD_AUD_K4_SRC_SEL,
MT2701_AUD_AUD_K5_SRC_SEL,
MT2701_AUD_AUD_K6_SRC_SEL,
MT2701_AUD_AUD_K1_SRC_DIV,
MT2701_AUD_AUD_K2_SRC_DIV,
MT2701_AUD_AUD_K3_SRC_DIV,
MT2701_AUD_AUD_K4_SRC_DIV,
MT2701_AUD_AUD_K5_SRC_DIV,
MT2701_AUD_AUD_K6_SRC_DIV,
MT2701_AUD_AUD_I2S1_MCLK,
MT2701_AUD_AUD_I2S2_MCLK,
MT2701_AUD_AUD_I2S3_MCLK,
MT2701_AUD_AUD_I2S4_MCLK,
MT2701_AUD_AUD_I2S5_MCLK,
MT2701_AUD_AUD_I2S6_MCLK,
MT2701_AUD_ASM_M_SEL,
MT2701_AUD_ASM_H_SEL,
MT2701_AUD_UNIVPLL2_D4,
MT2701_AUD_UNIVPLL2_D2,
MT2701_AUD_SYSPLL_D5,
MT2701_CLOCK_NUM
}; };
static const unsigned int mt2701_afe_backup_list[] = { static const unsigned int mt2701_afe_backup_list[] = {
...@@ -139,12 +94,8 @@ static const unsigned int mt2701_afe_backup_list[] = { ...@@ -139,12 +94,8 @@ static const unsigned int mt2701_afe_backup_list[] = {
AFE_MEMIF_PBUF_SIZE, AFE_MEMIF_PBUF_SIZE,
}; };
struct snd_pcm_substream;
struct mtk_base_irq_data;
struct mt2701_i2s_data { struct mt2701_i2s_data {
int i2s_ctrl_reg; int i2s_ctrl_reg;
int i2s_pwn_shift;
int i2s_asrc_fs_shift; int i2s_asrc_fs_shift;
int i2s_asrc_fs_mask; int i2s_asrc_fs_mask;
}; };
...@@ -160,12 +111,18 @@ struct mt2701_i2s_path { ...@@ -160,12 +111,18 @@ struct mt2701_i2s_path {
int mclk_rate; int mclk_rate;
int on[I2S_DIR_NUM]; int on[I2S_DIR_NUM];
int occupied[I2S_DIR_NUM]; int occupied[I2S_DIR_NUM];
const struct mt2701_i2s_data *i2s_data[2]; const struct mt2701_i2s_data *i2s_data[I2S_DIR_NUM];
struct clk *hop_ck[I2S_DIR_NUM];
struct clk *sel_ck;
struct clk *div_ck;
struct clk *mclk_ck;
struct clk *asrco_ck;
}; };
struct mt2701_afe_private { struct mt2701_afe_private {
struct clk *clocks[MT2701_CLOCK_NUM];
struct mt2701_i2s_path i2s_path[MT2701_I2S_NUM]; struct mt2701_i2s_path i2s_path[MT2701_I2S_NUM];
struct clk *base_ck[MT2701_BASE_CLK_NUM];
struct clk *mrgif_ck;
bool mrg_enable[MT2701_STREAM_DIR_NUM]; bool mrg_enable[MT2701_STREAM_DIR_NUM];
}; };
......
sound/soc/mediatek/mt2701/mt2701-afe-pcm.c
View file @ 19c2d849
This diff is collapsed.
sound/soc/mediatek/mt2701/mt2701-reg.h
View file @ 19c2d849
...@@ -17,17 +17,6 @@ ...@@ -17,17 +17,6 @@
#ifndef _MT2701_REG_H_ #ifndef _MT2701_REG_H_
#define _MT2701_REG_H_ #define _MT2701_REG_H_
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/pm_runtime.h>
#include <sound/soc.h>
#include "mt2701-afe-common.h"
/*****************************************************************************
* R E G I S T E R D E F I N I T I O N
*****************************************************************************/
#define AUDIO_TOP_CON0 0x0000 #define AUDIO_TOP_CON0 0x0000
#define AUDIO_TOP_CON4 0x0010 #define AUDIO_TOP_CON4 0x0010
#define AUDIO_TOP_CON5 0x0014 #define AUDIO_TOP_CON5 0x0014
...@@ -109,18 +98,6 @@ ...@@ -109,18 +98,6 @@
#define AFE_DAI_BASE 0x1370 #define AFE_DAI_BASE 0x1370
#define AFE_DAI_CUR 0x137c #define AFE_DAI_CUR 0x137c
/* AUDIO_TOP_CON0 (0x0000) */
#define AUDIO_TOP_CON0_A1SYS_A2SYS_ON (0x3 << 0)
#define AUDIO_TOP_CON0_PDN_AFE (0x1 << 2)
#define AUDIO_TOP_CON0_PDN_APLL_CK (0x1 << 23)
/* AUDIO_TOP_CON4 (0x0010) */
#define AUDIO_TOP_CON4_I2SO1_PWN (0x1 << 6)
#define AUDIO_TOP_CON4_PDN_A1SYS (0x1 << 21)
#define AUDIO_TOP_CON4_PDN_A2SYS (0x1 << 22)
#define AUDIO_TOP_CON4_PDN_AFE_CONN (0x1 << 23)
#define AUDIO_TOP_CON4_PDN_MRGIF (0x1 << 25)
/* AFE_DAIBT_CON0 (0x001c) */ /* AFE_DAIBT_CON0 (0x001c) */
#define AFE_DAIBT_CON0_DAIBT_EN (0x1 << 0) #define AFE_DAIBT_CON0_DAIBT_EN (0x1 << 0)
#define AFE_DAIBT_CON0_BT_FUNC_EN (0x1 << 1) #define AFE_DAIBT_CON0_BT_FUNC_EN (0x1 << 1)
...@@ -137,22 +114,8 @@ ...@@ -137,22 +114,8 @@
#define AFE_MRGIF_CON_I2S_MODE_MASK (0xf << 20) #define AFE_MRGIF_CON_I2S_MODE_MASK (0xf << 20)
#define AFE_MRGIF_CON_I2S_MODE_32K (0x4 << 20) #define AFE_MRGIF_CON_I2S_MODE_32K (0x4 << 20)
/* ASYS_I2SO1_CON (0x061c) */ /* ASYS_TOP_CON (0x0600) */
#define ASYS_I2SO1_CON_FS (0x1f << 8) #define ASYS_TOP_CON_ASYS_TIMING_ON (0x3 << 0)
#define ASYS_I2SO1_CON_FS_SET(x) ((x) << 8)
#define ASYS_I2SO1_CON_MULTI_CH (0x1 << 16)
#define ASYS_I2SO1_CON_SIDEGEN (0x1 << 30)
#define ASYS_I2SO1_CON_I2S_EN (0x1 << 0)
/* 0:EIAJ 1:I2S */
#define ASYS_I2SO1_CON_I2S_MODE (0x1 << 3)
#define ASYS_I2SO1_CON_WIDE_MODE (0x1 << 1)
#define ASYS_I2SO1_CON_WIDE_MODE_SET(x) ((x) << 1)
/* PWR2_TOP_CON (0x0634) */
#define PWR2_TOP_CON_INIT_VAL (0xffe1ffff)
/* ASYS_IRQ_CLR (0x07c0) */
#define ASYS_IRQ_CLR_ALL (0xffffffff)
/* PWR2_ASM_CON1 (0x1070) */ /* PWR2_ASM_CON1 (0x1070) */
#define PWR2_ASM_CON1_INIT_VAL (0x492492) #define PWR2_ASM_CON1_INIT_VAL (0x492492)
...@@ -182,5 +145,4 @@ ...@@ -182,5 +145,4 @@
#define ASYS_I2S_CON_WIDE_MODE_SET(x) ((x) << 1) #define ASYS_I2S_CON_WIDE_MODE_SET(x) ((x) << 1)
#define ASYS_I2S_IN_PHASE_FIX (0x1 << 31) #define ASYS_I2S_IN_PHASE_FIX (0x1 << 31)
#define AFE_END_ADDR 0x15e0
#endif #endif
sound/soc/mediatek/mt8173/mt8173-rt5650-rt5514.c
View file @ 19c2d849
...@@ -37,8 +37,6 @@ static const struct snd_soc_dapm_route mt8173_rt5650_rt5514_routes[] = { ...@@ -37,8 +37,6 @@ static const struct snd_soc_dapm_route mt8173_rt5650_rt5514_routes[] = {
{"Sub DMIC1R", NULL, "Int Mic"}, {"Sub DMIC1R", NULL, "Int Mic"},
{"Headphone", NULL, "HPOL"}, {"Headphone", NULL, "HPOL"},
{"Headphone", NULL, "HPOR"}, {"Headphone", NULL, "HPOR"},
{"Headset Mic", NULL, "micbias1"},
{"Headset Mic", NULL, "micbias2"},
{"IN1P", NULL, "Headset Mic"}, {"IN1P", NULL, "Headset Mic"},
{"IN1N", NULL, "Headset Mic"}, {"IN1N", NULL, "Headset Mic"},
}; };
......
sound/soc/mediatek/mt8173/mt8173-rt5650-rt5676.c
View file @ 19c2d849
...@@ -40,8 +40,6 @@ static const struct snd_soc_dapm_route mt8173_rt5650_rt5676_routes[] = { ...@@ -40,8 +40,6 @@ static const struct snd_soc_dapm_route mt8173_rt5650_rt5676_routes[] = {
{"Headphone", NULL, "HPOL"}, {"Headphone", NULL, "HPOL"},
{"Headphone", NULL, "HPOR"}, {"Headphone", NULL, "HPOR"},
{"Headphone", NULL, "Sub AIF2TX"}, /* IF2 ADC to 5650 */ {"Headphone", NULL, "Sub AIF2TX"}, /* IF2 ADC to 5650 */
{"Headset Mic", NULL, "micbias1"},
{"Headset Mic", NULL, "micbias2"},
{"IN1P", NULL, "Headset Mic"}, {"IN1P", NULL, "Headset Mic"},
{"IN1N", NULL, "Headset Mic"}, {"IN1N", NULL, "Headset Mic"},
{"Sub AIF2RX", NULL, "Headset Mic"}, /* IF2 DAC from 5650 */ {"Sub AIF2RX", NULL, "Headset Mic"}, /* IF2 DAC from 5650 */
......
sound/soc/mediatek/mt8173/mt8173-rt5650.c
View file @ 19c2d849
...@@ -51,8 +51,6 @@ static const struct snd_soc_dapm_route mt8173_rt5650_routes[] = { ...@@ -51,8 +51,6 @@ static const struct snd_soc_dapm_route mt8173_rt5650_routes[] = {
{"DMIC R1", NULL, "Int Mic"}, {"DMIC R1", NULL, "Int Mic"},
{"Headphone", NULL, "HPOL"}, {"Headphone", NULL, "HPOL"},
{"Headphone", NULL, "HPOR"}, {"Headphone", NULL, "HPOR"},
{"Headset Mic", NULL, "micbias1"},
{"Headset Mic", NULL, "micbias2"},
{"IN1P", NULL, "Headset Mic"}, {"IN1P", NULL, "Headset Mic"},
{"IN1N", NULL, "Headset Mic"}, {"IN1N", NULL, "Headset Mic"},
}; };
......
sound/soc/mxs/mxs-sgtl5000.c
View file @ 19c2d849
...@@ -93,6 +93,14 @@ static struct snd_soc_dai_link mxs_sgtl5000_dai[] = { ...@@ -93,6 +93,14 @@ static struct snd_soc_dai_link mxs_sgtl5000_dai[] = {
}, },
}; };
static const struct snd_soc_dapm_widget mxs_sgtl5000_dapm_widgets[] = {
SND_SOC_DAPM_MIC("Mic Jack", NULL),
SND_SOC_DAPM_LINE("Line In Jack", NULL),
SND_SOC_DAPM_HP("Headphone Jack", NULL),
SND_SOC_DAPM_SPK("Line Out Jack", NULL),
SND_SOC_DAPM_SPK("Ext Spk", NULL),
};
static struct snd_soc_card mxs_sgtl5000 = { static struct snd_soc_card mxs_sgtl5000 = {
.name = "mxs_sgtl5000", .name = "mxs_sgtl5000",
.owner = THIS_MODULE, .owner = THIS_MODULE,
...@@ -141,10 +149,23 @@ static int mxs_sgtl5000_probe(struct platform_device *pdev) ...@@ -141,10 +149,23 @@ static int mxs_sgtl5000_probe(struct platform_device *pdev)
card->dev = &pdev->dev; card->dev = &pdev->dev;
if (of_find_property(np, "audio-routing", NULL)) {
card->dapm_widgets = mxs_sgtl5000_dapm_widgets;
card->num_dapm_widgets = ARRAY_SIZE(mxs_sgtl5000_dapm_widgets);
ret = snd_soc_of_parse_audio_routing(card, "audio-routing");
if (ret) {
dev_err(&pdev->dev, "failed to parse audio-routing (%d)\n",
ret);
return ret;
}
}
ret = devm_snd_soc_register_card(&pdev->dev, card); ret = devm_snd_soc_register_card(&pdev->dev, card);
if (ret) { if (ret) {
dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", if (ret != -EPROBE_DEFER)
ret); dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
ret);
return ret; return ret;
} }
......
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