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Commit 3d07f0e8 authored by Benjamin Herrenschmidt's avatar Benjamin Herrenschmidt
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Merge remote branch 'kumar/next' into next

parents 593adf31 bbfff72e
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Documentation/devicetree/bindings/net/can/fsl-flexcan.txt 0 → 100755
View file @ 3d07f0e8
CAN Device Tree Bindings
------------------------
2011 Freescale Semiconductor, Inc.
fsl,flexcan-v1.0 nodes
-----------------------
In addition to the required compatible-, reg- and interrupt-properties, you can
also specify which clock source shall be used for the controller.
CPI Clock- Can Protocol Interface Clock
This CLK_SRC bit of CTRL(control register) selects the clock source to
the CAN Protocol Interface(CPI) to be either the peripheral clock
(driven by the PLL) or the crystal oscillator clock. The selected clock
is the one fed to the prescaler to generate the Serial Clock (Sclock).
The PRESDIV field of CTRL(control register) controls a prescaler that
generates the Serial Clock (Sclock), whose period defines the
time quantum used to compose the CAN waveform.
Can Engine Clock Source
There are two sources for CAN clock
- Platform Clock It represents the bus clock
- Oscillator Clock
Peripheral Clock (PLL)
--------------
|
--------- -------------
| |CPI Clock | Prescaler | Sclock
| |---------------->| (1.. 256) |------------>
--------- -------------
| |
-------------- ---------------------CLK_SRC
Oscillator Clock
- fsl,flexcan-clock-source : CAN Engine Clock Source.This property selects
the peripheral clock. PLL clock is fed to the
prescaler to generate the Serial Clock (Sclock).
Valid values are "oscillator" and "platform"
"oscillator": CAN engine clock source is oscillator clock.
"platform" The CAN engine clock source is the bus clock
(platform clock).
- fsl,flexcan-clock-divider : for the reference and system clock, an additional
clock divider can be specified.
- clock-frequency: frequency required to calculate the bitrate for FlexCAN.
Note:
- v1.0 of flexcan-v1.0 represent the IP block version for P1010 SOC.
- P1010 does not have oscillator as the Clock Source.So the default
Clock Source is platform clock.
Examples:
can0@1c000 {
compatible = "fsl,flexcan-v1.0";
reg = <0x1c000 0x1000>;
interrupts = <48 0x2>;
interrupt-parent = <&mpic>;
fsl,flexcan-clock-source = "platform";
fsl,flexcan-clock-divider = <2>;
clock-frequency = <fixed by u-boot>;
};
Documentation/devicetree/bindings/powerpc/fsl/ifc.txt 0 → 100644
View file @ 3d07f0e8
Integrated Flash Controller
Properties:
- name : Should be ifc
- compatible : should contain "fsl,ifc". The version of the integrated
flash controller can be found in the IFC_REV register at
offset zero.
- #address-cells : Should be either two or three. The first cell is the
chipselect number, and the remaining cells are the
offset into the chipselect.
- #size-cells : Either one or two, depending on how large each chipselect
can be.
- reg : Offset and length of the register set for the device
- interrupts : IFC has two interrupts. The first one is the "common"
interrupt(CM_EVTER_STAT), and second is the NAND interrupt
(NAND_EVTER_STAT).
- ranges : Each range corresponds to a single chipselect, and covers
the entire access window as configured.
Child device nodes describe the devices connected to IFC such as NOR (e.g.
cfi-flash) and NAND (fsl,ifc-nand). There might be board specific devices
like FPGAs, CPLDs, etc.
Example:
ifc@ffe1e000 {
compatible = "fsl,ifc", "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
reg = <0x0 0xffe1e000 0 0x2000>;
interrupts = <16 2 19 2>;
/* NOR, NAND Flashes and CPLD on board */
ranges = <0x0 0x0 0x0 0xee000000 0x02000000
0x1 0x0 0x0 0xffa00000 0x00010000
0x3 0x0 0x0 0xffb00000 0x00020000>;
flash@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x2000000>;
bank-width = <2>;
device-width = <1>;
partition@0 {
/* 32MB for user data */
reg = <0x0 0x02000000>;
label = "NOR Data";
};
};
flash@1,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,ifc-nand";
reg = <0x1 0x0 0x10000>;
partition@0 {
/* This location must not be altered */
/* 1MB for u-boot Bootloader Image */
reg = <0x0 0x00100000>;
label = "NAND U-Boot Image";
read-only;
};
};
cpld@3,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,p1010rdb-cpld";
reg = <0x3 0x0 0x000001f>;
};
};
Documentation/devicetree/bindings/powerpc/fsl/mpic-timer.txt 0 → 100644
View file @ 3d07f0e8
* Freescale MPIC timers
Required properties:
- compatible: "fsl,mpic-global-timer"
- reg : Contains two regions. The first is the main timer register bank
(GTCCRxx, GTBCRxx, GTVPRxx, GTDRxx). The second is the timer control
register (TCRx) for the group.
- fsl,available-ranges: use <start count> style section to define which
timer interrupts can be used. This property is optional; without this,
all timers within the group can be used.
- interrupts: one interrupt per timer in the group, in order, starting
with timer zero. If timer-available-ranges is present, only the
interrupts that correspond to available timers shall be present.
Example:
/* Note that this requires #interrupt-cells to be 4 */
timer0: timer@41100 {
compatible = "fsl,mpic-global-timer";
reg = <0x41100 0x100 0x41300 4>;
/* Another AMP partition is using timers 0 and 1 */
fsl,available-ranges = <2 2>;
interrupts = <2 0 3 0
3 0 3 0>;
};
timer1: timer@42100 {
compatible = "fsl,mpic-global-timer";
reg = <0x42100 0x100 0x42300 4>;
interrupts = <4 0 3 0
5 0 3 0
6 0 3 0
7 0 3 0>;
};
Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
View file @ 3d07f0e8
......@@ -190,7 +190,7 @@ EXAMPLE 4
*/
timer0: timer@41100 {
compatible = "fsl,mpic-global-timer";
reg = <0x41100 0x100>;
reg = <0x41100 0x100 0x41300 4>;
interrupts = <0 0 3 0
1 0 3 0
2 0 3 0
......
arch/powerpc/boot/dts/p1020rdb.dts
View file @ 3d07f0e8
......@@ -9,12 +9,11 @@
* option) any later version.
*/
/dts-v1/;
/include/ "p1020si.dtsi"
/ {
model = "fsl,P1020";
model = "fsl,P1020RDB";
compatible = "fsl,P1020RDB";
#address-cells = <2>;
#size-cells = <2>;
aliases {
serial0 = &serial0;
......@@ -26,34 +25,11 @@ aliases {
pci1 = &pci1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,P1020@0 {
device_type = "cpu";
reg = <0x0>;
next-level-cache = <&L2>;
};
PowerPC,P1020@1 {
device_type = "cpu";
reg = <0x1>;
next-level-cache = <&L2>;
};
};
memory {
device_type = "memory";
};
localbus@ffe05000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
reg = <0 0xffe05000 0 0x1000>;
interrupts = <19 2>;
interrupt-parent = <&mpic>;
/* NOR, NAND Flashes and Vitesse 5 port L2 switch */
ranges = <0x0 0x0 0x0 0xef000000 0x01000000
......@@ -165,88 +141,14 @@ L2switch@2,0 {
};
soc@ffe00000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "fsl,p1020-immr", "simple-bus";
ranges = <0x0 0x0 0xffe00000 0x100000>;
bus-frequency = <0>; // Filled out by uboot.
ecm-law@0 {
compatible = "fsl,ecm-law";
reg = <0x0 0x1000>;
fsl,num-laws = <12>;
};
ecm@1000 {
compatible = "fsl,p1020-ecm", "fsl,ecm";
reg = <0x1000 0x1000>;
interrupts = <16 2>;
interrupt-parent = <&mpic>;
};
memory-controller@2000 {
compatible = "fsl,p1020-memory-controller";
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <16 2>;
};
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
rtc@68 {
compatible = "dallas,ds1339";
reg = <0x68>;
};
};
i2c@3100 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
reg = <0x3100 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <0>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <0>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
spi@7000 {
cell-index = <0>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,espi";
reg = <0x7000 0x1000>;
interrupts = <59 0x2>;
interrupt-parent = <&mpic>;
mode = "cpu";
fsl_m25p80@0 {
#address-cells = <1>;
......@@ -294,66 +196,7 @@ partition@900000 {
};
};
gpio: gpio-controller@f000 {
#gpio-cells = <2>;
compatible = "fsl,mpc8572-gpio";
reg = <0xf000 0x100>;
interrupts = <47 0x2>;
interrupt-parent = <&mpic>;
gpio-controller;
};
L2: l2-cache-controller@20000 {
compatible = "fsl,p1020-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
cache-size = <0x40000>; // L2,256K
interrupt-parent = <&mpic>;
interrupts = <16 2>;
};
dma@21300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,eloplus-dma";
reg = <0x21300 0x4>;
ranges = <0x0 0x21100 0x200>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupt-parent = <&mpic>;
interrupts = <20 2>;
};
dma-channel@80 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&mpic>;
interrupts = <21 2>;
};
dma-channel@100 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&mpic>;
interrupts = <22 2>;
};
dma-channel@180 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupt-parent = <&mpic>;
interrupts = <23 2>;
};
};
mdio@24000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,etsec2-mdio";
reg = <0x24000 0x1000 0xb0030 0x4>;
phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>;
......@@ -369,10 +212,6 @@ phy1: ethernet-phy@1 {
};
mdio@25000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,etsec2-tbi";
reg = <0x25000 0x1000 0xb1030 0x4>;
tbi0: tbi-phy@11 {
reg = <0x11>;
......@@ -381,97 +220,25 @@ tbi0: tbi-phy@11 {
};
enet0: ethernet@b0000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "network";
model = "eTSEC";
compatible = "fsl,etsec2";
fsl,num_rx_queues = <0x8>;
fsl,num_tx_queues = <0x8>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupt-parent = <&mpic>;
fixed-link = <1 1 1000 0 0>;
phy-connection-type = "rgmii-id";
queue-group@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0xb0000 0x1000>;
interrupts = <29 2 30 2 34 2>;
};
queue-group@1 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0xb4000 0x1000>;
interrupts = <17 2 18 2 24 2>;
};
};
enet1: ethernet@b1000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "network";
model = "eTSEC";
compatible = "fsl,etsec2";
fsl,num_rx_queues = <0x8>;
fsl,num_tx_queues = <0x8>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupt-parent = <&mpic>;
phy-handle = <&phy0>;
tbi-handle = <&tbi0>;
phy-connection-type = "sgmii";
queue-group@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0xb1000 0x1000>;
interrupts = <35 2 36 2 40 2>;
};
queue-group@1 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0xb5000 0x1000>;
interrupts = <51 2 52 2 67 2>;
};
};
enet2: ethernet@b2000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "network";
model = "eTSEC";
compatible = "fsl,etsec2";
fsl,num_rx_queues = <0x8>;
fsl,num_tx_queues = <0x8>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupt-parent = <&mpic>;
phy-handle = <&phy1>;
phy-connection-type = "rgmii-id";
queue-group@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0xb2000 0x1000>;
interrupts = <31 2 32 2 33 2>;
};
queue-group@1 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0xb6000 0x1000>;
interrupts = <25 2 26 2 27 2>;
};
};
usb@22000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl-usb2-dr";
reg = <0x22000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <28 0x2>;
phy_type = "ulpi";
};
......@@ -481,82 +248,23 @@ since U-Boot doesn't clear the status property when
it enables USB2. OTOH, U-Boot does create a new node
when there isn't any. So, just comment it out.
usb@23000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl-usb2-dr";
reg = <0x23000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <46 0x2>;
phy_type = "ulpi";
};
*/
sdhci@2e000 {
compatible = "fsl,p1020-esdhc", "fsl,esdhc";
reg = <0x2e000 0x1000>;
interrupts = <72 0x2>;
interrupt-parent = <&mpic>;
/* Filled in by U-Boot */
clock-frequency = <0>;
};
crypto@30000 {
compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
"fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
reg = <0x30000 0x10000>;
interrupts = <45 2 58 2>;
interrupt-parent = <&mpic>;
fsl,num-channels = <4>;
fsl,channel-fifo-len = <24>;
fsl,exec-units-mask = <0xbfe>;
fsl,descriptor-types-mask = <0x3ab0ebf>;
};
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
};
msi@41600 {
compatible = "fsl,p1020-msi", "fsl,mpic-msi";
reg = <0x41600 0x80>;
msi-available-ranges = <0 0x100>;
interrupts = <
0xe0 0
0xe1 0
0xe2 0
0xe3 0
0xe4 0
0xe5 0
0xe6 0
0xe7 0>;
interrupt-parent = <&mpic>;
};
global-utilities@e0000 { //global utilities block
compatible = "fsl,p1020-guts";
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
};
pci0: pcie@ffe09000 {
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0 0xffe09000 0 0x1000>;
bus-range = <0 255>;
ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <16 2>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0x0 0x0 0x1 &mpic 0x4 0x1
0000 0x0 0x0 0x2 &mpic 0x5 0x1
0000 0x0 0x0 0x3 &mpic 0x6 0x1
0000 0x0 0x0 0x4 &mpic 0x7 0x1
>;
pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
......@@ -573,18 +281,16 @@ pcie@0 {
};
pci1: pcie@ffe0a000 {
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0 0xffe0a000 0 0x1000>;
bus-range = <0 255>;
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <16 2>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0x0 0x0 0x1 &mpic 0x0 0x1
0000 0x0 0x0 0x2 &mpic 0x1 0x1
0000 0x0 0x0 0x3 &mpic 0x2 0x1
0000 0x0 0x0 0x4 &mpic 0x3 0x1
>;
pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
......
arch/powerpc/boot/dts/p1020rdb_camp_core0.dts 0 → 100644
View file @ 3d07f0e8
/*
* P1020 RDB Core0 Device Tree Source in CAMP mode.
*
* In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
* can be shared, all the other devices must be assigned to one core only.
* This dts file allows core0 to have memory, l2, i2c, spi, gpio, tdm, dma, usb,
* eth1, eth2, sdhc, crypto, global-util, message, pci0, pci1, msi.
*
* Please note to add "-b 0" for core0's dts compiling.
*
* Copyright 2011 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/include/ "p1020si.dtsi"
/ {
model = "fsl,P1020RDB";
compatible = "fsl,P1020RDB", "fsl,MPC85XXRDB-CAMP";
aliases {
ethernet1 = &enet1;
ethernet2 = &enet2;
serial0 = &serial0;
pci0 = &pci0;
pci1 = &pci1;
};
cpus {
PowerPC,P1020@1 {
status = "disabled";
};
};
memory {
device_type = "memory";
};
localbus@ffe05000 {
status = "disabled";
};
soc@ffe00000 {
i2c@3000 {
rtc@68 {
compatible = "dallas,ds1339";
reg = <0x68>;
};
};
serial1: serial@4600 {
status = "disabled";
};
spi@7000 {
fsl_m25p80@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,espi-flash";
reg = <0>;
linux,modalias = "fsl_m25p80";
spi-max-frequency = <40000000>;
partition@0 {
/* 512KB for u-boot Bootloader Image */
reg = <0x0 0x00080000>;
label = "SPI (RO) U-Boot Image";
read-only;
};
partition@80000 {
/* 512KB for DTB Image */
reg = <0x00080000 0x00080000>;
label = "SPI (RO) DTB Image";
read-only;
};
partition@100000 {
/* 4MB for Linux Kernel Image */
reg = <0x00100000 0x00400000>;
label = "SPI (RO) Linux Kernel Image";
read-only;
};
partition@500000 {
/* 4MB for Compressed RFS Image */
reg = <0x00500000 0x00400000>;
label = "SPI (RO) Compressed RFS Image";
read-only;
};
partition@900000 {
/* 7MB for JFFS2 based RFS */
reg = <0x00900000 0x00700000>;
label = "SPI (RW) JFFS2 RFS";
};
};
};
mdio@24000 {
phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>;
interrupts = <3 1>;
reg = <0x0>;
};
phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>;
interrupts = <2 1>;
reg = <0x1>;
};
};
mdio@25000 {
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
enet0: ethernet@b0000 {
status = "disabled";
};
enet1: ethernet@b1000 {
phy-handle = <&phy0>;
tbi-handle = <&tbi0>;
phy-connection-type = "sgmii";
};
enet2: ethernet@b2000 {
phy-handle = <&phy1>;
phy-connection-type = "rgmii-id";
};
usb@22000 {
phy_type = "ulpi";
};
/* USB2 is shared with localbus, so it must be disabled
by default. We can't put 'status = "disabled";' here
since U-Boot doesn't clear the status property when
it enables USB2. OTOH, U-Boot does create a new node
when there isn't any. So, just comment it out.
usb@23000 {
phy_type = "ulpi";
};
*/
mpic: pic@40000 {
protected-sources = <
42 29 30 34 /* serial1, enet0-queue-group0 */
17 18 24 45 /* enet0-queue-group1, crypto */
>;
};
};
pci0: pcie@ffe09000 {
ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0x0 0x0 0x1 &mpic 0x4 0x1
0000 0x0 0x0 0x2 &mpic 0x5 0x1
0000 0x0 0x0 0x3 &mpic 0x6 0x1
0000 0x0 0x0 0x4 &mpic 0x7 0x1
>;
pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x2000000 0x0 0xa0000000
0x2000000 0x0 0xa0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
pci1: pcie@ffe0a000 {
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0x0 0x0 0x1 &mpic 0x0 0x1
0000 0x0 0x0 0x2 &mpic 0x1 0x1
0000 0x0 0x0 0x3 &mpic 0x2 0x1
0000 0x0 0x0 0x4 &mpic 0x3 0x1
>;
pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x2000000 0x0 0x80000000
0x2000000 0x0 0x80000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
};
arch/powerpc/boot/dts/p1020rdb_camp_core1.dts 0 → 100644
View file @ 3d07f0e8
/*
* P1020 RDB Core1 Device Tree Source in CAMP mode.
*
* In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
* can be shared, all the other devices must be assigned to one core only.
* This dts allows core1 to have l2, eth0, crypto.
*
* Please note to add "-b 1" for core1's dts compiling.
*
* Copyright 2011 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/include/ "p1020si.dtsi"
/ {
model = "fsl,P1020RDB";
compatible = "fsl,P1020RDB", "fsl,MPC85XXRDB-CAMP";
aliases {
ethernet0 = &enet0;
serial0 = &serial1;
};
cpus {
PowerPC,P1020@0 {
status = "disabled";
};
};
memory {
device_type = "memory";
};
localbus@ffe05000 {
status = "disabled";
};
soc@ffe00000 {
ecm-law@0 {
status = "disabled";
};
ecm@1000 {
status = "disabled";
};
memory-controller@2000 {
status = "disabled";
};
i2c@3000 {
status = "disabled";
};
i2c@3100 {
status = "disabled";
};
serial0: serial@4500 {
status = "disabled";
};
spi@7000 {
status = "disabled";
};
gpio: gpio-controller@f000 {
status = "disabled";
};
dma@21300 {
status = "disabled";
};
mdio@24000 {
status = "disabled";
};
mdio@25000 {
status = "disabled";
};
enet0: ethernet@b0000 {
fixed-link = <1 1 1000 0 0>;
phy-connection-type = "rgmii-id";
};
enet1: ethernet@b1000 {
status = "disabled";
};
enet2: ethernet@b2000 {
status = "disabled";
};
usb@22000 {
status = "disabled";
};
sdhci@2e000 {
status = "disabled";
};
mpic: pic@40000 {
protected-sources = <
16 /* ecm, mem, L2, pci0, pci1 */
43 42 59 /* i2c, serial0, spi */
47 63 62 /* gpio, tdm */
20 21 22 23 /* dma */
03 02 /* mdio */
35 36 40 /* enet1-queue-group0 */
51 52 67 /* enet1-queue-group1 */
31 32 33 /* enet2-queue-group0 */
25 26 27 /* enet2-queue-group1 */
28 72 58 /* usb, sdhci, crypto */
0xb0 0xb1 0xb2 /* message */
0xb3 0xb4 0xb5
0xb6 0xb7
0xe0 0xe1 0xe2 /* msi */
0xe3 0xe4 0xe5
0xe6 0xe7 /* sdhci, crypto , pci */
>;
};
msi@41600 {
status = "disabled";
};
global-utilities@e0000 { //global utilities block
status = "disabled";
};
};
pci0: pcie@ffe09000 {
status = "disabled";
};
pci1: pcie@ffe0a000 {
status = "disabled";
};
};
arch/powerpc/boot/dts/p1020si.dtsi 0 → 100644
View file @ 3d07f0e8
/*
* P1020si Device Tree Source
*
* Copyright 2011 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/dts-v1/;
/ {
compatible = "fsl,P1020";
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,P1020@0 {
device_type = "cpu";
reg = <0x0>;
next-level-cache = <&L2>;
};
PowerPC,P1020@1 {
device_type = "cpu";
reg = <0x1>;
next-level-cache = <&L2>;
};
};
localbus@ffe05000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
reg = <0 0xffe05000 0 0x1000>;
interrupts = <19 2>;
interrupt-parent = <&mpic>;
};
soc@ffe00000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "fsl,p1020-immr", "simple-bus";
ranges = <0x0 0x0 0xffe00000 0x100000>;
bus-frequency = <0>; // Filled out by uboot.
ecm-law@0 {
compatible = "fsl,ecm-law";
reg = <0x0 0x1000>;
fsl,num-laws = <12>;
};
ecm@1000 {
compatible = "fsl,p1020-ecm", "fsl,ecm";
reg = <0x1000 0x1000>;
interrupts = <16 2>;
interrupt-parent = <&mpic>;
};
memory-controller@2000 {
compatible = "fsl,p1020-memory-controller";
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <16 2>;
};
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
i2c@3100 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
reg = <0x3100 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <0>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <0>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
spi@7000 {
cell-index = <0>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,espi";
reg = <0x7000 0x1000>;
interrupts = <59 0x2>;
interrupt-parent = <&mpic>;
mode = "cpu";
};
gpio: gpio-controller@f000 {
#gpio-cells = <2>;
compatible = "fsl,mpc8572-gpio";
reg = <0xf000 0x100>;
interrupts = <47 0x2>;
interrupt-parent = <&mpic>;
gpio-controller;
};
L2: l2-cache-controller@20000 {
compatible = "fsl,p1020-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
cache-size = <0x40000>; // L2,256K
interrupt-parent = <&mpic>;
interrupts = <16 2>;
};
dma@21300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,eloplus-dma";
reg = <0x21300 0x4>;
ranges = <0x0 0x21100 0x200>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupt-parent = <&mpic>;
interrupts = <20 2>;
};
dma-channel@80 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&mpic>;
interrupts = <21 2>;
};
dma-channel@100 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&mpic>;
interrupts = <22 2>;
};
dma-channel@180 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupt-parent = <&mpic>;
interrupts = <23 2>;
};
};
mdio@24000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,etsec2-mdio";
reg = <0x24000 0x1000 0xb0030 0x4>;
};
mdio@25000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,etsec2-tbi";
reg = <0x25000 0x1000 0xb1030 0x4>;
};
enet0: ethernet@b0000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "network";
model = "eTSEC";
compatible = "fsl,etsec2";
fsl,num_rx_queues = <0x8>;
fsl,num_tx_queues = <0x8>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupt-parent = <&mpic>;
queue-group@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0xb0000 0x1000>;
interrupts = <29 2 30 2 34 2>;
};
queue-group@1 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0xb4000 0x1000>;
interrupts = <17 2 18 2 24 2>;
};
};
enet1: ethernet@b1000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "network";
model = "eTSEC";
compatible = "fsl,etsec2";
fsl,num_rx_queues = <0x8>;
fsl,num_tx_queues = <0x8>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupt-parent = <&mpic>;
queue-group@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0xb1000 0x1000>;
interrupts = <35 2 36 2 40 2>;
};
queue-group@1 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0xb5000 0x1000>;
interrupts = <51 2 52 2 67 2>;
};
};
enet2: ethernet@b2000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "network";
model = "eTSEC";
compatible = "fsl,etsec2";
fsl,num_rx_queues = <0x8>;
fsl,num_tx_queues = <0x8>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupt-parent = <&mpic>;
queue-group@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0xb2000 0x1000>;
interrupts = <31 2 32 2 33 2>;
};
queue-group@1 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0xb6000 0x1000>;
interrupts = <25 2 26 2 27 2>;
};
};
usb@22000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl-usb2-dr";
reg = <0x22000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <28 0x2>;
};
/* USB2 is shared with localbus, so it must be disabled
by default. We can't put 'status = "disabled";' here
since U-Boot doesn't clear the status property when
it enables USB2. OTOH, U-Boot does create a new node
when there isn't any. So, just comment it out.
usb@23000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl-usb2-dr";
reg = <0x23000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <46 0x2>;
phy_type = "ulpi";
};
*/
sdhci@2e000 {
compatible = "fsl,p1020-esdhc", "fsl,esdhc";
reg = <0x2e000 0x1000>;
interrupts = <72 0x2>;
interrupt-parent = <&mpic>;
/* Filled in by U-Boot */
clock-frequency = <0>;
};
crypto@30000 {
compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
"fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
reg = <0x30000 0x10000>;
interrupts = <45 2 58 2>;
interrupt-parent = <&mpic>;
fsl,num-channels = <4>;
fsl,channel-fifo-len = <24>;
fsl,exec-units-mask = <0xbfe>;
fsl,descriptor-types-mask = <0x3ab0ebf>;
};
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
};
msi@41600 {
compatible = "fsl,p1020-msi", "fsl,mpic-msi";
reg = <0x41600 0x80>;
msi-available-ranges = <0 0x100>;
interrupts = <
0xe0 0
0xe1 0
0xe2 0
0xe3 0
0xe4 0
0xe5 0
0xe6 0
0xe7 0>;
interrupt-parent = <&mpic>;
};
global-utilities@e0000 { //global utilities block
compatible = "fsl,p1020-guts","fsl,p2020-guts";
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
};
pci0: pcie@ffe09000 {
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0 0xffe09000 0 0x1000>;
bus-range = <0 255>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <16 2>;
};
pci1: pcie@ffe0a000 {
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0 0xffe0a000 0 0x1000>;
bus-range = <0 255>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <16 2>;
};
};
arch/powerpc/boot/dts/p1022ds.dts
View file @ 3d07f0e8
......@@ -52,7 +52,7 @@ localbus@fffe05000 {
#size-cells = <1>;
compatible = "fsl,p1022-elbc", "fsl,elbc", "simple-bus";
reg = <0 0xffe05000 0 0x1000>;
interrupts = <19 2>;
interrupts = <19 2 0 0>;
ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
0x1 0x0 0xf 0xe0000000 0x08000000
......@@ -157,7 +157,7 @@ board-control@3,0 {
* IRQ8 is generated if the "EVENT" switch is pressed
* and PX_CTL[EVESEL] is set to 00.
*/
interrupts = <8 8>;
interrupts = <8 8 0 0>;
};
};
......@@ -178,13 +178,13 @@ ecm-law@0 {
ecm@1000 {
compatible = "fsl,p1022-ecm", "fsl,ecm";
reg = <0x1000 0x1000>;
interrupts = <16 2>;
interrupts = <16 2 0 0>;
};
memory-controller@2000 {
compatible = "fsl,p1022-memory-controller";
reg = <0x2000 0x1000>;
interrupts = <16 2>;
interrupts = <16 2 0 0>;
};
i2c@3000 {
......@@ -193,7 +193,7 @@ i2c@3000 {
cell-index = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <43 2>;
interrupts = <43 2 0 0>;
dfsrr;
};
......@@ -203,7 +203,7 @@ i2c@3100 {
cell-index = <1>;
compatible = "fsl-i2c";
reg = <0x3100 0x100>;
interrupts = <43 2>;
interrupts = <43 2 0 0>;
dfsrr;
wm8776:codec@1a {
......@@ -220,7 +220,7 @@ serial0: serial@4500 {
compatible = "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <0>;
interrupts = <42 2>;
interrupts = <42 2 0 0>;
};
serial1: serial@4600 {
......@@ -229,7 +229,7 @@ serial1: serial@4600 {
compatible = "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <0>;
interrupts = <42 2>;
interrupts = <42 2 0 0>;
};
spi@7000 {
......@@ -238,7 +238,7 @@ spi@7000 {
#size-cells = <0>;
compatible = "fsl,espi";
reg = <0x7000 0x1000>;
interrupts = <59 0x2>;
interrupts = <59 0x2 0 0>;
espi,num-ss-bits = <4>;
mode = "cpu";
......@@ -275,7 +275,7 @@ ssi@15000 {
compatible = "fsl,mpc8610-ssi";
cell-index = <0>;
reg = <0x15000 0x100>;
interrupts = <75 2>;
interrupts = <75 2 0 0>;
fsl,mode = "i2s-slave";
codec-handle = <&wm8776>;
fsl,playback-dma = <&dma00>;
......@@ -294,25 +294,25 @@ dma00: dma-channel@0 {
compatible = "fsl,ssi-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupts = <76 2>;
interrupts = <76 2 0 0>;
};
dma01: dma-channel@80 {
compatible = "fsl,ssi-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupts = <77 2>;
interrupts = <77 2 0 0>;
};
dma-channel@100 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupts = <78 2>;
interrupts = <78 2 0 0>;
};
dma-channel@180 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupts = <79 2>;
interrupts = <79 2 0 0>;
};
};
......@@ -320,7 +320,7 @@ gpio: gpio-controller@f000 {
#gpio-cells = <2>;
compatible = "fsl,mpc8572-gpio";
reg = <0xf000 0x100>;
interrupts = <47 0x2>;
interrupts = <47 0x2 0 0>;
gpio-controller;
};
......@@ -329,7 +329,7 @@ L2: l2-cache-controller@20000 {
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
cache-size = <0x40000>; // L2, 256K
interrupts = <16 2>;
interrupts = <16 2 0 0>;
};
dma@21300 {
......@@ -343,25 +343,25 @@ dma-channel@0 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupts = <20 2>;
interrupts = <20 2 0 0>;
};
dma-channel@80 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupts = <21 2>;
interrupts = <21 2 0 0>;
};
dma-channel@100 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupts = <22 2>;
interrupts = <22 2 0 0>;
};
dma-channel@180 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupts = <23 2>;
interrupts = <23 2 0 0>;
};
};
......@@ -370,7 +370,7 @@ usb@22000 {
#size-cells = <0>;
compatible = "fsl-usb2-dr";
reg = <0x22000 0x1000>;
interrupts = <28 0x2>;
interrupts = <28 0x2 0 0>;
phy_type = "ulpi";
};
......@@ -381,11 +381,11 @@ mdio@24000 {
reg = <0x24000 0x1000 0xb0030 0x4>;
phy0: ethernet-phy@0 {
interrupts = <3 1>;
interrupts = <3 1 0 0>;
reg = <0x1>;
};
phy1: ethernet-phy@1 {
interrupts = <9 1>;
interrupts = <9 1 0 0>;
reg = <0x2>;
};
};
......@@ -416,13 +416,13 @@ queue-group@0{
#address-cells = <1>;
#size-cells = <1>;
reg = <0xB0000 0x1000>;
interrupts = <29 2 30 2 34 2>;
interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
};
queue-group@1{
#address-cells = <1>;
#size-cells = <1>;
reg = <0xB4000 0x1000>;
interrupts = <17 2 18 2 24 2>;
interrupts = <17 2 0 0 18 2 0 0 24 2 0 0>;
};
};
......@@ -443,20 +443,20 @@ queue-group@0{
#address-cells = <1>;
#size-cells = <1>;
reg = <0xB1000 0x1000>;
interrupts = <35 2 36 2 40 2>;
interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
};
queue-group@1{
#address-cells = <1>;
#size-cells = <1>;
reg = <0xB5000 0x1000>;
interrupts = <51 2 52 2 67 2>;
interrupts = <51 2 0 0 52 2 0 0 67 2 0 0>;
};
};
sdhci@2e000 {
compatible = "fsl,p1022-esdhc", "fsl,esdhc";
reg = <0x2e000 0x1000>;
interrupts = <72 0x2>;
interrupts = <72 0x2 0 0>;
fsl,sdhci-auto-cmd12;
/* Filled in by U-Boot */
clock-frequency = <0>;
......@@ -467,7 +467,7 @@ crypto@30000 {
"fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
"fsl,sec2.0";
reg = <0x30000 0x10000>;
interrupts = <45 2 58 2>;
interrupts = <45 2 0 0 58 2 0 0>;
fsl,num-channels = <4>;
fsl,channel-fifo-len = <24>;
fsl,exec-units-mask = <0x97c>;
......@@ -478,14 +478,14 @@ sata@18000 {
compatible = "fsl,p1022-sata", "fsl,pq-sata-v2";
reg = <0x18000 0x1000>;
cell-index = <1>;
interrupts = <74 0x2>;
interrupts = <74 0x2 0 0>;
};
sata@19000 {
compatible = "fsl,p1022-sata", "fsl,pq-sata-v2";
reg = <0x19000 0x1000>;
cell-index = <2>;
interrupts = <41 0x2>;
interrupts = <41 0x2 0 0>;
};
power@e0070{
......@@ -496,21 +496,33 @@ power@e0070{
display@10000 {
compatible = "fsl,diu", "fsl,p1022-diu";
reg = <0x10000 1000>;
interrupts = <64 2>;
interrupts = <64 2 0 0>;
};
timer@41100 {
compatible = "fsl,mpic-global-timer";
reg = <0x41100 0x204>;
interrupts = <0xf7 0x2>;
reg = <0x41100 0x100 0x41300 4>;
interrupts = <0 0 3 0
1 0 3 0
2 0 3 0
3 0 3 0>;
};
timer@42100 {
compatible = "fsl,mpic-global-timer";
reg = <0x42100 0x100 0x42300 4>;
interrupts = <4 0 3 0
5 0 3 0
6 0 3 0
7 0 3 0>;
};
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
#interrupt-cells = <4>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
compatible = "fsl,mpic";
device_type = "open-pic";
};
......@@ -519,14 +531,14 @@ msi@41600 {
reg = <0x41600 0x80>;
msi-available-ranges = <0 0x100>;
interrupts = <
0xe0 0
0xe1 0
0xe2 0
0xe3 0
0xe4 0
0xe5 0
0xe6 0
0xe7 0>;
0xe0 0 0 0
0xe1 0 0 0
0xe2 0 0 0
0xe3 0 0 0
0xe4 0 0 0
0xe5 0 0 0
0xe6 0 0 0
0xe7 0 0 0>;
};
global-utilities@e0000 { //global utilities block
......@@ -547,7 +559,7 @@ pci0: pcie@fffe09000 {
ranges = <0x2000000 0x0 0xa0000000 0xc 0x20000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
clock-frequency = <33333333>;
interrupts = <16 2>;
interrupts = <16 2 0 0>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
......@@ -582,7 +594,7 @@ pci1: pcie@fffe0a000 {
ranges = <0x2000000 0x0 0xc0000000 0xc 0x40000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x10000>;
clock-frequency = <33333333>;
interrupts = <16 2>;
interrupts = <16 2 0 0>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
......@@ -618,7 +630,7 @@ pci2: pcie@fffe0b000 {
ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
clock-frequency = <33333333>;
interrupts = <16 2>;
interrupts = <16 2 0 0>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
......
arch/powerpc/boot/dts/p2020ds.dts
View file @ 3d07f0e8
This diff is collapsed.
arch/powerpc/boot/dts/p2020rdb.dts
View file @ 3d07f0e8
This diff is collapsed.
arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
View file @ 3d07f0e8
......@@ -14,12 +14,11 @@
* option) any later version.
*/
/dts-v1/;
/include/ "p2020si.dtsi"
/ {
model = "fsl,P2020";
model = "fsl,P2020RDB";
compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP";
#address-cells = <2>;
#size-cells = <2>;
aliases {
ethernet1 = &enet1;
......@@ -29,91 +28,33 @@ aliases {
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,P2020@0 {
device_type = "cpu";
reg = <0x0>;
next-level-cache = <&L2>;
PowerPC,P2020@1 {
status = "disabled";
};
};
memory {
device_type = "memory";
};
soc@ffe00000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "fsl,p2020-immr", "simple-bus";
ranges = <0x0 0x0 0xffe00000 0x100000>;
bus-frequency = <0>; // Filled out by uboot.
ecm-law@0 {
compatible = "fsl,ecm-law";
reg = <0x0 0x1000>;
fsl,num-laws = <12>;
};
ecm@1000 {
compatible = "fsl,p2020-ecm", "fsl,ecm";
reg = <0x1000 0x1000>;
interrupts = <17 2>;
interrupt-parent = <&mpic>;
};
memory-controller@2000 {
compatible = "fsl,p2020-memory-controller";
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
};
localbus@ffe05000 {
status = "disabled";
};
soc@ffe00000 {
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
rtc@68 {
compatible = "dallas,ds1339";
reg = <0x68>;
};
};
i2c@3100 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
reg = <0x3100 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <0>;
serial1: serial@4600 {
status = "disabled";
};
spi@7000 {
cell-index = <0>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,espi";
reg = <0x7000 0x1000>;
interrupts = <59 0x2>;
interrupt-parent = <&mpic>;
mode = "cpu";
fsl_m25p80@0 {
#address-cells = <1>;
......@@ -161,76 +102,15 @@ partition@900000 {
};
};
gpio: gpio-controller@f000 {
#gpio-cells = <2>;
compatible = "fsl,mpc8572-gpio";
reg = <0xf000 0x100>;
interrupts = <47 0x2>;
interrupt-parent = <&mpic>;
gpio-controller;
};
L2: l2-cache-controller@20000 {
compatible = "fsl,p2020-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
cache-size = <0x80000>; // L2,512K
interrupt-parent = <&mpic>;
interrupts = <16 2>;
};
dma@21300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,eloplus-dma";
reg = <0x21300 0x4>;
ranges = <0x0 0x21100 0x200>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupt-parent = <&mpic>;
interrupts = <20 2>;
};
dma-channel@80 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&mpic>;
interrupts = <21 2>;
};
dma-channel@100 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&mpic>;
interrupts = <22 2>;
};
dma-channel@180 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupt-parent = <&mpic>;
interrupts = <23 2>;
};
dma@c300 {
status = "disabled";
};
usb@22000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl-usb2-dr";
reg = <0x22000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <28 0x2>;
phy_type = "ulpi";
};
mdio@24520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <0x24520 0x20>;
phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>;
......@@ -245,29 +125,21 @@ phy1: ethernet-phy@1 {
};
mdio@25520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x26520 0x20>;
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
mdio@26520 {
status = "disabled";
};
enet0: ethernet@24000 {
status = "disabled";
};
enet1: ethernet@25000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <1>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x25000 0x1000>;
ranges = <0x0 0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <35 2 36 2 40 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi0>;
phy-handle = <&phy0>;
phy-connection-type = "sgmii";
......@@ -275,49 +147,12 @@ enet1: ethernet@25000 {
};
enet2: ethernet@26000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <2>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x26000 0x1000>;
ranges = <0x0 0x26000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <31 2 32 2 33 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy1>;
phy-connection-type = "rgmii-id";
};
sdhci@2e000 {
compatible = "fsl,p2020-esdhc", "fsl,esdhc";
reg = <0x2e000 0x1000>;
interrupts = <72 0x2>;
interrupt-parent = <&mpic>;
/* Filled in by U-Boot */
clock-frequency = <0>;
};
crypto@30000 {
compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
"fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
reg = <0x30000 0x10000>;
interrupts = <45 2 58 2>;
interrupt-parent = <&mpic>;
fsl,num-channels = <4>;
fsl,channel-fifo-len = <24>;
fsl,exec-units-mask = <0xbfe>;
fsl,descriptor-types-mask = <0x3ab0ebf>;
};
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
protected-sources = <
42 76 77 78 79 /* serial1 , dma2 */
29 30 34 26 /* enet0, pci1 */
......@@ -326,26 +161,28 @@ mpic: pic@40000 {
>;
};
global-utilities@e0000 {
compatible = "fsl,p2020-guts";
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
msi@41600 {
status = "disabled";
};
};
pci0: pcie@ffe09000 {
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0 0xffe09000 0 0x1000>;
bus-range = <0 255>;
pci0: pcie@ffe08000 {
status = "disabled";
};
pci1: pcie@ffe09000 {
ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <25 2>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0x0 0x0 0x1 &mpic 0x4 0x1
0000 0x0 0x0 0x2 &mpic 0x5 0x1
0000 0x0 0x0 0x3 &mpic 0x6 0x1
0000 0x0 0x0 0x4 &mpic 0x7 0x1
>;
pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
......@@ -360,4 +197,8 @@ pcie@0 {
0x0 0x100000>;
};
};
pci2: pcie@ffe0a000 {
status = "disabled";
};
};
arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
View file @ 3d07f0e8
......@@ -15,27 +15,21 @@
* option) any later version.
*/
/dts-v1/;
/include/ "p2020si.dtsi"
/ {
model = "fsl,P2020";
model = "fsl,P2020RDB";
compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP";
#address-cells = <2>;
#size-cells = <2>;
aliases {
ethernet0 = &enet0;
serial0 = &serial0;
serial0 = &serial1;
pci1 = &pci1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,P2020@1 {
device_type = "cpu";
reg = <0x1>;
next-level-cache = <&L2>;
PowerPC,P2020@0 {
status = "disabled";
};
};
......@@ -43,20 +37,37 @@ memory {
device_type = "memory";
};
localbus@ffe05000 {
status = "disabled";
};
soc@ffe00000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "fsl,p2020-immr", "simple-bus";
ranges = <0x0 0x0 0xffe00000 0x100000>;
bus-frequency = <0>; // Filled out by uboot.
serial0: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <0>;
ecm-law@0 {
status = "disabled";
};
ecm@1000 {
status = "disabled";
};
memory-controller@2000 {
status = "disabled";
};
i2c@3000 {
status = "disabled";
};
i2c@3100 {
status = "disabled";
};
serial0: serial@4500 {
status = "disabled";
};
spi@7000 {
status = "disabled";
};
dma@c300 {
......@@ -96,6 +107,10 @@ dma-channel@180 {
};
};
gpio: gpio-controller@f000 {
status = "disabled";
};
L2: l2-cache-controller@20000 {
compatible = "fsl,p2020-l2-cache-controller";
reg = <0x20000 0x1000>;
......@@ -104,31 +119,49 @@ L2: l2-cache-controller@20000 {
interrupt-parent = <&mpic>;
};
dma@21300 {
status = "disabled";
};
usb@22000 {
status = "disabled";
};
mdio@24520 {
status = "disabled";
};
mdio@25520 {
status = "disabled";
};
mdio@26520 {
status = "disabled";
};
enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <0>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
ranges = <0x0 0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>;
fixed-link = <1 1 1000 0 0>;
phy-connection-type = "rgmii-id";
};
enet1: ethernet@25000 {
status = "disabled";
};
enet2: ethernet@26000 {
status = "disabled";
};
sdhci@2e000 {
status = "disabled";
};
crypto@30000 {
status = "disabled";
};
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
protected-sources = <
17 18 43 42 59 47 /*ecm, mem, i2c, serial0, spi,gpio */
16 20 21 22 23 28 /* L2, dma1, USB */
......@@ -152,21 +185,32 @@ msi@41600 {
0xe7 0>;
interrupt-parent = <&mpic>;
};
global-utilities@e0000 { //global utilities block
status = "disabled";
};
};
pci1: pcie@ffe0a000 {
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0 0xffe0a000 0 0x1000>;
bus-range = <0 255>;
pci0: pcie@ffe08000 {
status = "disabled";
};
pci1: pcie@ffe09000 {
status = "disabled";
};
pci2: pcie@ffe0a000 {
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <26 2>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0x0 0x0 0x1 &mpic 0x0 0x1
0000 0x0 0x0 0x2 &mpic 0x1 0x1
0000 0x0 0x0 0x3 &mpic 0x2 0x1
0000 0x0 0x0 0x4 &mpic 0x3 0x1
>;
pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
......
arch/powerpc/boot/dts/p2020si.dtsi 0 → 100644
View file @ 3d07f0e8
/*
* P2020 Device Tree Source
*
* Copyright 2011 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/dts-v1/;
/ {
compatible = "fsl,P2020";
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,P2020@0 {
device_type = "cpu";
reg = <0x0>;
next-level-cache = <&L2>;
};
PowerPC,P2020@1 {
device_type = "cpu";
reg = <0x1>;
next-level-cache = <&L2>;
};
};
localbus@ffe05000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus";
reg = <0 0xffe05000 0 0x1000>;
interrupts = <19 2>;
interrupt-parent = <&mpic>;
};
soc@ffe00000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "fsl,p2020-immr", "simple-bus";
ranges = <0x0 0x0 0xffe00000 0x100000>;
bus-frequency = <0>; // Filled out by uboot.
ecm-law@0 {
compatible = "fsl,ecm-law";
reg = <0x0 0x1000>;
fsl,num-laws = <12>;
};
ecm@1000 {
compatible = "fsl,p2020-ecm", "fsl,ecm";
reg = <0x1000 0x1000>;
interrupts = <17 2>;
interrupt-parent = <&mpic>;
};
memory-controller@2000 {
compatible = "fsl,p2020-memory-controller";
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
};
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
i2c@3100 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
reg = <0x3100 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <0>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <0>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
spi@7000 {
cell-index = <0>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,espi";
reg = <0x7000 0x1000>;
interrupts = <59 0x2>;
interrupt-parent = <&mpic>;
mode = "cpu";
};
dma@c300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,eloplus-dma";
reg = <0xc300 0x4>;
ranges = <0x0 0xc100 0x200>;
cell-index = <1>;
dma-channel@0 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupt-parent = <&mpic>;
interrupts = <76 2>;
};
dma-channel@80 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&mpic>;
interrupts = <77 2>;
};
dma-channel@100 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&mpic>;
interrupts = <78 2>;
};
dma-channel@180 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupt-parent = <&mpic>;
interrupts = <79 2>;
};
};
gpio: gpio-controller@f000 {
#gpio-cells = <2>;
compatible = "fsl,mpc8572-gpio";
reg = <0xf000 0x100>;
interrupts = <47 0x2>;
interrupt-parent = <&mpic>;
gpio-controller;
};
L2: l2-cache-controller@20000 {
compatible = "fsl,p2020-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
cache-size = <0x80000>; // L2,512K
interrupt-parent = <&mpic>;
interrupts = <16 2>;
};
dma@21300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,eloplus-dma";
reg = <0x21300 0x4>;
ranges = <0x0 0x21100 0x200>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupt-parent = <&mpic>;
interrupts = <20 2>;
};
dma-channel@80 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&mpic>;
interrupts = <21 2>;
};
dma-channel@100 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&mpic>;
interrupts = <22 2>;
};
dma-channel@180 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupt-parent = <&mpic>;
interrupts = <23 2>;
};
};
usb@22000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl-usb2-dr";
reg = <0x22000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <28 0x2>;
};
mdio@24520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <0x24520 0x20>;
};
mdio@25520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x26520 0x20>;
};
mdio@26520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x520 0x20>;
};
enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <0>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
ranges = <0x0 0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>;
};
enet1: ethernet@25000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <1>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x25000 0x1000>;
ranges = <0x0 0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <35 2 36 2 40 2>;
interrupt-parent = <&mpic>;
};
enet2: ethernet@26000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <2>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x26000 0x1000>;
ranges = <0x0 0x26000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <31 2 32 2 33 2>;
interrupt-parent = <&mpic>;
};
sdhci@2e000 {
compatible = "fsl,p2020-esdhc", "fsl,esdhc";
reg = <0x2e000 0x1000>;
interrupts = <72 0x2>;
interrupt-parent = <&mpic>;
/* Filled in by U-Boot */
clock-frequency = <0>;
};
crypto@30000 {
compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
"fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
reg = <0x30000 0x10000>;
interrupts = <45 2 58 2>;
interrupt-parent = <&mpic>;
fsl,num-channels = <4>;
fsl,channel-fifo-len = <24>;
fsl,exec-units-mask = <0xbfe>;
fsl,descriptor-types-mask = <0x3ab0ebf>;
};
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
};
msi@41600 {
compatible = "fsl,p2020-msi", "fsl,mpic-msi";
reg = <0x41600 0x80>;
msi-available-ranges = <0 0x100>;
interrupts = <
0xe0 0
0xe1 0
0xe2 0
0xe3 0
0xe4 0
0xe5 0
0xe6 0
0xe7 0>;
interrupt-parent = <&mpic>;
};
global-utilities@e0000 { //global utilities block
compatible = "fsl,p2020-guts";
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
};
pci0: pcie@ffe08000 {
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0 0xffe08000 0 0x1000>;
bus-range = <0 255>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <24 2>;
};
pci1: pcie@ffe09000 {
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0 0xffe09000 0 0x1000>;
bus-range = <0 255>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <25 2>;
};
pci2: pcie@ffe0a000 {
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0 0xffe0a000 0 0x1000>;
bus-range = <0 255>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <26 2>;
};
};
arch/powerpc/configs/83xx/mpc8313_rdb_defconfig
View file @ 3d07f0e8
......@@ -104,7 +104,6 @@ CONFIG_ROOT_NFS=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DETECT_HUNG_TASK=y
# CONFIG_DEBUG_BUGVERBOSE is not set
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
CONFIG_CRYPTO_PCBC=m
......
arch/powerpc/configs/83xx/mpc8315_rdb_defconfig
View file @ 3d07f0e8
......@@ -101,7 +101,6 @@ CONFIG_ROOT_NFS=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DETECT_HUNG_TASK=y
# CONFIG_DEBUG_BUGVERBOSE is not set
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
CONFIG_CRYPTO_PCBC=m
......
arch/powerpc/configs/85xx/mpc8540_ads_defconfig
View file @ 3d07f0e8
......@@ -58,7 +58,6 @@ CONFIG_PARTITION_ADVANCED=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEBUG_MUTEXES=y
# CONFIG_DEBUG_BUGVERBOSE is not set
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
arch/powerpc/configs/85xx/mpc8560_ads_defconfig
View file @ 3d07f0e8
......@@ -59,7 +59,6 @@ CONFIG_PARTITION_ADVANCED=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEBUG_MUTEXES=y
# CONFIG_DEBUG_BUGVERBOSE is not set
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
arch/powerpc/configs/85xx/mpc85xx_cds_defconfig
View file @ 3d07f0e8
......@@ -63,7 +63,6 @@ CONFIG_PARTITION_ADVANCED=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEBUG_MUTEXES=y
# CONFIG_DEBUG_BUGVERBOSE is not set
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
arch/powerpc/configs/86xx/mpc8641_hpcn_defconfig
View file @ 3d07f0e8
......@@ -168,7 +168,6 @@ CONFIG_MAC_PARTITION=y
CONFIG_CRC_T10DIF=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DETECT_HUNG_TASK=y
# CONFIG_DEBUG_BUGVERBOSE is not set
CONFIG_DEBUG_INFO=y
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
......
arch/powerpc/configs/e55xx_smp_defconfig
View file @ 3d07f0e8
......@@ -6,10 +6,10 @@ CONFIG_NR_CPUS=2
CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_SPARSE_IRQ=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_BLK_DEV_INITRD=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_EXPERT=y
......@@ -25,8 +25,32 @@ CONFIG_P5020_DS=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_BINFMT_MISC=m
CONFIG_SPARSE_IRQ=y
# CONFIG_PCI is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_XFRM_USER=y
CONFIG_NET_KEY=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_ROUTE_MULTIPATH=y
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
CONFIG_NET_IPIP=y
CONFIG_IP_MROUTE=y
CONFIG_IP_PIMSM_V1=y
CONFIG_IP_PIMSM_V2=y
CONFIG_ARPD=y
CONFIG_INET_ESP=y
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
CONFIG_IPV6=y
CONFIG_IP_SCTP=m
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_PROC_DEVICETREE=y
CONFIG_BLK_DEV_LOOP=y
......@@ -34,6 +58,9 @@ CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=131072
CONFIG_MISC_DEVICES=y
CONFIG_EEPROM_LEGACY=y
CONFIG_NETDEVICES=y
CONFIG_DUMMY=y
CONFIG_NET_ETHERNET=y
CONFIG_INPUT_FF_MEMLESS=m
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_KEYBOARD is not set
......@@ -64,22 +91,14 @@ CONFIG_NLS=y
CONFIG_NLS_UTF8=m
CONFIG_CRC_T10DIF=y
CONFIG_CRC_ITU_T=m
CONFIG_LIBCRC32C=m
CONFIG_FRAME_WARN=1024
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DETECT_HUNG_TASK=y
# CONFIG_DEBUG_BUGVERBOSE is not set
CONFIG_DEBUG_INFO=y
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
CONFIG_VIRQ_DEBUG=y
CONFIG_CRYPTO=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_PCBC=m
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_SHA1=m
CONFIG_CRYPTO_DES=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
CONFIG_CRYPTO_DEV_TALITOS=y
arch/powerpc/configs/mpc85xx_defconfig
View file @ 3d07f0e8
......@@ -204,7 +204,6 @@ CONFIG_CRC_T10DIF=y
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DETECT_HUNG_TASK=y
# CONFIG_DEBUG_BUGVERBOSE is not set
CONFIG_DEBUG_INFO=y
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
......
arch/powerpc/configs/mpc85xx_smp_defconfig
View file @ 3d07f0e8
......@@ -206,7 +206,6 @@ CONFIG_CRC_T10DIF=y
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DETECT_HUNG_TASK=y
# CONFIG_DEBUG_BUGVERBOSE is not set
CONFIG_DEBUG_INFO=y
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
......
arch/powerpc/configs/mpc86xx_defconfig
View file @ 3d07f0e8
......@@ -171,7 +171,6 @@ CONFIG_MAC_PARTITION=y
CONFIG_CRC_T10DIF=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DETECT_HUNG_TASK=y
# CONFIG_DEBUG_BUGVERBOSE is not set
CONFIG_DEBUG_INFO=y
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
......
arch/powerpc/include/asm/cputable.h
View file @ 3d07f0e8
......@@ -157,6 +157,7 @@ extern const char *powerpc_base_platform;
#define CPU_FTR_476_DD2 ASM_CONST(0x0000000000010000)
#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
#define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x0000000000080000)
#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000)
#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000)
......@@ -385,7 +386,8 @@ extern const char *powerpc_base_platform;
CPU_FTR_DBELL)
#define CPU_FTRS_E5500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD)
CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
CPU_FTR_DEBUG_LVL_EXC)
#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
/* 64-bit CPUs */
......
arch/powerpc/include/asm/mpic.h
View file @ 3d07f0e8
......@@ -263,6 +263,7 @@ struct mpic
#ifdef CONFIG_SMP
struct irq_chip hc_ipi;
#endif
struct irq_chip hc_tm;
const char *name;
/* Flags */
unsigned int flags;
......@@ -281,7 +282,7 @@ struct mpic
/* vector numbers used for internal sources (ipi/timers) */
unsigned int ipi_vecs[4];
unsigned int timer_vecs[4];
unsigned int timer_vecs[8];
/* Spurious vector to program into unused sources */
unsigned int spurious_vec;
......@@ -371,6 +372,8 @@ struct mpic
* NOTE: This flag trumps MPIC_WANTS_RESET.
*/
#define MPIC_NO_RESET 0x00004000
/* Freescale MPIC (compatible includes "fsl,mpic") */
#define MPIC_FSL 0x00008000
/* MPIC HW modification ID */
#define MPIC_REGSET_MASK 0xf0000000
......
arch/powerpc/include/asm/reg_booke.h
View file @ 3d07f0e8
......@@ -83,6 +83,10 @@
#define SPRN_IVOR13 0x19D /* Interrupt Vector Offset Register 13 */
#define SPRN_IVOR14 0x19E /* Interrupt Vector Offset Register 14 */
#define SPRN_IVOR15 0x19F /* Interrupt Vector Offset Register 15 */
#define SPRN_IVOR38 0x1B0 /* Interrupt Vector Offset Register 38 */
#define SPRN_IVOR39 0x1B1 /* Interrupt Vector Offset Register 39 */
#define SPRN_IVOR40 0x1B2 /* Interrupt Vector Offset Register 40 */
#define SPRN_IVOR41 0x1B3 /* Interrupt Vector Offset Register 41 */
#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */
#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */
#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */
......
arch/powerpc/kernel/cpu_setup_fsl_booke.S
View file @ 3d07f0e8
......@@ -88,6 +88,9 @@ _GLOBAL(__setup_cpu_e5500)
bl __e500_dcache_setup
#ifdef CONFIG_PPC_BOOK3E_64
bl .__setup_base_ivors
bl .setup_perfmon_ivor
bl .setup_doorbell_ivors
bl .setup_ehv_ivors
#else
bl __setup_e500mc_ivors
#endif
......
arch/powerpc/kernel/exceptions-64e.S
View file @ 3d07f0e8
......@@ -253,9 +253,6 @@ exception_marker:
.balign 0x1000
.globl interrupt_base_book3e
interrupt_base_book3e: /* fake trap */
/* Note: If real debug exceptions are supported by the HW, the vector
* below will have to be patched up to point to an appropriate handler
*/
EXCEPTION_STUB(0x000, machine_check) /* 0x0200 */
EXCEPTION_STUB(0x020, critical_input) /* 0x0580 */
EXCEPTION_STUB(0x040, debug_crit) /* 0x0d00 */
......@@ -272,8 +269,13 @@ interrupt_base_book3e: /* fake trap */
EXCEPTION_STUB(0x1a0, watchdog) /* 0x09f0 */
EXCEPTION_STUB(0x1c0, data_tlb_miss)
EXCEPTION_STUB(0x1e0, instruction_tlb_miss)
EXCEPTION_STUB(0x260, perfmon)
EXCEPTION_STUB(0x280, doorbell)
EXCEPTION_STUB(0x2a0, doorbell_crit)
EXCEPTION_STUB(0x2c0, guest_doorbell)
EXCEPTION_STUB(0x2e0, guest_doorbell_crit)
EXCEPTION_STUB(0x300, hypercall)
EXCEPTION_STUB(0x320, ehpriv)
.globl interrupt_end_book3e
interrupt_end_book3e:
......@@ -455,6 +457,70 @@ interrupt_end_book3e:
kernel_dbg_exc:
b . /* NYI */
/* Debug exception as a debug interrupt*/
START_EXCEPTION(debug_debug);
DBG_EXCEPTION_PROLOG(0xd00, PROLOG_ADDITION_2REGS)
/*
* If there is a single step or branch-taken exception in an
* exception entry sequence, it was probably meant to apply to
* the code where the exception occurred (since exception entry
* doesn't turn off DE automatically). We simulate the effect
* of turning off DE on entry to an exception handler by turning
* off DE in the DSRR1 value and clearing the debug status.
*/
mfspr r14,SPRN_DBSR /* check single-step/branch taken */
andis. r15,r14,DBSR_IC@h
beq+ 1f
LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e)
LOAD_REG_IMMEDIATE(r15,interrupt_end_book3e)
cmpld cr0,r10,r14
cmpld cr1,r10,r15
blt+ cr0,1f
bge+ cr1,1f
/* here it looks like we got an inappropriate debug exception. */
lis r14,DBSR_IC@h /* clear the IC event */
rlwinm r11,r11,0,~MSR_DE /* clear DE in the DSRR1 value */
mtspr SPRN_DBSR,r14
mtspr SPRN_DSRR1,r11
lwz r10,PACA_EXDBG+EX_CR(r13) /* restore registers */
ld r1,PACA_EXDBG+EX_R1(r13)
ld r14,PACA_EXDBG+EX_R14(r13)
ld r15,PACA_EXDBG+EX_R15(r13)
mtcr r10
ld r10,PACA_EXDBG+EX_R10(r13) /* restore registers */
ld r11,PACA_EXDBG+EX_R11(r13)
mfspr r13,SPRN_SPRG_DBG_SCRATCH
rfdi
/* Normal debug exception */
/* XXX We only handle coming from userspace for now since we can't
* quite save properly an interrupted kernel state yet
*/
1: andi. r14,r11,MSR_PR; /* check for userspace again */
beq kernel_dbg_exc; /* if from kernel mode */
/* Now we mash up things to make it look like we are coming on a
* normal exception
*/
mfspr r15,SPRN_SPRG_DBG_SCRATCH
mtspr SPRN_SPRG_GEN_SCRATCH,r15
mfspr r14,SPRN_DBSR
EXCEPTION_COMMON(0xd00, PACA_EXDBG, INTS_DISABLE_ALL)
std r14,_DSISR(r1)
addi r3,r1,STACK_FRAME_OVERHEAD
mr r4,r14
ld r14,PACA_EXDBG+EX_R14(r13)
ld r15,PACA_EXDBG+EX_R15(r13)
bl .save_nvgprs
bl .DebugException
b .ret_from_except
MASKABLE_EXCEPTION(0x260, perfmon, .performance_monitor_exception, ACK_NONE)
/* Doorbell interrupt */
MASKABLE_EXCEPTION(0x2070, doorbell, .doorbell_exception, ACK_NONE)
......@@ -469,6 +535,11 @@ kernel_dbg_exc:
// b ret_from_crit_except
b .
MASKABLE_EXCEPTION(0x2c0, guest_doorbell, .unknown_exception, ACK_NONE)
MASKABLE_EXCEPTION(0x2e0, guest_doorbell_crit, .unknown_exception, ACK_NONE)
MASKABLE_EXCEPTION(0x310, hypercall, .unknown_exception, ACK_NONE)
MASKABLE_EXCEPTION(0x320, ehpriv, .unknown_exception, ACK_NONE)
/*
* An interrupt came in while soft-disabled; clear EE in SRR1,
......@@ -588,7 +659,12 @@ fast_exception_return:
BAD_STACK_TRAMPOLINE(0x000)
BAD_STACK_TRAMPOLINE(0x100)
BAD_STACK_TRAMPOLINE(0x200)
BAD_STACK_TRAMPOLINE(0x260)
BAD_STACK_TRAMPOLINE(0x2c0)
BAD_STACK_TRAMPOLINE(0x2e0)
BAD_STACK_TRAMPOLINE(0x300)
BAD_STACK_TRAMPOLINE(0x310)
BAD_STACK_TRAMPOLINE(0x320)
BAD_STACK_TRAMPOLINE(0x400)
BAD_STACK_TRAMPOLINE(0x500)
BAD_STACK_TRAMPOLINE(0x600)
......@@ -1124,3 +1200,33 @@ _GLOBAL(__setup_base_ivors)
sync
blr
_GLOBAL(setup_perfmon_ivor)
SET_IVOR(35, 0x260) /* Performance Monitor */
blr
_GLOBAL(setup_doorbell_ivors)
SET_IVOR(36, 0x280) /* Processor Doorbell */
SET_IVOR(37, 0x2a0) /* Processor Doorbell Crit */
/* Check MMUCFG[LPIDSIZE] to determine if we have category E.HV */
mfspr r10,SPRN_MMUCFG
rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
beqlr
SET_IVOR(38, 0x2c0) /* Guest Processor Doorbell */
SET_IVOR(39, 0x2e0) /* Guest Processor Doorbell Crit/MC */
blr
_GLOBAL(setup_ehv_ivors)
/*
* We may be running as a guest and lack E.HV even on a chip
* that normally has it.
*/
mfspr r10,SPRN_MMUCFG
rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
beqlr
SET_IVOR(40, 0x300) /* Embedded Hypervisor System Call */
SET_IVOR(41, 0x320) /* Embedded Hypervisor Privilege */
blr
arch/powerpc/kernel/setup_64.c
View file @ 3d07f0e8
......@@ -62,6 +62,7 @@
#include <asm/udbg.h>
#include <asm/kexec.h>
#include <asm/mmu_context.h>
#include <asm/code-patching.h>
#include "setup.h"
......@@ -477,6 +478,9 @@ static void __init irqstack_early_init(void)
#ifdef CONFIG_PPC_BOOK3E
static void __init exc_lvl_early_init(void)
{
extern unsigned int interrupt_base_book3e;
extern unsigned int exc_debug_debug_book3e;
unsigned int i;
for_each_possible_cpu(i) {
......@@ -487,6 +491,10 @@ static void __init exc_lvl_early_init(void)
mcheckirq_ctx[i] = (struct thread_info *)
__va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
}
if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC))
patch_branch(&interrupt_base_book3e + (0x040 / 4) + 1,
(unsigned long)&exc_debug_debug_book3e, 0);
}
#else
#define exc_lvl_early_init()
......
arch/powerpc/platforms/86xx/mpc8610_hpcd.c
View file @ 3d07f0e8
......@@ -66,7 +66,7 @@ static void __init mpc8610_suspend_init(void)
return;
}
ret = request_irq(irq, mpc8610_sw9_irq, 0, "sw9/wakeup", NULL);
ret = request_irq(irq, mpc8610_sw9_irq, 0, "sw9:wakeup", NULL);
if (ret) {
pr_err("%s: can't request pixis event IRQ: %d\n",
__func__, ret);
......@@ -105,45 +105,77 @@ machine_device_initcall(mpc86xx_hpcd, mpc8610_declare_of_platform_devices);
#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
static u32 get_busfreq(void)
{
struct device_node *node;
u32 fs_busfreq = 0;
node = of_find_node_by_type(NULL, "cpu");
if (node) {
unsigned int size;
const unsigned int *prop =
of_get_property(node, "bus-frequency", &size);
if (prop)
fs_busfreq = *prop;
of_node_put(node);
};
return fs_busfreq;
}
/*
* DIU Area Descriptor
*
* The MPC8610 reference manual shows the bits of the AD register in
* little-endian order, which causes the BLUE_C field to be split into two
* parts. To simplify the definition of the MAKE_AD() macro, we define the
* fields in big-endian order and byte-swap the result.
*
* So even though the registers don't look like they're in the
* same bit positions as they are on the P1022, the same value is written to
* the AD register on the MPC8610 and on the P1022.
*/
#define AD_BYTE_F 0x10000000
#define AD_ALPHA_C_MASK 0x0E000000
#define AD_ALPHA_C_SHIFT 25
#define AD_BLUE_C_MASK 0x01800000
#define AD_BLUE_C_SHIFT 23
#define AD_GREEN_C_MASK 0x00600000
#define AD_GREEN_C_SHIFT 21
#define AD_RED_C_MASK 0x00180000
#define AD_RED_C_SHIFT 19
#define AD_PALETTE 0x00040000
#define AD_PIXEL_S_MASK 0x00030000
#define AD_PIXEL_S_SHIFT 16
#define AD_COMP_3_MASK 0x0000F000
#define AD_COMP_3_SHIFT 12
#define AD_COMP_2_MASK 0x00000F00
#define AD_COMP_2_SHIFT 8
#define AD_COMP_1_MASK 0x000000F0
#define AD_COMP_1_SHIFT 4
#define AD_COMP_0_MASK 0x0000000F
#define AD_COMP_0_SHIFT 0
#define MAKE_AD(alpha, red, blue, green, size, c0, c1, c2, c3) \
cpu_to_le32(AD_BYTE_F | (alpha << AD_ALPHA_C_SHIFT) | \
(blue << AD_BLUE_C_SHIFT) | (green << AD_GREEN_C_SHIFT) | \
(red << AD_RED_C_SHIFT) | (c3 << AD_COMP_3_SHIFT) | \
(c2 << AD_COMP_2_SHIFT) | (c1 << AD_COMP_1_SHIFT) | \
(c0 << AD_COMP_0_SHIFT) | (size << AD_PIXEL_S_SHIFT))
unsigned int mpc8610hpcd_get_pixel_format(unsigned int bits_per_pixel,
int monitor_port)
{
static const unsigned long pixelformat[][3] = {
{0x88882317, 0x88083218, 0x65052119},
{0x88883316, 0x88082219, 0x65053118},
{
MAKE_AD(3, 0, 2, 1, 3, 8, 8, 8, 8),
MAKE_AD(4, 2, 0, 1, 2, 8, 8, 8, 0),
MAKE_AD(4, 0, 2, 1, 1, 5, 6, 5, 0)
},
{
MAKE_AD(3, 2, 0, 1, 3, 8, 8, 8, 8),
MAKE_AD(4, 0, 2, 1, 2, 8, 8, 8, 0),
MAKE_AD(4, 2, 0, 1, 1, 5, 6, 5, 0)
},
};
unsigned int pix_fmt, arch_monitor;
unsigned int arch_monitor;
/* The DVI port is mis-wired on revision 1 of this board. */
arch_monitor = ((*pixis_arch == 0x01) && (monitor_port == 0))? 0 : 1;
/* DVI port for board version 0x01 */
if (bits_per_pixel == 32)
pix_fmt = pixelformat[arch_monitor][0];
else if (bits_per_pixel == 24)
pix_fmt = pixelformat[arch_monitor][1];
else if (bits_per_pixel == 16)
pix_fmt = pixelformat[arch_monitor][2];
else
pix_fmt = pixelformat[1][0];
return pix_fmt;
switch (bits_per_pixel) {
case 32:
return pixelformat[arch_monitor][0];
case 24:
return pixelformat[arch_monitor][1];
case 16:
return pixelformat[arch_monitor][2];
default:
pr_err("fsl-diu: unsupported pixel depth %u\n", bits_per_pixel);
return 0;
}
}
void mpc8610hpcd_set_gamma_table(int monitor_port, char *gamma_table_base)
......@@ -190,8 +222,7 @@ void mpc8610hpcd_set_pixel_clock(unsigned int pixclock)
}
/* Pixel Clock configuration */
pr_debug("DIU: Bus Frequency = %d\n", get_busfreq());
speed_ccb = get_busfreq();
speed_ccb = fsl_get_sys_freq();
/* Calculate the pixel clock with the smallest error */
/* calculate the following in steps to avoid overflow */
......
arch/powerpc/sysdev/mpic.c
View file @ 3d07f0e8
......@@ -6,6 +6,7 @@
* with various broken implementations of this HW.
*
* Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
* Copyright 2010-2011 Freescale Semiconductor, Inc.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
......@@ -218,6 +219,28 @@ static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 valu
_mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
}
static inline u32 _mpic_tm_read(struct mpic *mpic, unsigned int tm)
{
unsigned int offset = MPIC_INFO(TIMER_VECTOR_PRI) +
((tm & 3) * MPIC_INFO(TIMER_STRIDE));
if (tm >= 4)
offset += 0x1000 / 4;
return _mpic_read(mpic->reg_type, &mpic->tmregs, offset);
}
static inline void _mpic_tm_write(struct mpic *mpic, unsigned int tm, u32 value)
{
unsigned int offset = MPIC_INFO(TIMER_VECTOR_PRI) +
((tm & 3) * MPIC_INFO(TIMER_STRIDE));
if (tm >= 4)
offset += 0x1000 / 4;
_mpic_write(mpic->reg_type, &mpic->tmregs, offset, value);
}
static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
{
unsigned int cpu = mpic_processor_id(mpic);
......@@ -268,6 +291,8 @@ static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
#define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v))
#define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
#define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
#define mpic_tm_read(i) _mpic_tm_read(mpic,(i))
#define mpic_tm_write(i,v) _mpic_tm_write(mpic,(i),(v))
#define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
#define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))
#define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))
......@@ -624,6 +649,13 @@ static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq)
return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
}
/* Determine if the linux irq is a timer */
static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int irq)
{
unsigned int src = virq_to_hw(irq);
return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[7]);
}
/* Convert a cpu mask from logical to physical cpu numbers. */
static inline u32 mpic_physmask(u32 cpumask)
......@@ -810,6 +842,25 @@ static void mpic_end_ipi(struct irq_data *d)
#endif /* CONFIG_SMP */
static void mpic_unmask_tm(struct irq_data *d)
{
struct mpic *mpic = mpic_from_irq_data(d);
unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
DBG("%s: enable_tm: %d (tm %d)\n", mpic->name, irq, src);
mpic_tm_write(src, mpic_tm_read(src) & ~MPIC_VECPRI_MASK);
mpic_tm_read(src);
}
static void mpic_mask_tm(struct irq_data *d)
{
struct mpic *mpic = mpic_from_irq_data(d);
unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
mpic_tm_write(src, mpic_tm_read(src) | MPIC_VECPRI_MASK);
mpic_tm_read(src);
}
int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
bool force)
{
......@@ -936,6 +987,12 @@ static struct irq_chip mpic_ipi_chip = {
};
#endif /* CONFIG_SMP */
static struct irq_chip mpic_tm_chip = {
.irq_mask = mpic_mask_tm,
.irq_unmask = mpic_unmask_tm,
.irq_eoi = mpic_end_irq,
};
#ifdef CONFIG_MPIC_U3_HT_IRQS
static struct irq_chip mpic_irq_ht_chip = {
.irq_startup = mpic_startup_ht_irq,
......@@ -979,6 +1036,16 @@ static int mpic_host_map(struct irq_host *h, unsigned int virq,
}
#endif /* CONFIG_SMP */
if (hw >= mpic->timer_vecs[0] && hw <= mpic->timer_vecs[7]) {
WARN_ON(!(mpic->flags & MPIC_PRIMARY));
DBG("mpic: mapping as timer\n");
irq_set_chip_data(virq, mpic);
irq_set_chip_and_handler(virq, &mpic->hc_tm,
handle_fasteoi_irq);
return 0;
}
if (hw >= mpic->irq_count)
return -EINVAL;
......@@ -1019,6 +1086,7 @@ static int mpic_host_xlate(struct irq_host *h, struct device_node *ct,
irq_hw_number_t *out_hwirq, unsigned int *out_flags)
{
struct mpic *mpic = h->host_data;
static unsigned char map_mpic_senses[4] = {
IRQ_TYPE_EDGE_RISING,
IRQ_TYPE_LEVEL_LOW,
......@@ -1027,7 +1095,38 @@ static int mpic_host_xlate(struct irq_host *h, struct device_node *ct,
};
*out_hwirq = intspec[0];
if (intsize > 1) {
if (intsize >= 4 && (mpic->flags & MPIC_FSL)) {
/*
* Freescale MPIC with extended intspec:
* First two cells are as usual. Third specifies
* an "interrupt type". Fourth is type-specific data.
*
* See Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
*/
switch (intspec[2]) {
case 0:
case 1: /* no EISR/EIMR support for now, treat as shared IRQ */
break;
case 2:
if (intspec[0] >= ARRAY_SIZE(mpic->ipi_vecs))
return -EINVAL;
*out_hwirq = mpic->ipi_vecs[intspec[0]];
break;
case 3:
if (intspec[0] >= ARRAY_SIZE(mpic->timer_vecs))
return -EINVAL;
*out_hwirq = mpic->timer_vecs[intspec[0]];
break;
default:
pr_debug("%s: unknown irq type %u\n",
__func__, intspec[2]);
return -EINVAL;
}
*out_flags = map_mpic_senses[intspec[1] & 3];
} else if (intsize > 1) {
u32 mask = 0x3;
/* Apple invented a new race of encoding on machines with
......@@ -1103,6 +1202,9 @@ struct mpic * __init mpic_alloc(struct device_node *node,
mpic->hc_ipi.name = name;
#endif /* CONFIG_SMP */
mpic->hc_tm = mpic_tm_chip;
mpic->hc_tm.name = name;
mpic->flags = flags;
mpic->isu_size = isu_size;
mpic->irq_count = irq_count;
......@@ -1113,10 +1215,14 @@ struct mpic * __init mpic_alloc(struct device_node *node,
else
intvec_top = 255;
mpic->timer_vecs[0] = intvec_top - 8;
mpic->timer_vecs[1] = intvec_top - 7;
mpic->timer_vecs[2] = intvec_top - 6;
mpic->timer_vecs[3] = intvec_top - 5;
mpic->timer_vecs[0] = intvec_top - 12;
mpic->timer_vecs[1] = intvec_top - 11;
mpic->timer_vecs[2] = intvec_top - 10;
mpic->timer_vecs[3] = intvec_top - 9;
mpic->timer_vecs[4] = intvec_top - 8;
mpic->timer_vecs[5] = intvec_top - 7;
mpic->timer_vecs[6] = intvec_top - 6;
mpic->timer_vecs[7] = intvec_top - 5;
mpic->ipi_vecs[0] = intvec_top - 4;
mpic->ipi_vecs[1] = intvec_top - 3;
mpic->ipi_vecs[2] = intvec_top - 2;
......@@ -1126,6 +1232,8 @@ struct mpic * __init mpic_alloc(struct device_node *node,
/* Check for "big-endian" in device-tree */
if (node && of_get_property(node, "big-endian", NULL) != NULL)
mpic->flags |= MPIC_BIG_ENDIAN;
if (node && of_device_is_compatible(node, "fsl,mpic"))
mpic->flags |= MPIC_FSL;
/* Look for protected sources */
if (node) {
......@@ -1317,15 +1425,17 @@ void __init mpic_init(struct mpic *mpic)
/* Set current processor priority to max */
mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
/* Initialize timers: just disable them all */
/* Initialize timers to our reserved vectors and mask them for now */
for (i = 0; i < 4; i++) {
mpic_write(mpic->tmregs,
i * MPIC_INFO(TIMER_STRIDE) +
MPIC_INFO(TIMER_DESTINATION), 0);
MPIC_INFO(TIMER_DESTINATION),
1 << hard_smp_processor_id());
mpic_write(mpic->tmregs,
i * MPIC_INFO(TIMER_STRIDE) +
MPIC_INFO(TIMER_VECTOR_PRI),
MPIC_VECPRI_MASK |
(9 << MPIC_VECPRI_PRIORITY_SHIFT) |
(mpic->timer_vecs[0] + i));
}
......@@ -1434,6 +1544,11 @@ void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
~MPIC_VECPRI_PRIORITY_MASK;
mpic_ipi_write(src - mpic->ipi_vecs[0],
reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
} else if (mpic_is_tm(mpic, irq)) {
reg = mpic_tm_read(src - mpic->timer_vecs[0]) &
~MPIC_VECPRI_PRIORITY_MASK;
mpic_tm_write(src - mpic->timer_vecs[0],
reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
} else {
reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
& ~MPIC_VECPRI_PRIORITY_MASK;
......
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