drm/radeon: enable mgcg on CIK

Now that the CP is no longer reset and cg is properly
disabled in when appropriate in the dpm code we can
now enable mgcg (medium grained clockgating).
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/radeon/radeon_asic.c

@@ -2439,7 +2439,7 @@ int radeon_asic_init(struct radeon_device *rdev)
 		rdev->num_crtc = 6;
 		rdev->has_uvd = true;
 		rdev->cg_flags =
-			/*RADEON_CG_SUPPORT_GFX_MGCG |*/
+			RADEON_CG_SUPPORT_GFX_MGCG |
 			RADEON_CG_SUPPORT_GFX_MGLS |
 			/*RADEON_CG_SUPPORT_GFX_CGCG |*/
 			RADEON_CG_SUPPORT_GFX_CGLS |
@@ -2464,7 +2464,7 @@ int radeon_asic_init(struct radeon_device *rdev)
 		if (rdev->family == CHIP_KAVERI) {
 			rdev->num_crtc = 4;
 			rdev->cg_flags =
-				/*RADEON_CG_SUPPORT_GFX_MGCG |*/
+				RADEON_CG_SUPPORT_GFX_MGCG |
 				RADEON_CG_SUPPORT_GFX_MGLS |
 				/*RADEON_CG_SUPPORT_GFX_CGCG |*/
 				RADEON_CG_SUPPORT_GFX_CGLS |
@@ -2492,7 +2492,7 @@ int radeon_asic_init(struct radeon_device *rdev)
 		} else {
 			rdev->num_crtc = 2;
 			rdev->cg_flags =
-				/*RADEON_CG_SUPPORT_GFX_MGCG |*/
+				RADEON_CG_SUPPORT_GFX_MGCG |
 				RADEON_CG_SUPPORT_GFX_MGLS |
 				/*RADEON_CG_SUPPORT_GFX_CGCG |*/
 				RADEON_CG_SUPPORT_GFX_CGLS |