[ARM] 5532/1: Freescale STMP: register definitions [3/3]

Replace HW_zzz register access macros by regular __raw_readl/__raw_writel calls
Signed-off-by: dmitry pervushin <dpervushin@embeddedalley.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

arch/arm/mach-stmp378x/stmp378x.c

@@ -47,25 +47,28 @@
 static void stmp378x_ack_irq(unsigned int irq)
 {
 	/* Tell ICOLL to release IRQ line */
-	HW_ICOLL_VECTOR_WR(0x0);
+	__raw_writel(0, REGS_ICOLL_BASE + HW_ICOLL_VECTOR);
 
 	/* ACK current interrupt */
-	HW_ICOLL_LEVELACK_WR(BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0);
+	__raw_writel(0x01 /* BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 */,
+			REGS_ICOLL_BASE + HW_ICOLL_LEVELACK);
 
 	/* Barrier */
-	(void) HW_ICOLL_STAT_RD();
+	(void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT);
 }
 
 static void stmp378x_mask_irq(unsigned int irq)
 {
 	/* IRQ disable */
-	HW_ICOLL_INTERRUPTn_CLR(irq, BM_ICOLL_INTERRUPTn_ENABLE);
+	stmp3xxx_clearl(BM_ICOLL_INTERRUPTn_ENABLE,
+			REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn + irq * 0x10);
 }
 
 static void stmp378x_unmask_irq(unsigned int irq)
 {
 	/* IRQ enable */
-	HW_ICOLL_INTERRUPTn_SET(irq, BM_ICOLL_INTERRUPTn_ENABLE);
+	stmp3xxx_setl(BM_ICOLL_INTERRUPTn_ENABLE,
+		      REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn + irq * 0x10);
 }
 
 static struct irq_chip stmp378x_chip = {
@@ -84,52 +87,63 @@ void __init stmp378x_init_irq(void)
  */
 void stmp3xxx_arch_dma_enable_interrupt(int channel)
 {
-	int dmabus = channel / 16;
+	void __iomem *c1, *c2;
 
-	switch (dmabus) {
+	switch (STMP3XXX_DMA_BUS(channel)) {
 	case STMP3XXX_BUS_APBH:
-		HW_APBH_CTRL1_SET(1 << (16 + (channel % 16)));
-		HW_APBH_CTRL2_SET(1 << (16 + (channel % 16)));
+		c1 = REGS_APBH_BASE + HW_APBH_CTRL1;
+		c2 = REGS_APBH_BASE + HW_APBH_CTRL2;
 		break;
 
 	case STMP3XXX_BUS_APBX:
-		HW_APBX_CTRL1_SET(1 << (16 + (channel % 16)));
-		HW_APBX_CTRL2_SET(1 << (16 + (channel % 16)));
+		c1 = REGS_APBX_BASE + HW_APBX_CTRL1;
+		c2 = REGS_APBX_BASE + HW_APBX_CTRL2;
 		break;
+
+	default:
+		return;
 	}
+	stmp3xxx_setl(1 << (16 + STMP3XXX_DMA_CHANNEL(channel)), c1);
+	stmp3xxx_setl(1 << (16 + STMP3XXX_DMA_CHANNEL(channel)), c2);
 }
 EXPORT_SYMBOL(stmp3xxx_arch_dma_enable_interrupt);
 
 void stmp3xxx_arch_dma_clear_interrupt(int channel)
 {
-	int dmabus = channel / 16;
+	void __iomem *c1, *c2;
 
-	switch (dmabus) {
+	switch (STMP3XXX_DMA_BUS(channel)) {
 	case STMP3XXX_BUS_APBH:
-		HW_APBH_CTRL1_CLR(1 << (channel % 16));
-		HW_APBH_CTRL2_CLR(1 << (channel % 16));
+		c1 = REGS_APBH_BASE + HW_APBH_CTRL1;
+		c2 = REGS_APBH_BASE + HW_APBH_CTRL2;
 		break;
 
 	case STMP3XXX_BUS_APBX:
-		HW_APBX_CTRL1_CLR(1 << (channel % 16));
-		HW_APBX_CTRL2_CLR(1 << (channel % 16));
+		c1 = REGS_APBX_BASE + HW_APBX_CTRL1;
+		c2 = REGS_APBX_BASE + HW_APBX_CTRL2;
 		break;
+
+	default:
+		return;
 	}
+	stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel), c1);
+	stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel), c2);
 }
 EXPORT_SYMBOL(stmp3xxx_arch_dma_clear_interrupt);
 
 int stmp3xxx_arch_dma_is_interrupt(int channel)
 {
-	int dmabus = channel / 16;
 	int r = 0;
 
-	switch (dmabus) {
+	switch (STMP3XXX_DMA_BUS(channel)) {
 	case STMP3XXX_BUS_APBH:
-		r = HW_APBH_CTRL1_RD() & (1 << (channel % 16));
+		r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) &
+			(1 << STMP3XXX_DMA_CHANNEL(channel));
 		break;
 
 	case STMP3XXX_BUS_APBX:
-		r = HW_APBX_CTRL1_RD() & (1 << (channel % 16));
+		r = __raw_readl(REGS_APBX_BASE + HW_APBX_CTRL1) &
+			(1 << STMP3XXX_DMA_CHANNEL(channel));
 		break;
 	}
 	return r;
@@ -138,42 +152,41 @@ EXPORT_SYMBOL(stmp3xxx_arch_dma_is_interrupt);
 
 void stmp3xxx_arch_dma_reset_channel(int channel)
 {
-	int dmabus = channel / 16;
-	unsigned chbit = 1 << (channel % 16);
+	unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
+	void __iomem *c0;
+	u32 mask;
 
-	switch (dmabus) {
+	switch (STMP3XXX_DMA_BUS(channel)) {
 	case STMP3XXX_BUS_APBH:
-		/* Reset channel and wait for it to complete */
-		HW_APBH_CTRL0_SET(chbit <<
-				 BP_APBH_CTRL0_RESET_CHANNEL);
-		while (HW_APBH_CTRL0_RD() &
-		       (chbit << BP_APBH_CTRL0_RESET_CHANNEL))
-			continue;
+		c0 = REGS_APBH_BASE + HW_APBH_CTRL0;
+		mask = chbit << BP_APBH_CTRL0_RESET_CHANNEL;
 		break;
-
 	case STMP3XXX_BUS_APBX:
-		/* Reset channel and wait for it to complete */
-		HW_APBX_CHANNEL_CTRL_SET(
-			BF_APBX_CHANNEL_CTRL_RESET_CHANNEL(chbit));
-		while (HW_APBX_CHANNEL_CTRL_RD() &
-			BF_APBX_CHANNEL_CTRL_RESET_CHANNEL(chbit))
-			continue;
+		c0 = REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL;
+		mask = chbit << BP_APBX_CHANNEL_CTRL_RESET_CHANNEL;
 		break;
+	default:
+		return;
 	}
+
+	/* Reset channel and wait for it to complete */
+	stmp3xxx_setl(mask, c0);
+	while (__raw_readl(c0) & mask)
+		cpu_relax();
 }
 EXPORT_SYMBOL(stmp3xxx_arch_dma_reset_channel);
 
 void stmp3xxx_arch_dma_freeze(int channel)
 {
-	int dmabus = channel / 16;
-	unsigned chbit = 1 << (channel % 16);
+	unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
+	u32 mask = 1 << chbit;
 
-	switch (dmabus) {
+	switch (STMP3XXX_DMA_BUS(channel)) {
 	case STMP3XXX_BUS_APBH:
-		HW_APBH_CTRL0_SET(1<<chbit);
+		stmp3xxx_setl(mask, REGS_APBH_BASE + HW_APBH_CTRL0);
 		break;
 	case STMP3XXX_BUS_APBX:
-		HW_APBX_CHANNEL_CTRL_SET(1<<chbit);
+		stmp3xxx_setl(mask, REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL);
 		break;
 	}
 }
@@ -181,15 +194,15 @@ EXPORT_SYMBOL(stmp3xxx_arch_dma_freeze);
 
 void stmp3xxx_arch_dma_unfreeze(int channel)
 {
-	int dmabus = channel / 16;
-	unsigned chbit = 1 << (channel % 16);
+	unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
+	u32 mask = 1 << chbit;
 
-	switch (dmabus) {
+	switch (STMP3XXX_DMA_BUS(channel)) {
 	case STMP3XXX_BUS_APBH:
-		HW_APBH_CTRL0_CLR(1<<chbit);
+		stmp3xxx_clearl(mask, REGS_APBH_BASE + HW_APBH_CTRL0);
 		break;
 	case STMP3XXX_BUS_APBX:
-		HW_APBX_CHANNEL_CTRL_CLR(1<<chbit);
+		stmp3xxx_clearl(mask, REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL);
 		break;
 	}
 }
@@ -201,7 +214,7 @@ EXPORT_SYMBOL(stmp3xxx_arch_dma_unfreeze);
  *
  * Logical      Physical
  * f0000000	80000000	On-chip registers
- * f1000000	00000000	256k on-chip SRAM
+ * f1000000	00000000	32k on-chip SRAM
  */
 
 static struct map_desc stmp378x_io_desc[] __initdata = {

arch/arm/mach-stmp37xx/stmp37xx.c

@@ -34,6 +34,7 @@
 #include <mach/stmp3xxx.h>
 #include <mach/dma.h>
 
+#include <mach/platform.h>
 #include <mach/regs-icoll.h>
 #include <mach/regs-apbh.h>
 #include <mach/regs-apbx.h>
@@ -45,25 +46,28 @@
 static void stmp37xx_ack_irq(unsigned int irq)
 {
 	/* Disable IRQ */
-	HW_ICOLL_PRIORITYn_CLR(irq / 4, 0x04 << ((irq % 4) * 8));
+	stmp3xxx_clearl(0x04 << ((irq % 4) * 8),
+		REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + irq / 4 * 0x10);
 
 	/* ACK current interrupt */
-	HW_ICOLL_LEVELACK_WR(1);
+	__raw_writel(1, REGS_ICOLL_BASE + HW_ICOLL_LEVELACK);
 
 	/* Barrier */
-	(void) HW_ICOLL_STAT_RD();
+	(void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT);
 }
 
 static void stmp37xx_mask_irq(unsigned int irq)
 {
 	/* IRQ disable */
-	HW_ICOLL_PRIORITYn_CLR(irq / 4, 0x04 << ((irq % 4) * 8));
+	stmp3xxx_clearl(0x04 << ((irq % 4) * 8),
+		REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + irq / 4 * 0x10);
 }
 
 static void stmp37xx_unmask_irq(unsigned int irq)
 {
 	/* IRQ enable */
-	HW_ICOLL_PRIORITYn_SET(irq / 4, 0x04 << ((irq % 4) * 8));
+	stmp3xxx_setl(0x04 << ((irq % 4) * 8),
+		REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + irq / 4 * 0x10);
 }
 
 static struct irq_chip stmp37xx_chip = {
@@ -82,15 +86,15 @@ void __init stmp37xx_init_irq(void)
  */
 void stmp3xxx_arch_dma_enable_interrupt(int channel)
 {
-	int dmabus = channel / 16;
-
-	switch (dmabus) {
+	switch (STMP3XXX_DMA_BUS(channel)) {
 	case STMP3XXX_BUS_APBH:
-		HW_APBH_CTRL1_SET(1 << (8 + (channel % 16)));
+		stmp3xxx_setl(1 << (8 + STMP3XXX_DMA_CHANNEL(channel)),
+			REGS_APBH_BASE + HW_APBH_CTRL1);
 		break;
 
 	case STMP3XXX_BUS_APBX:
-		HW_APBX_CTRL1_SET(1 << (8 + (channel % 16)));
+		stmp3xxx_setl(1 << (8 + STMP3XXX_DMA_CHANNEL(channel)),
+			REGS_APBX_BASE + HW_APBX_CTRL1);
 		break;
 	}
 }
@@ -98,15 +102,15 @@ EXPORT_SYMBOL(stmp3xxx_arch_dma_enable_interrupt);
 
 void stmp3xxx_arch_dma_clear_interrupt(int channel)
 {
-	int dmabus = channel / 16;
-
-	switch (dmabus) {
+	switch (STMP3XXX_DMA_BUS(channel)) {
 	case STMP3XXX_BUS_APBH:
-		HW_APBH_CTRL1_CLR(1 << (channel % 16));
+		stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel),
+				REGS_APBH_BASE + HW_APBH_CTRL1);
 		break;
 
 	case STMP3XXX_BUS_APBX:
-		HW_APBX_CTRL1_CLR(1 << (channel % 16));
+		stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel),
+				REGS_APBX_BASE + HW_APBX_CTRL1);
 		break;
 	}
 }
@@ -116,15 +120,15 @@ int stmp3xxx_arch_dma_is_interrupt(int channel)
 {
 	int r = 0;
 
-	int dmabus = channel / 16;
-
-	switch (dmabus) {
+	switch (STMP3XXX_DMA_BUS(channel)) {
 	case STMP3XXX_BUS_APBH:
-		r = HW_APBH_CTRL1_RD() & (1 << (channel % 16));
+		r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) &
+			(1 << STMP3XXX_DMA_CHANNEL(channel));
 		break;
 
 	case STMP3XXX_BUS_APBX:
-		r = HW_APBX_CTRL1_RD() & (1 << (channel % 16));
+		r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) &
+			(1 << STMP3XXX_DMA_CHANNEL(channel));
 		break;
 	}
 	return r;
@@ -133,24 +137,24 @@ EXPORT_SYMBOL(stmp3xxx_arch_dma_is_interrupt);
 
 void stmp3xxx_arch_dma_reset_channel(int channel)
 {
-	int dmabus = channel / 16;
-	unsigned chbit = 1 << (channel % 16);
+	unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
 
-	switch (dmabus) {
+	switch (STMP3XXX_DMA_BUS(channel)) {
 	case STMP3XXX_BUS_APBH:
 		/* Reset channel and wait for it to complete */
-		HW_APBH_CTRL0_SET(chbit << BP_APBH_CTRL0_RESET_CHANNEL);
-		while (HW_APBH_CTRL0_RD() &
+		stmp3xxx_setl(chbit << BP_APBH_CTRL0_RESET_CHANNEL,
+			REGS_APBH_BASE + HW_APBH_CTRL0);
+		while (__raw_readl(REGS_APBH_BASE + HW_APBH_CTRL0) &
 		       (chbit << BP_APBH_CTRL0_RESET_CHANNEL))
-			continue;
+				cpu_relax();
 		break;
 
 	case STMP3XXX_BUS_APBX:
-		/* Reset channel and wait for it to complete */
-		HW_APBX_CTRL0_SET(chbit << BP_APBX_CTRL0_RESET_CHANNEL);
-		while (HW_APBX_CTRL0_RD() &
+		stmp3xxx_setl(chbit << BP_APBX_CTRL0_RESET_CHANNEL,
+			REGS_APBX_BASE + HW_APBX_CTRL0);
+		while (__raw_readl(REGS_APBX_BASE + HW_APBX_CTRL0) &
 		       (chbit << BP_APBX_CTRL0_RESET_CHANNEL))
-			continue;
+				cpu_relax();
 		break;
 	}
 }
@@ -158,15 +162,14 @@ EXPORT_SYMBOL(stmp3xxx_arch_dma_reset_channel);
 
 void stmp3xxx_arch_dma_freeze(int channel)
 {
-	int dmabus = channel / 16;
-	unsigned chbit = 1 << (channel % 16);
+	unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
 
-	switch (dmabus) {
+	switch (STMP3XXX_DMA_BUS(channel)) {
 	case STMP3XXX_BUS_APBH:
-		HW_APBH_CTRL0_SET(1<<chbit);
+		stmp3xxx_setl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
 		break;
 	case STMP3XXX_BUS_APBX:
-		HW_APBX_CTRL0_SET(1<<chbit);
+		stmp3xxx_setl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
 		break;
 	}
 }
@@ -174,15 +177,14 @@ EXPORT_SYMBOL(stmp3xxx_arch_dma_freeze);
 
 void stmp3xxx_arch_dma_unfreeze(int channel)
 {
-	int dmabus = channel / 16;
-	unsigned chbit = 1 << (channel % 16);
+	unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
 
-	switch (dmabus) {
+	switch (STMP3XXX_DMA_BUS(channel)) {
 	case STMP3XXX_BUS_APBH:
-		HW_APBH_CTRL0_CLR(1<<chbit);
+		stmp3xxx_clearl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
 		break;
 	case STMP3XXX_BUS_APBX:
-		HW_APBX_CTRL0_CLR(1<<chbit);
+		stmp3xxx_clearl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
 		break;
 	}
 }
@@ -194,7 +196,7 @@ EXPORT_SYMBOL(stmp3xxx_arch_dma_unfreeze);
  *
  * Logical      Physical
  * f0000000	80000000	On-chip registers
- * f1000000	00000000	256k on-chip SRAM
+ * f1000000	00000000	32k on-chip SRAM
  */
 static struct map_desc stmp37xx_io_desc[] __initdata = {
 	{

arch/arm/plat-stmp3xxx/core.c

@@ -20,6 +20,7 @@
 #include <linux/io.h>
 
 #include <mach/stmp3xxx.h>
+#include <mach/platform.h>
 #include <mach/dma.h>
 #include <mach/regs-clkctrl.h>
 
@@ -121,7 +122,7 @@ struct platform_device stmp3xxx_dbguart = {
 void __init stmp3xxx_init(void)
 {
 	/* Turn off auto-slow and other tricks */
-	HW_CLKCTRL_HBUS_CLR(0x07f00000U);
+	stmp3xxx_clearl(0x7f00000, REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS);
 
 	stmp3xxx_dma_init();
 }

arch/arm/plat-stmp3xxx/dma.c

@@ -23,6 +23,7 @@
 
 #include <asm/page.h>
 
+#include <mach/platform.h>
 #include <mach/dma.h>
 #include <mach/regs-apbx.h>
 #include <mach/regs-apbh.h>
@@ -35,16 +36,6 @@ static struct stmp3xxx_dma_user {
 	const char *name;
 } channels[MAX_DMA_CHANNELS];
 
-static inline int dmach(int ch)
-{
-	return ch % 16;
-}
-
-static inline int dmabus(int ch)
-{
-	return ch / 16;
-}
-
 #define IS_VALID_CHANNEL(ch) ((ch) >= 0 && (ch) < MAX_DMA_CHANNELS)
 #define IS_USED(ch) (channels[ch].inuse)
 
@@ -101,17 +92,19 @@ int stmp3xxx_dma_read_semaphore(int channel)
 {
 	int sem = -1;
 
-	switch (dmabus(channel)) {
+	switch (STMP3XXX_DMA_BUS(channel)) {
 	case STMP3XXX_BUS_APBH:
-		sem =
-		    (HW_APBH_CHn_SEMA_RD(dmach(channel)) &
-		     BM_APBH_CHn_SEMA_PHORE) >> BP_APBH_CHn_SEMA_PHORE;
+		sem = __raw_readl(REGS_APBH_BASE + HW_APBH_CHn_SEMA +
+				STMP3XXX_DMA_CHANNEL(channel) * 0x70);
+		sem &= BM_APBH_CHn_SEMA_PHORE;
+		sem >>= BP_APBH_CHn_SEMA_PHORE;
 		break;
 
 	case STMP3XXX_BUS_APBX:
-		sem =
-		    (HW_APBX_CHn_SEMA_RD(dmach(channel)) &
-		     BM_APBX_CHn_SEMA_PHORE) >> BP_APBX_CHn_SEMA_PHORE;
+		sem = __raw_readl(REGS_APBX_BASE + HW_APBX_CHn_SEMA +
+				STMP3XXX_DMA_CHANNEL(channel) * 0x70);
+		sem &= BM_APBX_CHn_SEMA_PHORE;
+		sem >>= BP_APBX_CHn_SEMA_PHORE;
 		break;
 	default:
 		BUG();
@@ -189,39 +182,44 @@ EXPORT_SYMBOL(stmp3xxx_dma_free_command);
 void stmp3xxx_dma_go(int channel,
 		     struct stmp3xxx_dma_descriptor *head, u32 semaphore)
 {
-	int ch = dmach(channel);
+	int ch = STMP3XXX_DMA_CHANNEL(channel);
+	void __iomem *c, *s;
 
-	switch (dmabus(channel)) {
+	switch (STMP3XXX_DMA_BUS(channel)) {
 	case STMP3XXX_BUS_APBH:
-		/* Set next command */
-		HW_APBH_CHn_NXTCMDAR_WR(ch, head->handle);
-		/* Set counting semaphore (kicks off transfer). Assumes
-		   peripheral has been set up correctly */
-		HW_APBH_CHn_SEMA_WR(ch, semaphore);
+		c = REGS_APBH_BASE + HW_APBH_CHn_NXTCMDAR + 0x70 * ch;
+		s = REGS_APBH_BASE + HW_APBH_CHn_SEMA + 0x70 * ch;
 		break;
 
 	case STMP3XXX_BUS_APBX:
-		/* Set next command */
-		HW_APBX_CHn_NXTCMDAR_WR(ch, head->handle);
-		/* Set counting semaphore (kicks off transfer). Assumes
-		   peripheral has been set up correctly */
-		HW_APBX_CHn_SEMA_WR(ch, semaphore);
+		c = REGS_APBX_BASE + HW_APBX_CHn_NXTCMDAR + 0x70 * ch;
+		s = REGS_APBX_BASE + HW_APBX_CHn_SEMA + 0x70 * ch;
 		break;
+
+	default:
+		return;
 	}
+
+	/* Set next command */
+	__raw_writel(head->handle, c);
+	/* Set counting semaphore (kicks off transfer). Assumes
+	   peripheral has been set up correctly */
+	__raw_writel(semaphore, s);
 }
 EXPORT_SYMBOL(stmp3xxx_dma_go);
 
 int stmp3xxx_dma_running(int channel)
 {
-	switch (dmabus(channel)) {
+	switch (STMP3XXX_DMA_BUS(channel)) {
 	case STMP3XXX_BUS_APBH:
-		return HW_APBH_CHn_SEMA_RD(dmach(channel)) &
-		    BM_APBH_CHn_SEMA_PHORE;
+		return (__raw_readl(REGS_APBH_BASE + HW_APBH_CHn_SEMA +
+			0x70 * STMP3XXX_DMA_CHANNEL(channel))) &
+			    BM_APBH_CHn_SEMA_PHORE;
 
 	case STMP3XXX_BUS_APBX:
-		return HW_APBX_CHn_SEMA_RD(dmach(channel)) &
-		    BM_APBX_CHn_SEMA_PHORE;
-
+		return (__raw_readl(REGS_APBX_BASE + HW_APBX_CHn_SEMA +
+			0x70 * STMP3XXX_DMA_CHANNEL(channel))) &
+			    BM_APBX_CHn_SEMA_PHORE;
 	default:
 		BUG();
 		return 0;
@@ -238,7 +236,7 @@ void stmp3xxx_dma_free_chain(struct stmp37xx_circ_dma_chain *chain)
 
 	for (i = 0; i < chain->total_count; i++)
 		stmp3xxx_dma_free_command(
-			STMP3xxx_DMA(chain->channel, chain->bus),
+			STMP3XXX_DMA(chain->channel, chain->bus),
 			&chain->chain[i]);
 }
 EXPORT_SYMBOL(stmp3xxx_dma_free_chain);
@@ -291,16 +289,15 @@ int stmp3xxx_dma_make_chain(int ch, struct stmp37xx_circ_dma_chain *chain,
 	chain->free_count = items;
 	chain->active_count = 0;
 	chain->cooked_count = 0;
-	chain->bus = dmabus(ch);
-	chain->channel = dmach(ch);
+	chain->bus = STMP3XXX_DMA_BUS(ch);
+	chain->channel = STMP3XXX_DMA_CHANNEL(ch);
 	return err;
 }
 EXPORT_SYMBOL(stmp3xxx_dma_make_chain);
 
 void stmp37xx_circ_clear_chain(struct stmp37xx_circ_dma_chain *chain)
 {
-	BUG_ON(stmp3xxx_dma_running(STMP3xxx_DMA(chain->channel, chain->bus)) >
-	       0);
+	BUG_ON(stmp3xxx_dma_running(STMP3XXX_DMA(chain->channel, chain->bus)));
 	chain->free_index = 0;
 	chain->active_index = 0;
 	chain->cooked_index = 0;
@@ -325,6 +322,8 @@ EXPORT_SYMBOL(stmp37xx_circ_advance_free);
 void stmp37xx_circ_advance_active(struct stmp37xx_circ_dma_chain *chain,
 		unsigned count)
 {
+	void __iomem *c;
+	u32 mask_clr, mask;
 	BUG_ON(chain->free_count < count);
 
 	chain->free_count -= count;
@@ -334,26 +333,24 @@ void stmp37xx_circ_advance_active(struct stmp37xx_circ_dma_chain *chain,
 
 	switch (chain->bus) {
 	case STMP3XXX_BUS_APBH:
-		/* Set counting semaphore (kicks off transfer). Assumes
-		   peripheral has been set up correctly */
-		HW_APBH_CHn_SEMA_CLR(chain->channel,
-				     BM_APBH_CHn_SEMA_INCREMENT_SEMA);
-		HW_APBH_CHn_SEMA_SET(chain->channel,
-				     BF_APBH_CHn_SEMA_INCREMENT_SEMA(count));
+		c = REGS_APBH_BASE + HW_APBH_CHn_SEMA + 0x70 * chain->channel;
+		mask_clr = BM_APBH_CHn_SEMA_INCREMENT_SEMA;
+		mask = BF(count, APBH_CHn_SEMA_INCREMENT_SEMA);
 		break;
-
 	case STMP3XXX_BUS_APBX:
-		/* Set counting semaphore (kicks off transfer). Assumes
-		   peripheral has been set up correctly */
-		HW_APBX_CHn_SEMA_CLR(chain->channel,
-				     BM_APBX_CHn_SEMA_INCREMENT_SEMA);
-		HW_APBX_CHn_SEMA_SET(chain->channel,
-				     BF_APBX_CHn_SEMA_INCREMENT_SEMA(count));
+		c = REGS_APBX_BASE + HW_APBX_CHn_SEMA + 0x70 * chain->channel;
+		mask_clr = BM_APBX_CHn_SEMA_INCREMENT_SEMA;
+		mask = BF(count, APBX_CHn_SEMA_INCREMENT_SEMA);
 		break;
-
 	default:
 		BUG();
+		return;
 	}
+
+	/* Set counting semaphore (kicks off transfer). Assumes
+	   peripheral has been set up correctly */
+	stmp3xxx_clearl(mask_clr, c);
+	stmp3xxx_setl(mask, c);
 }
 EXPORT_SYMBOL(stmp37xx_circ_advance_active);
 
@@ -362,7 +359,7 @@ unsigned stmp37xx_circ_advance_cooked(struct stmp37xx_circ_dma_chain *chain)
 	unsigned cooked;
 
 	cooked = chain->active_count -
-	  stmp3xxx_dma_read_semaphore(STMP3xxx_DMA(chain->channel, chain->bus));
+	  stmp3xxx_dma_read_semaphore(STMP3XXX_DMA(chain->channel, chain->bus));
 
 	chain->active_count -= cooked;
 	chain->active_index += cooked;
@@ -383,38 +380,41 @@ void stmp3xxx_dma_set_alt_target(int channel, int function)
 #else
 #error wrong arch
 #endif
-	int shift = dmach(channel) * bits;
+	int shift = STMP3XXX_DMA_CHANNEL(channel) * bits;
 	unsigned mask = (1<<bits) - 1;
+	void __iomem *c;
 
 	BUG_ON(function < 0 || function >= (1<<bits));
 	pr_debug("%s: channel = %d, using mask %x, "
 		 "shift = %d\n", __func__, channel, mask, shift);
 
-	switch (dmabus(channel)) {
+	switch (STMP3XXX_DMA_BUS(channel)) {
 	case STMP3XXX_BUS_APBH:
-		HW_APBH_DEVSEL_CLR(mask<<shift);
-		HW_APBH_DEVSEL_SET(function<<shift);
+		c = REGS_APBH_BASE + HW_APBH_DEVSEL;
 		break;
 	case STMP3XXX_BUS_APBX:
-		HW_APBX_DEVSEL_CLR(mask<<shift);
-		HW_APBX_DEVSEL_SET(function<<shift);
+		c = REGS_APBX_BASE + HW_APBX_DEVSEL;
 		break;
 	default:
 		BUG();
 	}
+	stmp3xxx_clearl(mask << shift, c);
+	stmp3xxx_setl(mask << shift, c);
 }
 EXPORT_SYMBOL(stmp3xxx_dma_set_alt_target);
 
 void stmp3xxx_dma_suspend(void)
 {
-	HW_APBH_CTRL0_SET(BM_APBH_CTRL0_CLKGATE);
-	HW_APBX_CTRL0_SET(BM_APBX_CTRL0_CLKGATE);
+	stmp3xxx_setl(BM_APBH_CTRL0_CLKGATE, REGS_APBH_BASE + HW_APBH_CTRL0);
+	stmp3xxx_setl(BM_APBX_CTRL0_CLKGATE, REGS_APBX_BASE + HW_APBX_CTRL0);
 }
 
 void stmp3xxx_dma_resume(void)
 {
-	HW_APBH_CTRL0_CLR(BM_APBH_CTRL0_CLKGATE | BM_APBH_CTRL0_SFTRST);
-	HW_APBX_CTRL0_CLR(BM_APBX_CTRL0_CLKGATE | BM_APBX_CTRL0_SFTRST);
+	stmp3xxx_clearl(BM_APBH_CTRL0_CLKGATE | BM_APBH_CTRL0_SFTRST,
+			REGS_APBH_BASE + HW_APBH_CTRL0);
+	stmp3xxx_clearl(BM_APBX_CTRL0_CLKGATE | BM_APBX_CTRL0_SFTRST,
+			REGS_APBX_BASE + HW_APBX_CTRL0);
 }
 
 #ifdef CONFIG_CPU_FREQ
@@ -452,11 +452,12 @@ static struct dma_notifier_block dma_cpufreq_nb = {
 
 void __init stmp3xxx_dma_init(void)
 {
-	HW_APBH_CTRL0_CLR(BM_APBH_CTRL0_CLKGATE | BM_APBH_CTRL0_SFTRST);
-	HW_APBX_CTRL0_CLR(BM_APBX_CTRL0_CLKGATE | BM_APBX_CTRL0_SFTRST);
+	stmp3xxx_clearl(BM_APBH_CTRL0_CLKGATE | BM_APBH_CTRL0_SFTRST,
+			REGS_APBH_BASE + HW_APBH_CTRL0);
+	stmp3xxx_clearl(BM_APBX_CTRL0_CLKGATE | BM_APBX_CTRL0_SFTRST,
+			REGS_APBX_BASE + HW_APBX_CTRL0);
 #ifdef CONFIG_CPU_FREQ
 	cpufreq_register_notifier(&dma_cpufreq_nb.nb,
 				CPUFREQ_TRANSITION_NOTIFIER);
 #endif /* CONFIG_CPU_FREQ */
-
 }

arch/arm/plat-stmp3xxx/include/mach/dma.h

@@ -25,16 +25,14 @@
 #define MAX_PIO_WORDS   (15)
 #endif
 
-#define STMP3XXX_BUS_APBH	0
-#define STMP3XXX_BUS_APBX	1
+#define STMP3XXX_BUS_APBH		0
+#define STMP3XXX_BUS_APBX		1
 #define STMP3XXX_DMA_MAX_CHANNEL	16
-
-
-#define STMP3xxx_DMA(channel, bus)  ((bus) * 16 + (channel))
-
-#define MAX_DMA_ADDRESS		0xffffffff
-
-#define MAX_DMA_CHANNELS	32
+#define STMP3XXX_DMA_BUS(dma)		((dma) / 16)
+#define STMP3XXX_DMA_CHANNEL(dma)	((dma) % 16)
+#define STMP3XXX_DMA(channel, bus)	((bus) * 16 + (channel))
+#define MAX_DMA_ADDRESS			0xffffffff
+#define MAX_DMA_CHANNELS		32
 
 struct stmp3xxx_dma_command {
 	u32 next;

arch/arm/plat-stmp3xxx/include/mach/pinmux.h

@@ -146,10 +146,9 @@ struct stmp3xxx_pinmux_bank {
 	u8 strengths[HW_DRIVE_PINDRV_NUM];
 
 	/* GPIO things */
-	void __iomem *hw_gpio_read,
-	     *hw_gpio_set,
-	     *hw_gpio_clr,
-	     *hw_gpio_doe;
+	void __iomem *hw_gpio_in,
+		     *hw_gpio_out,
+		     *hw_gpio_doe;
 	int irq, virq;
 };
 

arch/arm/plat-stmp3xxx/include/mach/platform.h

@@ -14,6 +14,9 @@
 #ifndef __ASM_PLAT_PLATFORM_H
 #define __ASM_PLAT_PLATFORM_H
 
+#ifndef __ASSEMBLER__
+#include <linux/io.h>
+#endif
 #include <asm/sizes.h>
 
 /* Virtual address where registers are mapped */
@@ -44,4 +47,22 @@
 #define IRQ_PRIORITY_REG_WR	HW_ICOLL_INTERRUPTn_WR
 #endif
 
+#define HW_STMP3XXX_SET		0x04
+#define HW_STMP3XXX_CLR		0x08
+#define HW_STMP3XXX_TOG		0x0c
+
+#ifndef __ASSEMBLER__
+static inline void stmp3xxx_clearl(u32 v, void __iomem *r)
+{
+	__raw_writel(v, r + HW_STMP3XXX_CLR);
+}
+
+static inline void stmp3xxx_setl(u32 v, void __iomem *r)
+{
+	__raw_writel(v, r + HW_STMP3XXX_SET);
+}
+#endif
+
+#define BF(value, field) (((value) << BP_##field) & BM_##field)
+
 #endif /* __ASM_ARCH_PLATFORM_H */

arch/arm/plat-stmp3xxx/include/mach/stmp3xxx_regs.h

-/*
- * Freescale STMP37XX/STMP378X SoC register access interfaces
- *
- * The SoC registers may be accessed via:
- *
- * - single 32 bit address, or
- * - four 32 bit addresses - general purpose, set, clear and toggle bits
- *
- * Multiple IP blocks (e.g. SSP, UART) provide identical register sets per
- * each module
- *
- * Embedded Alley Solutions, Inc <source@embeddedalley.com>
- *
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef __ASM_PLAT_STMP3XXX_REGS_H
-#define __ASM_PLAT_STMP3XXX_REGS_H
-
-#ifndef __ASSEMBLER__
-#include <linux/io.h>
-#endif
-
-#include "platform.h"
-
-#define REGS_BASE STMP3XXX_REGS_BASE
-
-#define HW_STMP3xxx_SET		0x04
-#define HW_STMP3xxx_CLR		0x08
-#define HW_STMP3xxx_TOG		0x0c
-
-#ifndef __ASSEMBLER__
-#define HW_REGISTER_FUNCS(id, base, offset, regset, rd, wr)		\
-	static const u32 id##_OFFSET = offset;				\
-	static inline u32 id##_RD_NB(const void __iomem *regbase) {	\
-		if (!rd)						\
-			printk(KERN_ERR"%s: cannot READ at %p+%x\n",	\
-				#id, regbase, offset);			\
-		return __raw_readl(regbase + offset);			\
-	}								\
-	static inline void id##_WR_NB(void __iomem *regbase, u32 v) {	\
-		if (!wr)						\
-			printk(KERN_ERR"%s: cannot WRITE at %p+%x\n",	\
-				#id, regbase, offset);			\
-		__raw_writel(v, regbase + offset);			\
-	}								\
-	static inline void id##_SET_NB(void __iomem *regbase, u32 v) {	\
-		if (!wr)						\
-			printk(KERN_ERR"%s: cannot SET at %p+%x\n",	\
-				#id, regbase, offset);			\
-		if (regset)						\
-			__raw_writel(v, regbase + 			\
-					offset + HW_STMP3xxx_SET);	\
-		else							\
-			__raw_writel(v | __raw_readl(regbase + offset),	\
-				regbase + offset);			\
-	}								\
-	static inline void id##_CLR_NB(void __iomem *regbase, u32 v) {	\
-		if (!wr) 						\
-			printk(KERN_ERR"%s: cannot CLR at %p+%x\n",	\
-				#id, regbase, offset);			\
-		if (regset)						\
-			__raw_writel(v, regbase + 			\
-					offset + HW_STMP3xxx_CLR);	\
-		else							\
-			__raw_writel(					\
-				~v & __raw_readl(regbase + offset),	\
-				regbase + offset);			\
-	}								\
-	static inline void id##_TOG_NB(void __iomem *regbase, u32 v) {	\
-		if (!wr) 						\
-			printk(KERN_ERR"%s: cannot TOG at %p+%x\n",	\
-				#id, regbase, offset);			\
-		if (regset)						\
-			__raw_writel(v, regbase + 			\
-					offset + HW_STMP3xxx_TOG);	\
-		else							\
-			__raw_writel(v ^ __raw_readl(regbase + offset),	\
-				regbase + offset);			\
-	}								\
-	static inline u32 id##_RD(void) { return id##_RD_NB(base); }	\
-	static inline void id##_WR(u32 v) { id##_WR_NB(base, v); }	\
-	static inline void id##_SET(u32 v) { id##_SET_NB(base, v); }	\
-	static inline void id##_CLR(u32 v) { id##_CLR_NB(base, v); }	\
-	static inline void id##_TOG(u32 v) { id##_TOG_NB(base, v); }
-
-#define HW_REGISTER_FUNCS_INDEXED(id, base, offset, regset, rd, wr, step)\
-	static inline u32 id##_OFFSET(int i) {				\
-		return offset + i * step;				\
-	}								\
-	static inline u32 id##_RD_NB(const void __iomem *regbase, int i) {\
-		if (!rd) 						\
-			printk(KERN_ERR"%s(%d): can't READ at %p+%x\n",	\
-				#id, i, regbase, offset + i * step);	\
-		return __raw_readl(regbase + offset + i * step);	\
-	}								\
-	static inline void id##_WR_NB(void __iomem *regbase, int i, u32 v) {\
-		if (!wr) 						\
-			printk(KERN_ERR"%s(%d): can't WRITE at %p+%x\n",\
-				#id, i, regbase, offset + i * step);	\
-		__raw_writel(v, regbase + offset + i * step);		\
-	}								\
-	static inline void id##_SET_NB(void __iomem *regbase, int i, u32 v) {\
-		if (!wr)						\
-			printk(KERN_ERR"%s(%d): can't SET at %p+%x\n",	\
-				#id, i, regbase, offset + i * step);	\
-		if (regset)						\
-			__raw_writel(v, regbase + offset + 		\
-					i * step + HW_STMP3xxx_SET);	\
-		else							\
-			__raw_writel(v | __raw_readl(regbase + 		\
-						offset + i * step),	\
-				regbase + offset + i * step);		\
-	}								\
-	static inline void id##_CLR_NB(void __iomem *regbase, int i, u32 v) {\
-		if (!wr) 						\
-			printk(KERN_ERR"%s(%d): cannot CLR at %p+%x\n",	\
-				#id, i, regbase, offset + i * step);	\
-		if (regset)						\
-			__raw_writel(v, regbase + offset + 		\
-					i * step + HW_STMP3xxx_CLR);	\
-		else							\
-			__raw_writel(~v & __raw_readl(regbase + 	\
-						offset + i * step),	\
-				regbase + offset + i * step);		\
-	}								\
-	static inline void id##_TOG_NB(void __iomem *regbase, int i, u32 v) {\
-		if (!wr) 						\
-			printk(KERN_ERR"%s(%d): cannot TOG at %p+%x\n",	\
-				#id, i, regbase, offset + i * step);	\
-		if (regset)						\
-			__raw_writel(v, regbase + offset + 		\
-					i * step + HW_STMP3xxx_TOG);	\
-		else							\
-			__raw_writel(v ^ __raw_readl(regbase + offset 	\
-						+ i * step),		\
-				regbase + offset + i * step);		\
-	}								\
-	static inline u32 id##_RD(int i) 				\
-	{ 								\
-		return id##_RD_NB(base, i); 				\
-	}								\
-	static inline void id##_WR(int i, u32 v) 			\
-	{ 								\
-		id##_WR_NB(base, i, v); 				\
-	}								\
-	static inline void id##_SET(int i, u32 v) 			\
-	{								\
-		id##_SET_NB(base, i, v); 				\
-	}								\
-	static inline void id##_CLR(int i, u32 v) 			\
-	{ 								\
-		id##_CLR_NB(base, i, v);				\
-	}								\
-	static inline void id##_TOG(int i, u32 v) 			\
-	{ 								\
-		id##_TOG_NB(base, i, v); 				\
-	}
-
-#define HW_REGISTER_WO(id, base, offset)\
-	HW_REGISTER_FUNCS(id, base, offset, 1,  0, 1)
-#define HW_REGISTER_RO(id, base, offset)\
-	HW_REGISTER_FUNCS(id, base, offset, 1,  1, 0)
-#define HW_REGISTER(id, base, offset)	\
-	HW_REGISTER_FUNCS(id, base, offset, 1,	1, 1)
-#define HW_REGISTER_0(id, base, offset)	\
-	HW_REGISTER_FUNCS(id, base, offset, 0,  1, 1)
-#define HW_REGISTER_INDEXED(id, base, offset, step)	\
-	HW_REGISTER_FUNCS_INDEXED(id, base, offset, 1,  1, 1, step)
-#define HW_REGISTER_RO_INDEXED(id, base, offset, step)	\
-	HW_REGISTER_FUNCS_INDEXED(id, base, offset, 1,  1, 0, step)
-#define HW_REGISTER_0_INDEXED(id, base, offset, step)	\
-	HW_REGISTER_FUNCS_INDEXED(id, base, offset, 0,  1, 1, step)
-#else /* __ASSEMBLER__ */
-#define HW_REGISTER_FUNCS(id, base, offset, regset, rd, wr)
-#define HW_REGISTER_FUNCS_INDEXED(id, base, offset, regset, rd, wr, step)
-#define HW_REGISTER_WO(id, base, offset)
-#define HW_REGISTER_RO(id, base, offset)
-#define HW_REGISTER(id, base, offset)
-#define HW_REGISTER_0(id, base, offset)
-#define HW_REGISTER_INDEXED(id, base, offset, step)
-#define HW_REGISTER_RO_INDEXED(id, base, offset, step)
-#define HW_REGISTER_0_INDEXED(id, base, offset, step)
-#endif /* __ASSEMBLER__ */
-
-#endif /* __ASM_PLAT_STMP3XXX_REGS_H */

arch/arm/plat-stmp3xxx/include/mach/system.h

@@ -17,6 +17,7 @@
 #define __ASM_ARCH_SYSTEM_H
 
 #include <asm/proc-fns.h>
+#include <mach/platform.h>
 #include <mach/regs-clkctrl.h>
 #include <mach/regs-power.h>
 
@@ -33,13 +34,14 @@ static inline void arch_idle(void)
 static inline void arch_reset(char mode, const char *cmd)
 {
 	/* Set BATTCHRG to default value */
-	HW_POWER_CHARGE_WR(0x00010000);
+	__raw_writel(0x00010000, REGS_POWER_BASE + HW_POWER_CHARGE);
 
 	/* Set MINPWR to default value   */
-	HW_POWER_MINPWR_WR(0);
+	__raw_writel(0, REGS_POWER_BASE + HW_POWER_MINPWR);
 
 	/* Reset digital side of chip (but not power or RTC) */
-	HW_CLKCTRL_RESET_WR(BM_CLKCTRL_RESET_DIG);
+	__raw_writel(BM_CLKCTRL_RESET_DIG,
+			REGS_CLKCTRL_BASE + HW_CLKCTRL_RESET);
 
 	/* Should not return */
 }

arch/arm/plat-stmp3xxx/irq.c

@@ -22,21 +22,15 @@
 #include <linux/sysdev.h>
 
 #include <mach/stmp3xxx.h>
+#include <mach/platform.h>
 #include <mach/regs-icoll.h>
 
 void __init stmp3xxx_init_irq(struct irq_chip *chip)
 {
-	unsigned int i;
+	unsigned int i, lv;
 
 	/* Reset the interrupt controller */
-	HW_ICOLL_CTRL_CLR(BM_ICOLL_CTRL_CLKGATE);
-	udelay(10);
-	HW_ICOLL_CTRL_CLR(BM_ICOLL_CTRL_SFTRST);
-	udelay(10);
-	HW_ICOLL_CTRL_SET(BM_ICOLL_CTRL_SFTRST);
-	while (!(HW_ICOLL_CTRL_RD() & BM_ICOLL_CTRL_CLKGATE))
-		continue;
-	HW_ICOLL_CTRL_CLR(BM_ICOLL_CTRL_SFTRST | BM_ICOLL_CTRL_CLKGATE);
+	stmp3xxx_reset_block(REGS_ICOLL_BASE + HW_ICOLL_CTRL, true);
 
 	/* Disable all interrupts initially */
 	for (i = 0; i < NR_REAL_IRQS; i++) {
@@ -47,13 +41,11 @@ void __init stmp3xxx_init_irq(struct irq_chip *chip)
 	}
 
 	/* Ensure vector is cleared */
-	HW_ICOLL_LEVELACK_WR(1);
-	HW_ICOLL_LEVELACK_WR(2);
-	HW_ICOLL_LEVELACK_WR(4);
-	HW_ICOLL_LEVELACK_WR(8);
+	for (lv = 0; lv < 4; lv++)
+		__raw_writel(1 << lv, REGS_ICOLL_BASE + HW_ICOLL_LEVELACK);
+	__raw_writel(0, REGS_ICOLL_BASE + HW_ICOLL_VECTOR);
 
-	HW_ICOLL_VECTOR_WR(0);
 	/* Barrier */
-	(void) HW_ICOLL_STAT_RD();
+	(void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT);
 }
 

arch/arm/plat-stmp3xxx/timer.c

@@ -26,6 +26,7 @@
 
 #include <asm/mach/time.h>
 #include <mach/stmp3xxx.h>
+#include <mach/platform.h>
 #include <mach/regs-timrot.h>
 
 static irqreturn_t
@@ -33,13 +34,22 @@ stmp3xxx_timer_interrupt(int irq, void *dev_id)
 {
 	struct clock_event_device *c = dev_id;
 
-	if (HW_TIMROT_TIMCTRLn_RD(0) & (1<<15)) {
-		HW_TIMROT_TIMCTRLn_CLR(0, (1<<15));
+	/* timer 0 */
+	if (__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0) &
+			BM_TIMROT_TIMCTRLn_IRQ) {
+		stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ,
+				REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
 		c->event_handler(c);
-	} else if (HW_TIMROT_TIMCTRLn_RD(1) & (1<<15)) {
-		HW_TIMROT_TIMCTRLn_CLR(1, (1<<15));
-		HW_TIMROT_TIMCTRLn_CLR(1, BM_TIMROT_TIMCTRLn_IRQ_EN);
-		HW_TIMROT_TIMCOUNTn_WR(1, 0xFFFF);
+	}
+
+	/* timer 1 */
+	else if (__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1)
+			& BM_TIMROT_TIMCTRLn_IRQ) {
+		stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ,
+				REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
+		stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ_EN,
+				REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
+		__raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
 	}
 
 	return IRQ_HANDLED;
@@ -47,14 +57,16 @@ stmp3xxx_timer_interrupt(int irq, void *dev_id)
 
 static cycle_t stmp3xxx_clock_read(struct clocksource *cs)
 {
-	return ~((HW_TIMROT_TIMCOUNTn_RD(1) & 0xFFFF0000) >> 16);
+	return ~((__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1)
+				& 0xFFFF0000) >> 16);
 }
 
 static int
 stmp3xxx_timrot_set_next_event(unsigned long delta,
 		struct clock_event_device *dev)
 {
-	HW_TIMROT_TIMCOUNTn_WR(0, delta); /* reload */
+	/* reload the timer */
+	__raw_writel(delta, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
 	return 0;
 }
 
@@ -102,25 +114,29 @@ static void __init stmp3xxx_init_timer(void)
 	ckevt_timrot.max_delta_ns = clockevent_delta2ns(0xFFF, &ckevt_timrot);
 	ckevt_timrot.cpumask = cpumask_of(0);
 
-	HW_TIMROT_ROTCTRL_CLR(BM_TIMROT_ROTCTRL_SFTRST |
-				BM_TIMROT_ROTCTRL_CLKGATE);
-	HW_TIMROT_TIMCOUNTn_WR(0, 0);
-	HW_TIMROT_TIMCOUNTn_WR(1, 0);
-
-	HW_TIMROT_TIMCTRLn_WR(0,
-			      (BF_TIMROT_TIMCTRLn_SELECT(8) |  /* 32 kHz */
-			       BF_TIMROT_TIMCTRLn_PRESCALE(0) |
-			       BM_TIMROT_TIMCTRLn_RELOAD |
-			       BM_TIMROT_TIMCTRLn_UPDATE |
-			       BM_TIMROT_TIMCTRLn_IRQ_EN));
-	HW_TIMROT_TIMCTRLn_WR(1,
-			      (BF_TIMROT_TIMCTRLn_SELECT(8) |  /* 32 kHz */
-			       BF_TIMROT_TIMCTRLn_PRESCALE(0) |
-			       BM_TIMROT_TIMCTRLn_RELOAD |
-			       BM_TIMROT_TIMCTRLn_UPDATE));
-
-	HW_TIMROT_TIMCOUNTn_WR(0, CLOCK_TICK_RATE / HZ - 1);
-	HW_TIMROT_TIMCOUNTn_WR(1, 0xFFFF); /* reload */
+	stmp3xxx_reset_block(REGS_TIMROT_BASE, false);
+
+	/* clear two timers */
+	__raw_writel(0, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
+	__raw_writel(0, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
+
+	/* configure them */
+	__raw_writel(
+		(8 << BP_TIMROT_TIMCTRLn_SELECT) |  /* 32 kHz */
+		BM_TIMROT_TIMCTRLn_RELOAD |
+		BM_TIMROT_TIMCTRLn_UPDATE |
+		BM_TIMROT_TIMCTRLn_IRQ_EN,
+			REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
+	__raw_writel(
+		(8 << BP_TIMROT_TIMCTRLn_SELECT) |  /* 32 kHz */
+		BM_TIMROT_TIMCTRLn_RELOAD |
+		BM_TIMROT_TIMCTRLn_UPDATE |
+		BM_TIMROT_TIMCTRLn_IRQ_EN,
+			REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
+
+	__raw_writel(CLOCK_TICK_RATE / HZ - 1,
+			REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
+	__raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
 
 	setup_irq(IRQ_TIMER0, &stmp3xxx_timer_irq);
 
@@ -132,30 +148,31 @@ static void __init stmp3xxx_init_timer(void)
 
 void stmp3xxx_suspend_timer(void)
 {
-	HW_TIMROT_TIMCTRLn_CLR(0, BM_TIMROT_TIMCTRLn_IRQ_EN);
-	HW_TIMROT_TIMCTRLn_CLR(0, (1<<15));
-	HW_TIMROT_ROTCTRL_SET(BM_TIMROT_ROTCTRL_CLKGATE);
+	stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ_EN | BM_TIMROT_TIMCTRLn_IRQ,
+			REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
+	stmp3xxx_setl(BM_TIMROT_ROTCTRL_CLKGATE,
+			REGS_TIMROT_BASE + HW_TIMROT_ROTCTRL);
 }
 
 void stmp3xxx_resume_timer(void)
 {
-	HW_TIMROT_ROTCTRL_CLR(BM_TIMROT_ROTCTRL_SFTRST |
-				BM_TIMROT_ROTCTRL_CLKGATE);
-
-
-	HW_TIMROT_TIMCTRLn_WR(0,
-			      (BF_TIMROT_TIMCTRLn_SELECT(8) |  /* 32 kHz */
-			       BF_TIMROT_TIMCTRLn_PRESCALE(0) |
-			       BM_TIMROT_TIMCTRLn_UPDATE |
-			       BM_TIMROT_TIMCTRLn_IRQ_EN));
-	HW_TIMROT_TIMCTRLn_WR(1,
-			      (BF_TIMROT_TIMCTRLn_SELECT(8) |  /* 32 kHz */
-			       BF_TIMROT_TIMCTRLn_PRESCALE(0) |
-			       BM_TIMROT_TIMCTRLn_RELOAD |
-			       BM_TIMROT_TIMCTRLn_UPDATE));
-
-	HW_TIMROT_TIMCOUNTn_WR(0, CLOCK_TICK_RATE / HZ - 1);
-	HW_TIMROT_TIMCOUNTn_WR(1, 0xFFFF); /* reload */
+	stmp3xxx_clearl(BM_TIMROT_ROTCTRL_SFTRST | BM_TIMROT_ROTCTRL_CLKGATE,
+			REGS_TIMROT_BASE + HW_TIMROT_ROTCTRL);
+	__raw_writel(
+		8 << BP_TIMROT_TIMCTRLn_SELECT |  /* 32 kHz */
+		BM_TIMROT_TIMCTRLn_RELOAD |
+		BM_TIMROT_TIMCTRLn_UPDATE |
+		BM_TIMROT_TIMCTRLn_IRQ_EN,
+			REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
+	__raw_writel(
+		8 << BP_TIMROT_TIMCTRLn_SELECT |  /* 32 kHz */
+		BM_TIMROT_TIMCTRLn_RELOAD |
+		BM_TIMROT_TIMCTRLn_UPDATE |
+		BM_TIMROT_TIMCTRLn_IRQ_EN,
+			REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
+	__raw_writel(CLOCK_TICK_RATE / HZ - 1,
+			REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
+	__raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
 }
 
 #else