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Commit abb33def authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
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merge

parents 39d6ca01 8c8079c3
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Showing with 446 additions and 301 deletions
Documentation/DMA-mapping.txt
View file @ abb33def
......@@ -132,7 +132,7 @@ exactly why.
The standard 32-bit addressing PCI device would do something like
this:
if (pci_set_dma_mask(pdev, 0xffffffff)) {
if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
printk(KERN_WARNING
"mydev: No suitable DMA available.\n");
goto ignore_this_device;
......@@ -151,9 +151,9 @@ all 64-bits when accessing streaming DMA:
int using_dac;
if (!pci_set_dma_mask(pdev, 0xffffffffffffffff)) {
if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
using_dac = 1;
} else if (!pci_set_dma_mask(pdev, 0xffffffff)) {
} else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
using_dac = 0;
} else {
printk(KERN_WARNING
......@@ -166,14 +166,14 @@ the case would look like this:
int using_dac, consistent_using_dac;
if (!pci_set_dma_mask(pdev, 0xffffffffffffffff)) {
if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
using_dac = 1;
consistent_using_dac = 1;
pci_set_consistent_dma_mask(pdev, 0xffffffffffffffff)
} else if (!pci_set_dma_mask(pdev, 0xffffffff)) {
pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
} else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
using_dac = 0;
consistent_using_dac = 0;
pci_set_consistent_dma_mask(pdev, 0xffffffff)
pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
} else {
printk(KERN_WARNING
"mydev: No suitable DMA available.\n");
......@@ -215,7 +215,7 @@ most specific mask.
Here is pseudo-code showing how this might be done:
#define PLAYBACK_ADDRESS_BITS 0xffffffff
#define PLAYBACK_ADDRESS_BITS DMA_32BIT_MASK
#define RECORD_ADDRESS_BITS 0x00ffffff
struct my_sound_card *card;
......
drivers/net/e1000/e1000.h
View file @ abb33def
......@@ -74,8 +74,6 @@
#define BAR_0 0
#define BAR_1 1
#define BAR_5 5
#define PCI_DMA_64BIT 0xffffffffffffffffULL
#define PCI_DMA_32BIT 0x00000000ffffffffULL
struct e1000_adapter;
......
drivers/net/e1000/e1000_main.c
View file @ abb33def
......@@ -390,10 +390,10 @@ e1000_probe(struct pci_dev *pdev,
if((err = pci_enable_device(pdev)))
return err;
if(!(err = pci_set_dma_mask(pdev, PCI_DMA_64BIT))) {
if(!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
pci_using_dac = 1;
} else {
if((err = pci_set_dma_mask(pdev, PCI_DMA_32BIT))) {
if((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
E1000_ERR("No usable DMA configuration, aborting\n");
return err;
}
......
drivers/net/ixgb/ixgb.h
View file @ abb33def
......@@ -65,8 +65,6 @@ struct ixgb_adapter;
#define BAR_0 0
#define BAR_1 1
#define BAR_5 5
#define PCI_DMA_64BIT 0xffffffffffffffffULL
#define PCI_DMA_32BIT 0x00000000ffffffffULL
#include "ixgb_hw.h"
#include "ixgb_ee.h"
......
drivers/net/ixgb/ixgb_main.c
View file @ abb33def
......@@ -308,10 +308,10 @@ ixgb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
return i;
}
if (!(i = pci_set_dma_mask(pdev, PCI_DMA_64BIT))) {
if (!(i = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
pci_using_dac = 1;
} else {
if ((i = pci_set_dma_mask(pdev, PCI_DMA_32BIT))) {
if ((i = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
IXGB_ERR("No usable DMA configuration, aborting\n");
return i;
}
......
drivers/pci/hotplug/acpiphp_glue.c
View file @ abb33def
......@@ -1243,40 +1243,38 @@ int acpiphp_disable_slot(struct acpiphp_slot *slot)
/**
* acpiphp_check_bridge - re-enumerate devices
*
* Iterate over all slots under this bridge and make sure that if a
* card is present they are enabled, and if not they are disabled.
*/
int acpiphp_check_bridge(struct acpiphp_bridge *bridge)
{
struct acpiphp_slot *slot;
unsigned int sta;
int retval = 0;
int enabled, disabled;
enabled = disabled = 0;
for (slot = bridge->slots; slot; slot = slot->next) {
sta = get_slot_status(slot);
unsigned int status = get_slot_status(slot);
if (slot->flags & SLOT_ENABLED) {
/* if enabled but not present, disable */
if (sta != ACPI_STA_ALL) {
retval = acpiphp_disable_slot(slot);
if (retval) {
err("Error occurred in enabling\n");
up(&slot->crit_sect);
goto err_exit;
}
disabled++;
if (status == ACPI_STA_ALL)
continue;
retval = acpiphp_disable_slot(slot);
if (retval) {
err("Error occurred in disabling\n");
goto err_exit;
}
disabled++;
} else {
/* if disabled but present, enable */
if (sta == ACPI_STA_ALL) {
retval = acpiphp_enable_slot(slot);
if (retval) {
err("Error occurred in enabling\n");
up(&slot->crit_sect);
goto err_exit;
}
enabled++;
if (status != ACPI_STA_ALL)
continue;
retval = acpiphp_enable_slot(slot);
if (retval) {
err("Error occurred in enabling\n");
goto err_exit;
}
enabled++;
}
}
......
drivers/pci/hotplug/acpiphp_pci.c
View file @ abb33def
......@@ -198,106 +198,42 @@ static int init_config_space (struct acpiphp_func *func)
/* detect_used_resource - subtract resource under dev from bridge */
static int detect_used_resource (struct acpiphp_bridge *bridge, struct pci_dev *dev)
{
u32 bar, len;
u64 base;
u32 address[] = {
PCI_BASE_ADDRESS_0,
PCI_BASE_ADDRESS_1,
PCI_BASE_ADDRESS_2,
PCI_BASE_ADDRESS_3,
PCI_BASE_ADDRESS_4,
PCI_BASE_ADDRESS_5,
0
};
int count;
struct pci_resource *res;
dbg("Device %s\n", pci_name(dev));
for (count = 0; address[count]; count++) { /* for 6 BARs */
pci_read_config_dword(dev, address[count], &bar);
for (count = 0; count < DEVICE_COUNT_RESOURCE; count++) {
struct pci_resource *res;
struct pci_resource **head;
unsigned long base = dev->resource[count].start;
unsigned long len = dev->resource[count].end - base + 1;
unsigned long flags = dev->resource[count].flags;
if (!bar) /* This BAR is not implemented */
if (!flags)
continue;
pci_write_config_dword(dev, address[count], 0xFFFFFFFF);
pci_read_config_dword(dev, address[count], &len);
dbg("BAR[%d] 0x%lx - 0x%lx (0x%lx)\n", count, base,
base + len - 1, flags);
if (len & PCI_BASE_ADDRESS_SPACE_IO) {
/* This is IO */
base = bar & 0xFFFFFFFC;
len = len & (PCI_BASE_ADDRESS_IO_MASK & 0xFFFF);
len = len & ~(len - 1);
dbg("BAR[%d] %08x - %08x (IO)\n", count, (u32)base, (u32)base + len - 1);
spin_lock(&bridge->res_lock);
res = acpiphp_get_resource_with_base(&bridge->io_head, base, len);
spin_unlock(&bridge->res_lock);
if (res)
kfree(res);
if (flags & IORESOURCE_IO) {
head = &bridge->io_head;
} else if (flags & IORESOURCE_PREFETCH) {
head = &bridge->p_mem_head;
} else {
/* This is Memory */
base = bar & 0xFFFFFFF0;
if (len & PCI_BASE_ADDRESS_MEM_PREFETCH) {
/* pfmem */
len &= 0xFFFFFFF0;
len = ~len + 1;
if (len & PCI_BASE_ADDRESS_MEM_TYPE_64) { /* takes up another dword */
dbg("prefetch mem 64\n");
count += 1;
}
dbg("BAR[%d] %08x - %08x (PMEM)\n", count, (u32)base, (u32)base + len - 1);
spin_lock(&bridge->res_lock);
res = acpiphp_get_resource_with_base(&bridge->p_mem_head, base, len);
spin_unlock(&bridge->res_lock);
if (res)
kfree(res);
} else {
/* regular memory */
len &= 0xFFFFFFF0;
len = ~len + 1;
if (len & PCI_BASE_ADDRESS_MEM_TYPE_64) {
/* takes up another dword */
dbg("mem 64\n");
count += 1;
}
dbg("BAR[%d] %08x - %08x (MEM)\n", count, (u32)base, (u32)base + len - 1);
spin_lock(&bridge->res_lock);
res = acpiphp_get_resource_with_base(&bridge->mem_head, base, len);
spin_unlock(&bridge->res_lock);
if (res)
kfree(res);
}
head = &bridge->mem_head;
}
pci_write_config_dword(dev, address[count], bar);
spin_lock(&bridge->res_lock);
res = acpiphp_get_resource_with_base(head, base, len);
spin_unlock(&bridge->res_lock);
if (res)
kfree(res);
}
return 0;
}
/* detect_pci_resource_bus - subtract resource under pci_bus */
static void detect_used_resource_bus(struct acpiphp_bridge *bridge, struct pci_bus *bus)
{
struct list_head *l;
struct pci_dev *dev;
list_for_each (l, &bus->devices) {
dev = pci_dev_b(l);
detect_used_resource(bridge, dev);
/* XXX recursive call */
if (dev->subordinate)
detect_used_resource_bus(bridge, dev->subordinate);
}
}
/**
* acpiphp_detect_pci_resource - detect resources under bridge
* @bridge: detect all resources already used under this bridge
......@@ -306,7 +242,13 @@ static void detect_used_resource_bus(struct acpiphp_bridge *bridge, struct pci_b
*/
int acpiphp_detect_pci_resource (struct acpiphp_bridge *bridge)
{
detect_used_resource_bus(bridge, bridge->pci_bus);
struct list_head *l;
struct pci_dev *dev;
list_for_each (l, &bridge->pci_bus->devices) {
dev = pci_dev_b(l);
detect_used_resource(bridge, dev);
}
return 0;
}
......
drivers/pci/hotplug/pci_hotplug.h
View file @ abb33def
......@@ -43,7 +43,7 @@ enum pci_bus_speed {
PCI_SPEED_100MHz_PCIX_266 = 0x0a,
PCI_SPEED_133MHz_PCIX_266 = 0x0b,
PCI_SPEED_66MHz_PCIX_533 = 0x11,
PCI_SPEED_100MHz_PCIX_533 = 0X12,
PCI_SPEED_100MHz_PCIX_533 = 0x12,
PCI_SPEED_133MHz_PCIX_533 = 0x13,
PCI_SPEED_UNKNOWN = 0xff,
};
......
drivers/pci/hotplug/pciehp_ctrl.c
View file @ abb33def
......@@ -135,7 +135,7 @@ u8 pciehp_handle_switch_change(u8 hp_slot, void *inst_id)
p_slot->hpc_ops->get_adapter_status(p_slot, &(func->presence_save));
p_slot->hpc_ops->get_latch_status(p_slot, &getstatus);
if (!getstatus) {
if (getstatus) {
/*
* Switch opened
*/
......@@ -1705,7 +1705,7 @@ int pciehp_enable_slot (struct slot *p_slot)
}
rc = p_slot->hpc_ops->get_latch_status(p_slot, &getstatus);
if (rc || !getstatus) {
if (rc || getstatus) {
info("%s: latch open on slot(%x)\n", __FUNCTION__, p_slot->number);
up(&p_slot->ctrl->crit_sect);
return (0);
......@@ -1792,7 +1792,7 @@ int pciehp_disable_slot (struct slot *p_slot)
}
ret = p_slot->hpc_ops->get_latch_status(p_slot, &getstatus);
if (ret || !getstatus) {
if (ret || getstatus) {
info("%s: latch open on slot(%x)\n", __FUNCTION__, p_slot->number);
up(&p_slot->ctrl->crit_sect);
return (0);
......
drivers/pci/hotplug/pciehp_hpc.c
View file @ abb33def
......@@ -37,6 +37,7 @@
#include <linux/spinlock.h>
#include <linux/pci.h>
#include <asm/system.h>
#include "../pci.h"
#include "pciehp.h"
#ifdef DEBUG
......@@ -315,12 +316,13 @@ static int pcie_write_cmd(struct slot *slot, u16 cmd)
dbg("%s : CMD_COMPLETED not clear after 1 sec.\n", __FUNCTION__);
}
retval = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL, cmd);
dbg("%s: Before hp_register_write_word SLOT_CTRL %x\n", __FUNCTION__, cmd);
retval = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL, cmd | CMD_CMPL_INTR_ENABLE);
if (retval) {
err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
return retval;
}
dbg("%s : hp_register_write_word SLOT_CTRL %x\n", __FUNCTION__, cmd);
dbg("%s : hp_register_write_word SLOT_CTRL %x\n", __FUNCTION__, cmd | CMD_CMPL_INTR_ENABLE);
dbg("%s : Exit\n", __FUNCTION__);
DBG_LEAVE_ROUTINE
......@@ -918,13 +920,32 @@ static irqreturn_t pcie_isr(int IRQ, void *dev_id, struct pt_regs *regs)
return IRQ_NONE;
}
temp_word = (temp_word & ~HP_INTR_ENABLE) | 0x00;
dbg("%s: Set Mask Hot-plug Interrupt Enable\n", __FUNCTION__);
dbg("%s: hp_register_read_word SLOT_CTRL with value %x\n", __FUNCTION__, temp_word);
temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00;
rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL, temp_word);
if (rc) {
err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
return IRQ_NONE;
}
dbg("%s: hp_register_write_word SLOT_CTRL with value %x\n", __FUNCTION__, temp_word);
rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS, slot_status);
if (rc) {
err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
return IRQ_NONE;
}
dbg("%s: hp_register_read_word SLOT_STATUS with value %x\n", __FUNCTION__, slot_status);
/* Clear command complete interrupt caused by this write */
temp_word = 0x1f;
rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS, temp_word);
if (rc) {
err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
return IRQ_NONE;
}
dbg("%s: hp_register_write_word SLOT_STATUS with value %x\n", __FUNCTION__, temp_word);
}
if (intr_loc & CMD_COMPLETED) {
......@@ -949,7 +970,7 @@ static irqreturn_t pcie_isr(int IRQ, void *dev_id, struct pt_regs *regs)
hp_slot, php_ctlr->callback_instance_id);
/* Clear all events after serving them */
temp_word = slot_status | 0xff;
temp_word = 0x1F;
rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS, temp_word);
if (rc) {
err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
......@@ -963,6 +984,8 @@ static irqreturn_t pcie_isr(int IRQ, void *dev_id, struct pt_regs *regs)
return IRQ_NONE;
}
dbg("%s: Unmask Hot-plug Interrupt Enable\n", __FUNCTION__);
dbg("%s: hp_register_read_word SLOT_CTRL with value %x\n", __FUNCTION__, temp_word);
temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE;
rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL, temp_word);
......@@ -970,6 +993,23 @@ static irqreturn_t pcie_isr(int IRQ, void *dev_id, struct pt_regs *regs)
err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
return IRQ_NONE;
}
dbg("%s: hp_register_write_word SLOT_CTRL with value %x\n", __FUNCTION__, temp_word);
rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS, slot_status);
if (rc) {
err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
return IRQ_NONE;
}
dbg("%s: hp_register_read_word SLOT_STATUS with value %x\n", __FUNCTION__, slot_status);
/* Clear command complete interrupt caused by this write */
temp_word = 0x1F;
rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS, temp_word);
if (rc) {
err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
return IRQ_NONE;
}
dbg("%s: hp_register_write_word SLOT_STATUS with value %x\n", __FUNCTION__, temp_word);
}
return IRQ_HANDLED;
......@@ -1330,7 +1370,7 @@ int pcie_init(struct controller * ctrl,
}
dbg("%s: SLOT_CTRL %x value read %x\n", __FUNCTION__, SLOT_CTRL, temp_word);
temp_word = (temp_word & ~HP_INTR_ENABLE) | 0x00;
temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00;
rc = hp_register_write_word(pdev, SLOT_CTRL, temp_word);
if (rc) {
......@@ -1346,12 +1386,13 @@ int pcie_init(struct controller * ctrl,
}
dbg("%s: Mask HPIE SLOT_STATUS offset %x reads slot_status %x\n", __FUNCTION__, SLOT_STATUS, slot_status);
rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS, slot_status);
temp_word = 0x1F; /* Clear all events */
rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS, temp_word);
if (rc) {
err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
goto abort_free_ctlr;
}
dbg("%s: SLOT_STATUS offset %x writes slot_status %x\n", __FUNCTION__, SLOT_STATUS, slot_status);
dbg("%s: SLOT_STATUS offset %x writes slot_status %x\n", __FUNCTION__, SLOT_STATUS, temp_word);
if (pciehp_poll_mode) {/* Install interrupt polling code */
/* Install and start the interrupt polling timer */
......@@ -1359,15 +1400,16 @@ int pcie_init(struct controller * ctrl,
start_int_poll_timer( php_ctlr, 10 ); /* start with 10 second delay */
} else {
/* Installs the interrupt handler */
#ifdef CONFIG_PCI_USE_VECTOR
rc = pci_enable_msi(pdev);
if (rc) {
err("Can't get msi for the hotplug controller\n");
dbg("%s: rc = %x\n", __FUNCTION__, rc);
goto abort_free_ctlr;
dbg("%s: pciehp_msi_quirk = %x\n", __FUNCTION__, pciehp_msi_quirk);
if (!pciehp_msi_quirk) {
rc = pci_enable_msi(pdev);
if (rc) {
info("Can't get msi for the hotplug controller\n");
info("Use INTx for the hotplug controller\n");
dbg("%s: rc = %x\n", __FUNCTION__, rc);
} else
php_ctlr->irq = pdev->irq;
}
php_ctlr->irq = pdev->irq;
#endif
rc = request_irq(php_ctlr->irq, pcie_isr, SA_SHIRQ, MY_NAME, (void *) ctrl);
dbg("%s: request_irq %d for hpc%d (returns %d)\n", __FUNCTION__, php_ctlr->irq, ctlr_seq_num, rc);
if (rc) {
......@@ -1384,7 +1426,7 @@ int pcie_init(struct controller * ctrl,
dbg("%s: SLOT_CTRL %x value read %x\n", __FUNCTION__, SLOT_CTRL, temp_word);
intr_enable = ATTN_BUTTN_ENABLE | PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE |
PRSN_DETECT_ENABLE | CMD_CMPL_INTR_ENABLE;
PRSN_DETECT_ENABLE;
temp_word = (temp_word & ~intr_enable) | intr_enable;
......@@ -1402,6 +1444,21 @@ int pcie_init(struct controller * ctrl,
goto abort_free_ctlr;
}
dbg("%s : Unmask HPIE hp_register_write_word SLOT_CTRL with %x\n", __FUNCTION__, temp_word);
rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS, slot_status);
if (rc) {
err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
goto abort_free_ctlr;
}
dbg("%s: Unmask HPIE SLOT_STATUS offset %x reads slot_status %x\n", __FUNCTION__,
SLOT_STATUS, slot_status);
temp_word = 0x1F; /* Clear all events */
rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS, temp_word);
if (rc) {
err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
goto abort_free_ctlr;
}
dbg("%s: SLOT_STATUS offset %x writes slot_status %x\n", __FUNCTION__, SLOT_STATUS, temp_word);
/* Add this HPC instance into the HPC list */
spin_lock(&list_lock);
......
drivers/pci/hotplug/pciehp_pci.c
View file @ abb33def
......@@ -192,7 +192,6 @@ int pciehp_save_config(struct controller *ctrl, int busnumber, int num_ctlr_slot
for (device = FirstSupported; device <= LastSupported; device++) {
ID = 0xFFFFFFFF;
rc = pci_bus_read_config_dword(pci_bus, PCI_DEVFN(device, 0), PCI_VENDOR_ID, &ID);
dbg("%s: ID = %x\n", __FUNCTION__, ID);
if (ID != 0xFFFFFFFF) { /* device in slot */
dbg("%s: ID = %x\n", __FUNCTION__, ID);
......@@ -325,7 +324,6 @@ int pciehp_save_config(struct controller *ctrl, int busnumber, int num_ctlr_slot
new_slot->presence_save = 0;
new_slot->switch_save = 0;
}
dbg("%s: End of For loop\n", __FUNCTION__);
} /* End of FOR loop */
dbg("%s: Exit\n", __FUNCTION__);
......
drivers/pci/hotplug/rpadlpar_core.c
View file @ abb33def
......@@ -79,25 +79,18 @@ static struct device_node *find_php_slot_pci_node(char *drc_name)
return np;
}
static inline struct hotplug_slot *find_php_slot(char *drc_name)
{
struct kobject *k;
k = kset_find_obj(&pci_hotplug_slots_subsys.kset, drc_name);
if (!k)
return NULL;
return to_hotplug_slot(k);
}
static struct slot *find_slot(char *drc_name)
{
struct hotplug_slot *php_slot = find_php_slot(drc_name);
struct list_head *tmp, *n;
struct slot *slot;
if (!php_slot)
return NULL;
list_for_each_safe(tmp, n, &rpaphp_slot_head) {
slot = list_entry(tmp, struct slot, rpaphp_slot_list);
if (strcmp(slot->location, drc_name) == 0)
return slot;
}
return (struct slot *) php_slot->private;
return NULL;
}
static void rpadlpar_claim_one_bus(struct pci_bus *b)
......
drivers/pci/hotplug/rpaphp.h
View file @ abb33def
......@@ -85,6 +85,7 @@ struct slot {
u32 type;
u32 power_domain;
char *name;
char *location;
struct device_node *dn; /* slot's device_node in OFDT */
/* dn has phb info */
struct pci_dev *bridge; /* slot's pci_dev in pci_devices */
......@@ -129,5 +130,6 @@ extern struct slot *alloc_slot_struct(struct device_node *dn, int drc_index, cha
extern int register_slot(struct slot *slot);
extern int rpaphp_get_power_status(struct slot *slot, u8 * value);
extern int rpaphp_set_attention_status(struct slot *slot, u8 status);
extern void rpaphp_sysfs_remove_attr_location(struct hotplug_slot *slot);
#endif /* _PPC64PHP_H */
drivers/pci/hotplug/rpaphp_core.c
View file @ abb33def
......@@ -246,17 +246,14 @@ static int get_cur_bus_speed(struct hotplug_slot *hotplug_slot, enum pci_bus_spe
int rpaphp_remove_slot(struct slot *slot)
{
int retval = 0;
char *rm_link;
struct hotplug_slot *php_slot = slot->hotplug_slot;
dbg("%s - Entry: slot[%s]\n", __FUNCTION__, slot->name);
if (slot->dev_type == PCI_DEV)
rm_link = pci_name(slot->bridge);
else
rm_link = strstr(slot->dn->full_name, "@");
sysfs_remove_link(slot->hotplug_slot->kobj.parent, rm_link);
list_del(&slot->rpaphp_slot_list);
retval = pci_hp_deregister(slot->hotplug_slot);
/* remove "php_location" file */
rpaphp_sysfs_remove_attr_location(php_slot);
retval = pci_hp_deregister(php_slot);
if (retval)
err("Problem unregistering a slot %s\n", slot->name);
......@@ -380,14 +377,7 @@ static void cleanup_slots(void)
*/
list_for_each_safe(tmp, n, &rpaphp_slot_head) {
char *rm_link;
slot = list_entry(tmp, struct slot, rpaphp_slot_list);
if (slot->dev_type == PCI_DEV)
rm_link = pci_name(slot->bridge);
else
rm_link = strstr(slot->dn->full_name, "@");
sysfs_remove_link(slot->hotplug_slot->kobj.parent, rm_link);
list_del(&slot->rpaphp_slot_list);
pci_hp_deregister(slot->hotplug_slot);
}
......@@ -478,3 +468,4 @@ module_exit(rpaphp_exit);
EXPORT_SYMBOL_GPL(rpaphp_add_slot);
EXPORT_SYMBOL_GPL(rpaphp_remove_slot);
EXPORT_SYMBOL_GPL(rpaphp_slot_head);
drivers/pci/hotplug/rpaphp_pci.c
View file @ abb33def
......@@ -304,7 +304,6 @@ static int setup_pci_hotplug_slot_info(struct slot *slot)
if (slot->hotplug_slot->info->adapter_status == NOT_VALID) {
dbg("%s: NOT_VALID: skip dn->full_name=%s\n",
__FUNCTION__, slot->dn->full_name);
dealloc_slot_struct(slot);
return (-1);
}
return (0);
......
drivers/pci/hotplug/rpaphp_slot.c
View file @ abb33def
......@@ -29,8 +29,36 @@
#include <linux/pci.h>
#include "rpaphp.h"
/* free up the memory user by a slot */
static ssize_t location_read_file (struct hotplug_slot *php_slot, char *buf)
{
char *value;
int retval = -ENOENT;
struct slot *slot = (struct slot *)php_slot->private;
if (!slot)
return retval;
value = slot->location;
retval = sprintf (buf, "%s\n", value);
return retval;
}
static struct hotplug_slot_attribute hotplug_slot_attr_location = {
.attr = {.name = "phy_location", .mode = S_IFREG | S_IRUGO},
.show = location_read_file,
};
static void rpaphp_sysfs_add_attr_location (struct hotplug_slot *slot)
{
sysfs_create_file(&slot->kobj, &hotplug_slot_attr_location.attr);
}
void rpaphp_sysfs_remove_attr_location (struct hotplug_slot *slot)
{
sysfs_remove_file(&slot->kobj, &hotplug_slot_attr_location.attr);
}
/* free up the memory user by a slot */
static void rpaphp_release_slot(struct hotplug_slot *hotplug_slot)
{
struct slot *slot = hotplug_slot? (struct slot *) hotplug_slot->private:NULL;
......@@ -76,17 +104,25 @@ struct slot *alloc_slot_struct(struct device_node *dn, int drc_index, char *drc_
return (NULL);
}
memset(slot->hotplug_slot->info, 0, sizeof (struct hotplug_slot_info));
slot->hotplug_slot->name = kmalloc(strlen(drc_name) + 1, GFP_KERNEL);
slot->hotplug_slot->name = kmalloc(BUS_ID_SIZE + 1, GFP_KERNEL);
if (!slot->hotplug_slot->name) {
kfree(slot->hotplug_slot->info);
kfree(slot->hotplug_slot);
kfree(slot);
return (NULL);
}
slot->location = kmalloc(strlen(drc_name) + 1, GFP_KERNEL);
if (!slot->location) {
kfree(slot->hotplug_slot->info);
kfree(slot->hotplug_slot->name);
kfree(slot->hotplug_slot);
kfree(slot);
return (NULL);
}
slot->name = slot->hotplug_slot->name;
slot->dn = dn;
slot->index = drc_index;
strcpy(slot->name, drc_name);
strcpy(slot->location, drc_name);
slot->power_domain = power_domain;
slot->magic = SLOT_MAGIC;
slot->hotplug_slot->private = slot;
......@@ -110,41 +146,9 @@ int register_slot(struct slot *slot)
rpaphp_release_slot(slot->hotplug_slot);
return (retval);
}
switch (slot->dev_type) {
case PCI_DEV:
/* create symlink between slot->name and it's bus_id */
dbg("%s: sysfs_create_link: %s --> %s\n", __FUNCTION__,
pci_name(slot->bridge), slot->name);
retval = sysfs_create_link(slot->hotplug_slot->kobj.parent,
&slot->hotplug_slot->kobj,
pci_name(slot->bridge));
if (retval) {
err("sysfs_create_link failed with error %d\n", retval);
rpaphp_release_slot(slot->hotplug_slot);
return (retval);
}
break;
case VIO_DEV:
/* create symlink between slot->name and it's uni-address */
vio_uni_addr = strchr(slot->dn->full_name, '@');
if (!vio_uni_addr)
return (1);
dbg("%s: sysfs_create_link: %s --> %s\n", __FUNCTION__,
vio_uni_addr, slot->name);
retval = sysfs_create_link(slot->hotplug_slot->kobj.parent,
&slot->hotplug_slot->kobj,
vio_uni_addr);
if (retval) {
err("sysfs_create_link failed with error %d\n", retval);
rpaphp_release_slot(slot->hotplug_slot);
return (retval);
}
break;
default:
return (1);
}
/* create "phy_locatoin" file */
rpaphp_sysfs_add_attr_location(slot->hotplug_slot);
/* add slot to our internal list */
dbg("%s adding slot[%s] to rpaphp_slot_list\n",
......
drivers/pci/hotplug/shpchp_ctrl.c
View file @ abb33def
......@@ -138,7 +138,7 @@ u8 shpchp_handle_switch_change(u8 hp_slot, void *inst_id)
p_slot->hpc_ops->get_adapter_status(p_slot, &(func->presence_save));
p_slot->hpc_ops->get_latch_status(p_slot, &getstatus);
if (!getstatus) {
if (getstatus) {
/*
* Switch opened
*/
......@@ -1219,7 +1219,7 @@ static u32 board_added(struct pci_func * func, struct controller * ctrl)
up(&ctrl->crit_sect);
}
} else {
if ((bus_speed > 0x4) || (max_bus_speed > 0x4)) {
if (bus_speed > 0x4) {
err("%s: speed of bus %x and adapter %x mismatch\n", __FUNCTION__, bus_speed, adapter_speed);
return WRONG_BUS_FREQUENCY;
}
......@@ -1302,7 +1302,7 @@ static u32 board_added(struct pci_func * func, struct controller * ctrl)
up(&ctrl->crit_sect);
}
} else {
if ((bus_speed > 0x2) || (max_bus_speed > 0x2)) {
if (bus_speed > 0x2) {
err("%s: speed of bus %x and adapter %x mismatch\n", __FUNCTION__, bus_speed, adapter_speed);
return WRONG_BUS_FREQUENCY;
}
......@@ -2107,7 +2107,7 @@ int shpchp_enable_slot (struct slot *p_slot)
return (0);
}
rc = p_slot->hpc_ops->get_latch_status(p_slot, &getstatus);
if (rc || !getstatus) {
if (rc || getstatus) {
info("%s: latch open on slot(%x)\n", __FUNCTION__, p_slot->number);
up(&p_slot->ctrl->crit_sect);
return (0);
......@@ -2192,7 +2192,7 @@ int shpchp_disable_slot (struct slot *p_slot)
return (0);
}
ret = p_slot->hpc_ops->get_latch_status(p_slot, &getstatus);
if (ret || !getstatus) {
if (ret || getstatus) {
info("%s: latch open on slot(%x)\n", __FUNCTION__, p_slot->number);
up(&p_slot->ctrl->crit_sect);
return (0);
......
drivers/pci/hotplug/shpchp_hpc.c
View file @ abb33def
......@@ -104,12 +104,12 @@
#define PCIX_66MHZ_ECC 0x5
#define PCIX_100MHZ_ECC 0x6
#define PCIX_133MHZ_ECC 0x7
#define PCIX_66MHZ_266 0x8
#define PCIX_100MHZ_266 0x9
#define PCIX_133MHZ_266 0x0a
#define PCIX_66MHZ_533 0x0b
#define PCIX_100MHZ_533 0x0c
#define PCIX_133MHZ_533 0x0d
#define PCIX_66MHZ_266 0x9
#define PCIX_100MHZ_266 0xa
#define PCIX_133MHZ_266 0xb
#define PCIX_66MHZ_533 0x11
#define PCIX_100MHZ_533 0x12
#define PCIX_133MHZ_533 0x13
/* Slot Configuration */
#define SLOT_NUM 0x0000001F
......@@ -464,7 +464,8 @@ static int hpc_get_latch_status(struct slot *slot, u8 *status)
slot_reg = readl(php_ctlr->creg + SLOT1 + 4*(slot->hp_slot));
slot_status = (u16)slot_reg;
*status = ((slot_status & 0x0100) == 0) ? 1 : 0;
*status = ((slot_status & 0x0100) == 0) ? 0 : 1; /* 0 -> close; 1 -> open */
DBG_LEAVE_ROUTINE
return 0;
......@@ -1441,6 +1442,7 @@ int shpc_init(struct controller * ctrl,
err("%s : shpc_cap_offset == 0\n", __FUNCTION__);
goto abort_free_ctlr;
}
dbg("%s: shpc_cap_offset = %x\n", __FUNCTION__, shpc_cap_offset);
rc = pci_write_config_byte(pdev, (u8)shpc_cap_offset + DWORD_SELECT , BASE_OFFSET);
if (rc) {
......@@ -1547,15 +1549,13 @@ int shpc_init(struct controller * ctrl,
start_int_poll_timer( php_ctlr, 10 ); /* start with 10 second delay */
} else {
/* Installs the interrupt handler */
#ifdef CONFIG_PCI_USE_VECTOR
rc = pci_enable_msi(pdev);
if (rc) {
err("Can't get msi for the hotplug controller\n");
info("Can't get msi for the hotplug controller\n");
info("Use INTx for the hotplug controller\n");
dbg("%s: rc = %x\n", __FUNCTION__, rc);
goto abort_free_ctlr;
}
php_ctlr->irq = pdev->irq;
#endif
} else
php_ctlr->irq = pdev->irq;
rc = request_irq(php_ctlr->irq, shpc_isr, SA_SHIRQ, MY_NAME, (void *) ctrl);
dbg("%s: request_irq %d for hpc%d (returns %d)\n", __FUNCTION__, php_ctlr->irq, ctlr_seq_num, rc);
......
drivers/pci/hotplug/shpchprm_acpi.c
View file @ abb33def
......@@ -1267,7 +1267,8 @@ static int print_acpi_resources (struct acpi_bridge *ab)
int shpchprm_print_pirt(void)
{
dbg("SHPCHPRM ACPI Slots\n");
print_acpi_resources (acpi_bridges_head);
if (acpi_bridges_head)
print_acpi_resources (acpi_bridges_head);
return 0;
}
......
drivers/pci/hotplug/shpchprm_legacy.c
View file @ abb33def
......@@ -96,23 +96,6 @@ static void *detect_HRT_floating_pointer(void *begin, void *end)
return fp;
}
#if link_available
/*
* Links available memory, IO, and IRQ resources for programming
* devices which may be added to the system
*
* Returns 0 if success
*/
static int
link_available_resources (
struct controller *ctrl,
struct pci_func *func,
int index )
{
return shpchp_save_used_resources (ctrl, func, !DISABLE_CARD);
}
#endif
/*
* shpchprm_find_available_resources
*
......@@ -345,19 +328,6 @@ int shpchprm_find_available_resources(struct controller *ctrl)
}
}
#if link_available
++index;
while (index < 8) {
if (((func = shpchp_slot_find(primary_bus, dev_func >> 3, index)) != NULL) && populated_slot)
rc = link_available_resources(ctrl, func, index);
if (rc)
break;
++index;
}
#endif
i--;
one_slot += sizeof(struct slot_rt);
}
......
drivers/pci/pci-sysfs.c
View file @ abb33def
/*
* drivers/pci/pci-sysfs.c
*
* (C) Copyright 2002 Greg Kroah-Hartman
* (C) Copyright 2002 IBM Corp.
* (C) Copyright 2002-2004 Greg Kroah-Hartman <greg@kroah.com>
* (C) Copyright 2002-2004 IBM Corp.
* (C) Copyright 2003 Matthew Wilcox
* (C) Copyright 2003 Hewlett-Packard
*
......@@ -71,7 +71,7 @@ pci_read_config(struct kobject *kobj, char *buf, loff_t off, size_t count)
/* Several chips lock up trying to read undefined config space */
if (capable(CAP_SYS_ADMIN)) {
size = 256;
size = dev->cfg_size;
} else if (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) {
size = 128;
}
......@@ -123,10 +123,10 @@ pci_write_config(struct kobject *kobj, char *buf, loff_t off, size_t count)
unsigned int size = count;
loff_t init_off = off;
if (off > 256)
if (off > dev->cfg_size)
return 0;
if (off + count > 256) {
size = 256 - off;
if (off + count > dev->cfg_size) {
size = dev->cfg_size - off;
count = size;
}
......@@ -167,6 +167,17 @@ static struct bin_attribute pci_config_attr = {
.write = pci_write_config,
};
static struct bin_attribute pcie_config_attr = {
.attr = {
.name = "config",
.mode = S_IRUGO | S_IWUSR,
.owner = THIS_MODULE,
},
.size = 4096,
.read = pci_read_config,
.write = pci_write_config,
};
void pci_create_sysfs_dev_files (struct pci_dev *pdev)
{
struct device *dev = &pdev->dev;
......@@ -179,7 +190,11 @@ void pci_create_sysfs_dev_files (struct pci_dev *pdev)
device_create_file (dev, &dev_attr_class);
device_create_file (dev, &dev_attr_irq);
device_create_file (dev, &dev_attr_resource);
sysfs_create_bin_file(&dev->kobj, &pci_config_attr);
if (pdev->cfg_size < 4096)
sysfs_create_bin_file(&dev->kobj, &pci_config_attr);
else
sysfs_create_bin_file(&dev->kobj, &pcie_config_attr);
/* add platform-specific attributes */
pcibios_add_platform_entries(pdev);
......
drivers/pci/pci.c
View file @ abb33def
......@@ -111,21 +111,15 @@ static int __pci_bus_find_cap(struct pci_bus *bus, unsigned int devfn, u8 hdr_ty
* support it. Possible values for @cap:
*
* %PCI_CAP_ID_PM Power Management
*
* %PCI_CAP_ID_AGP Accelerated Graphics Port
*
* %PCI_CAP_ID_VPD Vital Product Data
*
* %PCI_CAP_ID_SLOTID Slot Identification
*
* %PCI_CAP_ID_MSI Message Signalled Interrupts
*
* %PCI_CAP_ID_CHSWP CompactPCI HotSwap
*
* %PCI_CAP_ID_PCIX PCI-X
* %PCI_CAP_ID_EXP PCI Express
*/
int
pci_find_capability(struct pci_dev *dev, int cap)
int pci_find_capability(struct pci_dev *dev, int cap)
{
return __pci_bus_find_cap(dev->bus, dev->devfn, dev->hdr_type, cap);
}
......@@ -152,6 +146,54 @@ int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
return __pci_bus_find_cap(bus, devfn, hdr_type & 0x7f, cap);
}
/**
* pci_find_ext_capability - Find an extended capability
* @dev: PCI device to query
* @cap: capability code
*
* Returns the address of the requested extended capability structure
* within the device's PCI configuration space or 0 if the device does
* not support it. Possible values for @cap:
*
* %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
* %PCI_EXT_CAP_ID_VC Virtual Channel
* %PCI_EXT_CAP_ID_DSN Device Serial Number
* %PCI_EXT_CAP_ID_PWR Power Budgeting
*/
int pci_find_ext_capability(struct pci_dev *dev, int cap)
{
u32 header;
int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */
int pos = 0x100;
if (dev->cfg_size <= 256)
return 0;
if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
return 0;
/*
* If we have no capabilities, this is indicated by cap ID,
* cap version and next pointer all being 0.
*/
if (header == 0)
return 0;
while (ttl-- > 0) {
if (PCI_EXT_CAP_ID(header) == cap)
return pos;
pos = PCI_EXT_CAP_NEXT(header);
if (pos < 0x100)
break;
if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
break;
}
return 0;
}
/**
* pci_find_parent_resource - return resource region of parent bus of given region
* @dev: PCI device structure contains resources to be searched
......@@ -658,6 +700,10 @@ pci_clear_mwi(struct pci_dev *dev)
}
}
#ifndef HAVE_ARCH_PCI_SET_DMA_MASK
/*
* These can be overridden by arch-specific implementations
*/
int
pci_set_dma_mask(struct pci_dev *dev, u64 mask)
{
......@@ -690,6 +736,7 @@ pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
return 0;
}
#endif
static int __devinit pci_init(void)
{
......
drivers/pci/pci.h
View file @ abb33def
......@@ -60,3 +60,5 @@ extern int pci_visit_dev(struct pci_visit *fn,
/* Lock for read/write access to pci device and bus lists */
extern spinlock_t pci_bus_lock;
extern int pciehp_msi_quirk;
drivers/pci/probe.c
View file @ abb33def
......@@ -18,6 +18,8 @@
#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
#define CARDBUS_RESERVE_BUSNR 3
#define PCI_CFG_SPACE_SIZE 256
#define PCI_CFG_SPACE_EXP_SIZE 4096
/* Ugh. Need to stop exporting this to modules. */
LIST_HEAD(pci_root_buses);
......@@ -530,6 +532,43 @@ static void pci_release_dev(struct device *dev)
kfree(pci_dev);
}
/**
* pci_cfg_space_size - get the configuration space size of the PCI device.
*
* Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
* have 4096 bytes. Even if the device is capable, that doesn't mean we can
* access it. Maybe we don't have a way to generate extended config space
* accesses, or the device is behind a reverse Express bridge. So we try
* reading the dword at 0x100 which must either be 0 or a valid extended
* capability header.
*/
static int pci_cfg_space_size(struct pci_dev *dev)
{
int pos;
u32 status;
pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
if (!pos) {
pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
if (!pos)
goto fail;
pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
goto fail;
}
if (pci_read_config_dword(dev, 256, &status) != PCIBIOS_SUCCESSFUL)
goto fail;
if (status == 0xffffffff)
goto fail;
return PCI_CFG_SPACE_EXP_SIZE;
fail:
return PCI_CFG_SPACE_SIZE;
}
/*
* Read the config data for a PCI device, sanity-check it
* and fill in the dev structure...
......@@ -566,6 +605,7 @@ pci_scan_device(struct pci_bus *bus, int devfn)
dev->multifunction = !!(hdr_type & 0x80);
dev->vendor = l & 0xffff;
dev->device = (l >> 16) & 0xffff;
dev->cfg_size = pci_cfg_space_size(dev);
/* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
set this higher, assuming the system even supports it. */
......
drivers/pci/proc.c
View file @ abb33def
......@@ -16,16 +16,15 @@
#include <asm/uaccess.h>
#include <asm/byteorder.h>
#define PCI_CFG_SPACE_SIZE 256
static int proc_initialized; /* = 0 */
static loff_t
proc_bus_pci_lseek(struct file *file, loff_t off, int whence)
{
loff_t new = -1;
struct inode *inode = file->f_dentry->d_inode;
down(&file->f_dentry->d_inode->i_sem);
down(&inode->i_sem);
switch (whence) {
case 0:
new = off;
......@@ -34,14 +33,14 @@ proc_bus_pci_lseek(struct file *file, loff_t off, int whence)
new = file->f_pos + off;
break;
case 2:
new = PCI_CFG_SPACE_SIZE + off;
new = inode->i_size + off;
break;
}
if (new < 0 || new > PCI_CFG_SPACE_SIZE)
if (new < 0 || new > inode->i_size)
new = -EINVAL;
else
file->f_pos = new;
up(&file->f_dentry->d_inode->i_sem);
up(&inode->i_sem);
return new;
}
......@@ -61,7 +60,7 @@ proc_bus_pci_read(struct file *file, char __user *buf, size_t nbytes, loff_t *pp
*/
if (capable(CAP_SYS_ADMIN))
size = PCI_CFG_SPACE_SIZE;
size = dev->cfg_size;
else if (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
size = 128;
else
......@@ -134,14 +133,15 @@ proc_bus_pci_write(struct file *file, const char __user *buf, size_t nbytes, lof
const struct proc_dir_entry *dp = PDE(ino);
struct pci_dev *dev = dp->data;
int pos = *ppos;
int size = dev->cfg_size;
int cnt;
if (pos >= PCI_CFG_SPACE_SIZE)
if (pos >= size)
return 0;
if (nbytes >= PCI_CFG_SPACE_SIZE)
nbytes = PCI_CFG_SPACE_SIZE;
if (pos + nbytes > PCI_CFG_SPACE_SIZE)
nbytes = PCI_CFG_SPACE_SIZE - pos;
if (nbytes >= size)
nbytes = size;
if (pos + nbytes > size)
nbytes = size - pos;
cnt = nbytes;
if (!access_ok(VERIFY_READ, buf, cnt))
......@@ -403,7 +403,7 @@ int pci_proc_attach_device(struct pci_dev *dev)
return -ENOMEM;
e->proc_fops = &proc_bus_pci_operations;
e->data = dev;
e->size = PCI_CFG_SPACE_SIZE;
e->size = dev->cfg_size;
return 0;
}
......
drivers/pci/quirks.c
View file @ abb33def
......@@ -868,6 +868,13 @@ static void __init quirk_intel_ide_combined(struct pci_dev *pdev)
}
#endif /* CONFIG_SCSI_SATA */
int pciehp_msi_quirk;
static void __devinit quirk_pciehp_msi(struct pci_dev *pdev)
{
pciehp_msi_quirk = 1;
}
/*
* The main table of quirks.
*
......@@ -984,6 +991,8 @@ static struct pci_fixup pci_fixups[] __devinitdata = {
quirk_intel_ide_combined },
#endif /* CONFIG_SCSI_SATA */
{ PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SMCH, quirk_pciehp_msi },
{ 0 }
};
......@@ -1008,3 +1017,5 @@ void pci_fixup_device(int pass, struct pci_dev *dev)
pci_do_fixups(dev, pass, pcibios_fixups);
pci_do_fixups(dev, pass, pci_fixups);
}
EXPORT_SYMBOL(pciehp_msi_quirk);
include/linux/dma-mapping.h
View file @ abb33def
......@@ -10,6 +10,9 @@ enum dma_data_direction {
DMA_NONE = 3,
};
#define DMA_64BIT_MASK 0xffffffffffffffffULL
#define DMA_32BIT_MASK 0x00000000ffffffffULL
#include <asm/dma-mapping.h>
/* Backwards compat, remove in 2.7.x */
......
include/linux/pci.h
View file @ abb33def
......@@ -305,18 +305,89 @@
#define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
#define PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */
#define PCI_X_CMD_MAX_SPLIT 0x0070 /* Max Outstanding Split Transactions */
#define PCI_X_DEVFN 4 /* A copy of devfn. */
#define PCI_X_BUSNR 5 /* Bus segment number */
#define PCI_X_STATUS 6 /* PCI-X capabilities */
#define PCI_X_STATUS_64BIT 0x0001 /* 64-bit device */
#define PCI_X_STATUS_133MHZ 0x0002 /* 133 MHz capable */
#define PCI_X_STATUS_SPL_DISC 0x0004 /* Split Completion Discarded */
#define PCI_X_STATUS_UNX_SPL 0x0008 /* Unexpected Split Completion */
#define PCI_X_STATUS_COMPLEX 0x0010 /* Device Complexity */
#define PCI_X_STATUS_MAX_READ 0x0060 /* Designed Maximum Memory Read Count */
#define PCI_X_STATUS_MAX_SPLIT 0x0380 /* Design Max Outstanding Split Trans */
#define PCI_X_STATUS_MAX_CUM 0x1c00 /* Designed Max Cumulative Read Size */
#define PCI_X_STATUS_SPL_ERR 0x2000 /* Rcvd Split Completion Error Msg */
#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */
#define PCI_X_STATUS 4 /* PCI-X capabilities */
#define PCI_X_STATUS_DEVFN 0x000000ff /* A copy of devfn */
#define PCI_X_STATUS_BUS 0x0000ff00 /* A copy of bus nr */
#define PCI_X_STATUS_64BIT 0x00010000 /* 64-bit device */
#define PCI_X_STATUS_133MHZ 0x00020000 /* 133 MHz capable */
#define PCI_X_STATUS_SPL_DISC 0x00040000 /* Split Completion Discarded */
#define PCI_X_STATUS_UNX_SPL 0x00080000 /* Unexpected Split Completion */
#define PCI_X_STATUS_COMPLEX 0x00100000 /* Device Complexity */
#define PCI_X_STATUS_MAX_READ 0x00600000 /* Designed Max Memory Read Count */
#define PCI_X_STATUS_MAX_SPLIT 0x03800000 /* Designed Max Outstanding Split Transactions */
#define PCI_X_STATUS_MAX_CUM 0x1c000000 /* Designed Max Cumulative Read Size */
#define PCI_X_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */
#define PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */
#define PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */
/* Extended Capabilities (PCI-X 2.0 and Express) */
#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf)
#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
#define PCI_EXT_CAP_ID_ERR 1
#define PCI_EXT_CAP_ID_VC 2
#define PCI_EXT_CAP_ID_DSN 3
#define PCI_EXT_CAP_ID_PWR 4
/* Advanced Error Reporting */
#define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */
#define PCI_ERR_UNC_TRAIN 0x00000001 /* Training */
#define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */
#define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */
#define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */
#define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */
#define PCI_ERR_UNC_COMP_ABORT 0x00008000 /* Completer Abort */
#define PCI_ERR_UNC_UNX_COMP 0x00010000 /* Unexpected Completion */
#define PCI_ERR_UNC_RX_OVER 0x00020000 /* Receiver Overflow */
#define PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */
#define PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */
#define PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */
#define PCI_ERR_UNCOR_MASK 8 /* Uncorrectable Error Mask */
/* Same bits as above */
#define PCI_ERR_UNCOR_SEVER 12 /* Uncorrectable Error Severity */
/* Same bits as above */
#define PCI_ERR_COR_STATUS 16 /* Correctable Error Status */
#define PCI_ERR_COR_RCVR 0x00000001 /* Receiver Error Status */
#define PCI_ERR_COR_BAD_TLP 0x00000040 /* Bad TLP Status */
#define PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */
#define PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */
#define PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */
#define PCI_ERR_COR_MASK 20 /* Correctable Error Mask */
/* Same bits as above */
#define PCI_ERR_CAP 24 /* Advanced Error Capabilities */
#define PCI_ERR_CAP_FEP(x) ((x) & 31) /* First Error Pointer */
#define PCI_ERR_CAP_ECRC_GENC 0x00000020 /* ECRC Generation Capable */
#define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */
#define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */
#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */
#define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */
#define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */
#define PCI_ERR_ROOT_STATUS 48
#define PCI_ERR_ROOT_COR_SRC 52
#define PCI_ERR_ROOT_SRC 54
/* Virtual Channel */
#define PCI_VC_PORT_REG1 4
#define PCI_VC_PORT_REG2 8
#define PCI_VC_PORT_CTRL 12
#define PCI_VC_PORT_STATUS 14
#define PCI_VC_RES_CAP 16
#define PCI_VC_RES_CTRL 20
#define PCI_VC_RES_STATUS 26
/* Power Budgeting */
#define PCI_PWR_DSR 4 /* Data Select Register */
#define PCI_PWR_DATA 8 /* Data Register */
#define PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */
#define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */
#define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */
#define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */
#define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */
#define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */
#define PCI_PWR_CAP 12 /* Capability */
#define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */
/* Include the ID list */
......@@ -403,6 +474,8 @@ struct pci_dev {
unsigned short vendor_compatible[DEVICE_COUNT_COMPATIBLE];
unsigned short device_compatible[DEVICE_COUNT_COMPATIBLE];
int cfg_size; /* Size of configuration space */
/*
* Instead of touching interrupt line and base address registers
* directly, use the values stored here. They might be different!
......@@ -602,6 +675,7 @@ struct pci_dev *pci_find_subsys (unsigned int vendor, unsigned int device,
struct pci_dev *pci_find_class (unsigned int class, const struct pci_dev *from);
struct pci_dev *pci_find_slot (unsigned int bus, unsigned int devfn);
int pci_find_capability (struct pci_dev *dev, int cap);
int pci_find_ext_capability (struct pci_dev *dev, int cap);
struct pci_bus * pci_find_next_bus(const struct pci_bus *from);
struct pci_dev *pci_get_device (unsigned int vendor, unsigned int device, struct pci_dev *from);
......@@ -774,6 +848,7 @@ static inline int pci_assign_resource(struct pci_dev *dev, int i) { return -EBUS
static inline int pci_register_driver(struct pci_driver *drv) { return 0;}
static inline void pci_unregister_driver(struct pci_driver *drv) { }
static inline int pci_find_capability (struct pci_dev *dev, int cap) {return 0; }
static inline int pci_find_ext_capability (struct pci_dev *dev, int cap) {return 0; }
static inline const struct pci_device_id *pci_match_device(const struct pci_device_id *ids, const struct pci_dev *dev) { return NULL; }
/* Power management related routines */
......
include/linux/pci_ids.h
View file @ abb33def
......@@ -2087,6 +2087,7 @@
#define PCI_DEVICE_ID_INTEL_82830_CGC 0x3577
#define PCI_DEVICE_ID_INTEL_82855GM_HB 0x3580
#define PCI_DEVICE_ID_INTEL_82855GM_IG 0x3582
#define PCI_DEVICE_ID_INTEL_SMCH 0x3590
#define PCI_DEVICE_ID_INTEL_80310 0x530d
#define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000
#define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010
......
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