spi: dw-apb-ssi: Add Intel Keem Bay support

Document Intel Keem Bay SPI controller DT bindings.
Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
Link: https://lore.kernel.org/r/20200505130618.554-7-wan.ahmad.zainie.wan.mohamad@intel.comSigned-off-by: Mark Brown <broonie@kernel.org>

Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt

@@ -2,7 +2,8 @@ Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface.
 
 Required properties:
 - compatible : "snps,dw-apb-ssi" or "mscc,<soc>-spi", where soc is "ocelot" or
-  "jaguar2", or "amazon,alpine-dw-apb-ssi", or "snps,dwc-ssi-1.01a"
+  "jaguar2", or "amazon,alpine-dw-apb-ssi", or "snps,dwc-ssi-1.01a" or
+  "intel,keembay-ssi"
 - reg : The register base for the controller. For "mscc,<soc>-spi", a second
   register set is required (named ICPU_CFG:SPI_MST)
 - interrupts : One interrupt, used by the controller.