Commit c48e0c53 authored by Wan Ahmad Zainie's avatar Wan Ahmad Zainie Committed by Mark Brown

spi: dw-apb-ssi: Add Intel Keem Bay support

Document Intel Keem Bay SPI controller DT bindings.
Signed-off-by: default avatarWan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
Link: https://lore.kernel.org/r/20200505130618.554-7-wan.ahmad.zainie.wan.mohamad@intel.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
parent 3812a081
...@@ -2,7 +2,8 @@ Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface. ...@@ -2,7 +2,8 @@ Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface.
Required properties: Required properties:
- compatible : "snps,dw-apb-ssi" or "mscc,<soc>-spi", where soc is "ocelot" or - compatible : "snps,dw-apb-ssi" or "mscc,<soc>-spi", where soc is "ocelot" or
"jaguar2", or "amazon,alpine-dw-apb-ssi", or "snps,dwc-ssi-1.01a" "jaguar2", or "amazon,alpine-dw-apb-ssi", or "snps,dwc-ssi-1.01a" or
"intel,keembay-ssi"
- reg : The register base for the controller. For "mscc,<soc>-spi", a second - reg : The register base for the controller. For "mscc,<soc>-spi", a second
register set is required (named ICPU_CFG:SPI_MST) register set is required (named ICPU_CFG:SPI_MST)
- interrupts : One interrupt, used by the controller. - interrupts : One interrupt, used by the controller.
......
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