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nexedi
linux
Commits
c6906c3e
Commit
c6906c3e
authored
Jan 03, 2011
by
Kukjin Kim
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Merge branch 'next-s5pv310' into for-next
Conflicts: arch/arm/mach-s5pv310/Makefile
parents
285dee7f
8267e2e0
Changes
8
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8 changed files
with
711 additions
and
9 deletions
+711
-9
arch/arm/Kconfig
arch/arm/Kconfig
+1
-0
arch/arm/mach-s5pv310/Makefile
arch/arm/mach-s5pv310/Makefile
+1
-0
arch/arm/mach-s5pv310/clock.c
arch/arm/mach-s5pv310/clock.c
+21
-7
arch/arm/mach-s5pv310/cpu.c
arch/arm/mach-s5pv310/cpu.c
+5
-0
arch/arm/mach-s5pv310/cpufreq.c
arch/arm/mach-s5pv310/cpufreq.c
+580
-0
arch/arm/mach-s5pv310/include/mach/map.h
arch/arm/mach-s5pv310/include/mach/map.h
+2
-0
arch/arm/mach-s5pv310/include/mach/regs-clock.h
arch/arm/mach-s5pv310/include/mach/regs-clock.h
+78
-2
arch/arm/mach-s5pv310/include/mach/regs-mem.h
arch/arm/mach-s5pv310/include/mach/regs-mem.h
+23
-0
No files found.
arch/arm/Kconfig
View file @
c6906c3e
...
...
@@ -738,6 +738,7 @@ config ARCH_S5PV310
select ARCH_SPARSEMEM_ENABLE
select GENERIC_GPIO
select HAVE_CLK
select ARCH_HAS_CPUFREQ
select GENERIC_CLOCKEVENTS
select HAVE_S3C_RTC if RTC_CLASS
select HAVE_S3C2410_I2C if I2C
...
...
arch/arm/mach-s5pv310/Makefile
View file @
c6906c3e
...
...
@@ -14,6 +14,7 @@ obj- :=
obj-$(CONFIG_CPU_S5PV310)
+=
cpu.o init.o clock.o irq-combiner.o
obj-$(CONFIG_CPU_S5PV310)
+=
setup-i2c0.o time.o gpiolib.o irq-eint.o dma.o
obj-$(CONFIG_CPU_FREQ)
+=
cpufreq.o
obj-$(CONFIG_SMP)
+=
platsmp.o headsmp.o
obj-$(CONFIG_LOCAL_TIMERS)
+=
localtimer.o
...
...
arch/arm/mach-s5pv310/clock.c
View file @
c6906c3e
...
...
@@ -244,7 +244,7 @@ static struct clksrc_clk clk_mout_corebus = {
.
id
=
-
1
,
},
.
sources
=
&
clkset_mout_corebus
,
.
reg_src
=
{
.
reg
=
S5P_CLKSRC_
CORE
,
.
shift
=
4
,
.
size
=
1
},
.
reg_src
=
{
.
reg
=
S5P_CLKSRC_
DMC
,
.
shift
=
4
,
.
size
=
1
},
};
static
struct
clksrc_clk
clk_sclk_dmc
=
{
...
...
@@ -253,7 +253,7 @@ static struct clksrc_clk clk_sclk_dmc = {
.
id
=
-
1
,
.
parent
=
&
clk_mout_corebus
.
clk
,
},
.
reg_div
=
{
.
reg
=
S5P_CLKDIV_
CORE
0
,
.
shift
=
12
,
.
size
=
3
},
.
reg_div
=
{
.
reg
=
S5P_CLKDIV_
DMC
0
,
.
shift
=
12
,
.
size
=
3
},
};
static
struct
clksrc_clk
clk_aclk_cored
=
{
...
...
@@ -262,7 +262,7 @@ static struct clksrc_clk clk_aclk_cored = {
.
id
=
-
1
,
.
parent
=
&
clk_sclk_dmc
.
clk
,
},
.
reg_div
=
{
.
reg
=
S5P_CLKDIV_
CORE
0
,
.
shift
=
16
,
.
size
=
3
},
.
reg_div
=
{
.
reg
=
S5P_CLKDIV_
DMC
0
,
.
shift
=
16
,
.
size
=
3
},
};
static
struct
clksrc_clk
clk_aclk_corep
=
{
...
...
@@ -271,7 +271,7 @@ static struct clksrc_clk clk_aclk_corep = {
.
id
=
-
1
,
.
parent
=
&
clk_aclk_cored
.
clk
,
},
.
reg_div
=
{
.
reg
=
S5P_CLKDIV_
CORE
0
,
.
shift
=
20
,
.
size
=
3
},
.
reg_div
=
{
.
reg
=
S5P_CLKDIV_
DMC
0
,
.
shift
=
20
,
.
size
=
3
},
};
static
struct
clksrc_clk
clk_aclk_acp
=
{
...
...
@@ -280,7 +280,7 @@ static struct clksrc_clk clk_aclk_acp = {
.
id
=
-
1
,
.
parent
=
&
clk_mout_corebus
.
clk
,
},
.
reg_div
=
{
.
reg
=
S5P_CLKDIV_
CORE
0
,
.
shift
=
0
,
.
size
=
3
},
.
reg_div
=
{
.
reg
=
S5P_CLKDIV_
DMC
0
,
.
shift
=
0
,
.
size
=
3
},
};
static
struct
clksrc_clk
clk_pclk_acp
=
{
...
...
@@ -289,7 +289,7 @@ static struct clksrc_clk clk_pclk_acp = {
.
id
=
-
1
,
.
parent
=
&
clk_aclk_acp
.
clk
,
},
.
reg_div
=
{
.
reg
=
S5P_CLKDIV_
CORE
0
,
.
shift
=
4
,
.
size
=
3
},
.
reg_div
=
{
.
reg
=
S5P_CLKDIV_
DMC
0
,
.
shift
=
4
,
.
size
=
3
},
};
/* Core list of CMU_TOP side */
...
...
@@ -1020,6 +1020,17 @@ static struct clksrc_clk *sysclks[] = {
&
clk_dout_mmc4
,
};
static
int
xtal_rate
;
static
unsigned
long
s5pv310_fout_apll_get_rate
(
struct
clk
*
clk
)
{
return
s5p_get_pll45xx
(
xtal_rate
,
__raw_readl
(
S5P_APLL_CON0
),
pll_4508
);
}
static
struct
clk_ops
s5pv310_fout_apll_ops
=
{
.
get_rate
=
s5pv310_fout_apll_get_rate
,
};
void
__init_or_cpufreq
s5pv310_setup_clocks
(
void
)
{
struct
clk
*
xtal_clk
;
...
...
@@ -1043,6 +1054,9 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
BUG_ON
(
IS_ERR
(
xtal_clk
));
xtal
=
clk_get_rate
(
xtal_clk
);
xtal_rate
=
xtal
;
clk_put
(
xtal_clk
);
printk
(
KERN_DEBUG
"%s: xtal is %ld
\n
"
,
__func__
,
xtal
);
...
...
@@ -1056,7 +1070,7 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
vpll
=
s5p_get_pll46xx
(
vpllsrc
,
__raw_readl
(
S5P_VPLL_CON0
),
__raw_readl
(
S5P_VPLL_CON1
),
pll_4650
);
clk_fout_apll
.
rate
=
apll
;
clk_fout_apll
.
ops
=
&
s5pv310_fout_apll_ops
;
clk_fout_mpll
.
rate
=
mpll
;
clk_fout_epll
.
rate
=
epll
;
clk_fout_vpll
.
rate
=
vpll
;
...
...
arch/arm/mach-s5pv310/cpu.c
View file @
c6906c3e
...
...
@@ -77,6 +77,11 @@ static struct map_desc s5pv310_iodesc[] __initdata = {
.
pfn
=
__phys_to_pfn
(
S5PV310_PA_GPIO3
),
.
length
=
SZ_256
,
.
type
=
MT_DEVICE
,
},
{
.
virtual
=
(
unsigned
long
)
S5P_VA_DMC0
,
.
pfn
=
__phys_to_pfn
(
S5PV310_PA_DMC0
),
.
length
=
SZ_4K
,
.
type
=
MT_DEVICE
,
},
{
.
virtual
=
(
unsigned
long
)
S3C_VA_UART
,
.
pfn
=
__phys_to_pfn
(
S3C_PA_UART
),
...
...
arch/arm/mach-s5pv310/cpufreq.c
0 → 100644
View file @
c6906c3e
This diff is collapsed.
Click to expand it.
arch/arm/mach-s5pv310/include/mach/map.h
View file @
c6906c3e
...
...
@@ -46,6 +46,8 @@
#define S5PV310_PA_WATCHDOG (0x10060000)
#define S5PV310_PA_RTC (0x10070000)
#define S5PV310_PA_DMC0 (0x10400000)
#define S5PV310_PA_COMBINER (0x10448000)
#define S5PV310_PA_COREPERI (0x10500000)
...
...
arch/arm/mach-s5pv310/include/mach/regs-clock.h
View file @
c6906c3e
...
...
@@ -19,6 +19,12 @@
#define S5P_INFORM0 S5P_CLKREG(0x800)
#define S5P_CLKDIV_LEFTBUS S5P_CLKREG(0x04500)
#define S5P_CLKDIV_STAT_LEFTBUS S5P_CLKREG(0x04600)
#define S5P_CLKDIV_RIGHTBUS S5P_CLKREG(0x08500)
#define S5P_CLKDIV_STAT_RIGHTBUS S5P_CLKREG(0x08600)
#define S5P_EPLL_CON0 S5P_CLKREG(0x0C110)
#define S5P_EPLL_CON1 S5P_CLKREG(0x0C114)
#define S5P_VPLL_CON0 S5P_CLKREG(0x0C120)
...
...
@@ -58,6 +64,8 @@
#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350)
#define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354)
#define S5P_CLKDIV_STAT_TOP S5P_CLKREG(0x0C610)
#define S5P_CLKGATE_IP_CAM S5P_CLKREG(0x0C920)
#define S5P_CLKGATE_IP_IMAGE S5P_CLKREG(0x0C930)
#define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934)
...
...
@@ -66,8 +74,9 @@
#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950)
#define S5P_CLKGATE_IP_PERIR S5P_CLKREG(0x0C960)
#define S5P_CLKSRC_CORE S5P_CLKREG(0x10200)
#define S5P_CLKDIV_CORE0 S5P_CLKREG(0x10500)
#define S5P_CLKSRC_DMC S5P_CLKREG(0x10200)
#define S5P_CLKDIV_DMC0 S5P_CLKREG(0x10500)
#define S5P_CLKDIV_STAT_DMC0 S5P_CLKREG(0x10600)
#define S5P_APLL_LOCK S5P_CLKREG(0x14000)
#define S5P_MPLL_LOCK S5P_CLKREG(0x14004)
...
...
@@ -80,10 +89,77 @@
#define S5P_CLKMUX_STATCPU S5P_CLKREG(0x14400)
#define S5P_CLKDIV_CPU S5P_CLKREG(0x14500)
#define S5P_CLKDIV_CPU1 S5P_CLKREG(0x14504)
#define S5P_CLKDIV_STATCPU S5P_CLKREG(0x14600)
#define S5P_CLKDIV_STATCPU1 S5P_CLKREG(0x14604)
#define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800)
/* APLL_LOCK */
#define S5P_APLL_LOCKTIME (0x1C20)
/* 300us */
/* APLL_CON0 */
#define S5P_APLLCON0_ENABLE_SHIFT (31)
#define S5P_APLLCON0_LOCKED_SHIFT (29)
#define S5P_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1)
#define S5P_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1)
/* CLK_SRC_CPU */
#define S5P_CLKSRC_CPU_MUXCORE_SHIFT (16)
#define S5P_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)
/* CLKDIV_CPU0 */
#define S5P_CLKDIV_CPU0_CORE_SHIFT (0)
#define S5P_CLKDIV_CPU0_CORE_MASK (0x7 << S5P_CLKDIV_CPU0_CORE_SHIFT)
#define S5P_CLKDIV_CPU0_COREM0_SHIFT (4)
#define S5P_CLKDIV_CPU0_COREM0_MASK (0x7 << S5P_CLKDIV_CPU0_COREM0_SHIFT)
#define S5P_CLKDIV_CPU0_COREM1_SHIFT (8)
#define S5P_CLKDIV_CPU0_COREM1_MASK (0x7 << S5P_CLKDIV_CPU0_COREM1_SHIFT)
#define S5P_CLKDIV_CPU0_PERIPH_SHIFT (12)
#define S5P_CLKDIV_CPU0_PERIPH_MASK (0x7 << S5P_CLKDIV_CPU0_PERIPH_SHIFT)
#define S5P_CLKDIV_CPU0_ATB_SHIFT (16)
#define S5P_CLKDIV_CPU0_ATB_MASK (0x7 << S5P_CLKDIV_CPU0_ATB_SHIFT)
#define S5P_CLKDIV_CPU0_PCLKDBG_SHIFT (20)
#define S5P_CLKDIV_CPU0_PCLKDBG_MASK (0x7 << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT)
#define S5P_CLKDIV_CPU0_APLL_SHIFT (24)
#define S5P_CLKDIV_CPU0_APLL_MASK (0x7 << S5P_CLKDIV_CPU0_APLL_SHIFT)
/* CLKDIV_DMC0 */
#define S5P_CLKDIV_DMC0_ACP_SHIFT (0)
#define S5P_CLKDIV_DMC0_ACP_MASK (0x7 << S5P_CLKDIV_DMC0_ACP_SHIFT)
#define S5P_CLKDIV_DMC0_ACPPCLK_SHIFT (4)
#define S5P_CLKDIV_DMC0_ACPPCLK_MASK (0x7 << S5P_CLKDIV_DMC0_ACPPCLK_SHIFT)
#define S5P_CLKDIV_DMC0_DPHY_SHIFT (8)
#define S5P_CLKDIV_DMC0_DPHY_MASK (0x7 << S5P_CLKDIV_DMC0_DPHY_SHIFT)
#define S5P_CLKDIV_DMC0_DMC_SHIFT (12)
#define S5P_CLKDIV_DMC0_DMC_MASK (0x7 << S5P_CLKDIV_DMC0_DMC_SHIFT)
#define S5P_CLKDIV_DMC0_DMCD_SHIFT (16)
#define S5P_CLKDIV_DMC0_DMCD_MASK (0x7 << S5P_CLKDIV_DMC0_DMCD_SHIFT)
#define S5P_CLKDIV_DMC0_DMCP_SHIFT (20)
#define S5P_CLKDIV_DMC0_DMCP_MASK (0x7 << S5P_CLKDIV_DMC0_DMCP_SHIFT)
#define S5P_CLKDIV_DMC0_COPY2_SHIFT (24)
#define S5P_CLKDIV_DMC0_COPY2_MASK (0x7 << S5P_CLKDIV_DMC0_COPY2_SHIFT)
#define S5P_CLKDIV_DMC0_CORETI_SHIFT (28)
#define S5P_CLKDIV_DMC0_CORETI_MASK (0x7 << S5P_CLKDIV_DMC0_CORETI_SHIFT)
/* CLKDIV_TOP */
#define S5P_CLKDIV_TOP_ACLK200_SHIFT (0)
#define S5P_CLKDIV_TOP_ACLK200_MASK (0x7 << S5P_CLKDIV_TOP_ACLK200_SHIFT)
#define S5P_CLKDIV_TOP_ACLK100_SHIFT (4)
#define S5P_CLKDIV_TOP_ACLK100_MASK (0xf << S5P_CLKDIV_TOP_ACLK100_SHIFT)
#define S5P_CLKDIV_TOP_ACLK160_SHIFT (8)
#define S5P_CLKDIV_TOP_ACLK160_MASK (0x7 << S5P_CLKDIV_TOP_ACLK160_SHIFT)
#define S5P_CLKDIV_TOP_ACLK133_SHIFT (12)
#define S5P_CLKDIV_TOP_ACLK133_MASK (0x7 << S5P_CLKDIV_TOP_ACLK133_SHIFT)
#define S5P_CLKDIV_TOP_ONENAND_SHIFT (16)
#define S5P_CLKDIV_TOP_ONENAND_MASK (0x7 << S5P_CLKDIV_TOP_ONENAND_SHIFT)
/* CLKDIV_LEFTBUS / CLKDIV_RIGHTBUS*/
#define S5P_CLKDIV_BUS_GDLR_SHIFT (0)
#define S5P_CLKDIV_BUS_GDLR_MASK (0x7 << S5P_CLKDIV_BUS_GDLR_SHIFT)
#define S5P_CLKDIV_BUS_GPLR_SHIFT (4)
#define S5P_CLKDIV_BUS_GPLR_MASK (0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT)
/* Compatibility defines */
#define S5P_EPLL_CON S5P_EPLL_CON0
...
...
arch/arm/mach-s5pv310/include/mach/regs-mem.h
0 → 100644
View file @
c6906c3e
/* linux/arch/arm/mach-s5pv310/include/mach/regs-mem.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5PV310 - SROMC and DMC register definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_REGS_MEM_H
#define __ASM_ARCH_REGS_MEM_H __FILE__
#include <mach/map.h>
#define S5P_DMC0_MEMCON_OFFSET 0x04
#define S5P_DMC0_MEMTYPE_SHIFT 8
#define S5P_DMC0_MEMTYPE_MASK 0xF
#endif
/* __ASM_ARCH_REGS_MEM_H */
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