Commit c7861adb authored by Vladimir Oltean's avatar Vladimir Oltean Committed by Shawn Guo

ARM: dts: ls1021: Fix SGMII PCS link remaining down after PHY disconnect

Each eTSEC MAC has its own TBI (SGMII) PCS and private MDIO bus.
But due to a DTS oversight, both SGMII-compatible MACs of the LS1021 SoC
are pointing towards the same internal PCS. Therefore nobody is
controlling the internal PCS of eTSEC0.

Upon initial ndo_open, the SGMII link is ok by virtue of U-boot
initialization. But upon an ifdown/ifup sequence, the code path from
ndo_open -> init_phy -> gfar_configure_serdes does not get executed for
the PCS of eTSEC0 (and is executed twice for MAC eTSEC1). So the SGMII
link remains down for eTSEC0. On the LS1021A-TWR board, to signal this
failure condition, the PHY driver keeps printing
'803x_aneg_done: SGMII link is not ok'.

Also, it changes compatible of mdio0 to "fsl,etsec2-mdio" to match
mdio1 device.

Fixes: 055223d4 ("ARM: dts: ls1021a: Enable the eTSEC ports on QDS and TWR")
Signed-off-by: default avatarVladimir Oltean <olteanv@gmail.com>
Reviewed-by: default avatarClaudiu Manoil <claudiu.manoil@nxp.com>
Acked-by: default avatarLi Yang <leoyang.li@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 7aedca87
...@@ -145,7 +145,7 @@ dspiflash: s25fl064k@0 { ...@@ -145,7 +145,7 @@ dspiflash: s25fl064k@0 {
}; };
&enet0 { &enet0 {
tbi-handle = <&tbi1>; tbi-handle = <&tbi0>;
phy-handle = <&sgmii_phy2>; phy-handle = <&sgmii_phy2>;
phy-connection-type = "sgmii"; phy-connection-type = "sgmii";
status = "okay"; status = "okay";
...@@ -225,6 +225,13 @@ rgmii_phy1: ethernet-phy@1 { ...@@ -225,6 +225,13 @@ rgmii_phy1: ethernet-phy@1 {
sgmii_phy2: ethernet-phy@2 { sgmii_phy2: ethernet-phy@2 {
reg = <0x2>; reg = <0x2>;
}; };
tbi0: tbi-phy@1f {
reg = <0x1f>;
device_type = "tbi-phy";
};
};
&mdio1 {
tbi1: tbi-phy@1f { tbi1: tbi-phy@1f {
reg = <0x1f>; reg = <0x1f>;
device_type = "tbi-phy"; device_type = "tbi-phy";
......
...@@ -701,7 +701,7 @@ dcu: dcu@2ce0000 { ...@@ -701,7 +701,7 @@ dcu: dcu@2ce0000 {
}; };
mdio0: mdio@2d24000 { mdio0: mdio@2d24000 {
compatible = "gianfar"; compatible = "fsl,etsec2-mdio";
device_type = "mdio"; device_type = "mdio";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
...@@ -709,6 +709,15 @@ mdio0: mdio@2d24000 { ...@@ -709,6 +709,15 @@ mdio0: mdio@2d24000 {
<0x0 0x2d10030 0x0 0x4>; <0x0 0x2d10030 0x0 0x4>;
}; };
mdio1: mdio@2d64000 {
compatible = "fsl,etsec2-mdio";
device_type = "mdio";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2d64000 0x0 0x4000>,
<0x0 0x2d50030 0x0 0x4>;
};
ptp_clock@2d10e00 { ptp_clock@2d10e00 {
compatible = "fsl,etsec-ptp"; compatible = "fsl,etsec-ptp";
reg = <0x0 0x2d10e00 0x0 0xb0>; reg = <0x0 0x2d10e00 0x0 0xb0>;
......
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