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Commit d64b3932 authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'pinctrl-v3.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl 

Pull pin control bulk changes from Linus Walleij:
 "Pin control bulk changes for the v3.15 series, no new core
  functionality this time, just incremental driver updates:

   - A large refactoring of the MVEBU (Marvell) driver.

   - A large refactoring of the Tegra (nVidia) driver.

   - GPIO interrupt including soft edges support in the STi driver.

   - Misc updates to PFC (Renesas), AT91, ADI2 (Blackfin),
     pinctrl-single, sirf (CSR), msm (Qualcomm), Exynos (Samsung), sunxi
     (AllWinner), i.MX (Freescale), Baytrail"

* tag 'pinctrl-v3.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (72 commits)
  pinctrl: tegra: add some missing Tegra114 entries
  pinctrl: tegra: fix some mistakes in Tegra124
  pinctrl: msm: fix up out-of-order merge conflict
  pinctrl: st: Fix error check for of_irq_to_resource usage
  pinctrl: tegra: consistency cleanup
  pinctrl: tegra: dynamically calculate function list of groups
  pinctrl: tegra: init Tegra20/30 at module_init time
  pinctrl: st: Use ARRAY_SIZE instead of raw value for number of delays
  pinctrl: st: add pinctrl support for the STiH407 SoC
  pinctrl: st: Enhance the controller to manage unavailable registers
  pinctrl: msm: Simplify msm_config_reg() and callers
  pinctrl: msm: Remove impossible WARN_ON()s
  pinctrl: msm: Replace lookup tables with math
  pinctrl: msm: Drop OF_IRQ dependency
  pinctrl: msm: Drop unused includes
  pinctrl: msm: Check for ngpios > MAX_NR_GPIO
  pinctrl: msm: Silence recursive lockdep warning
  pinctrl: mvebu: silence WARN to dev_warn
  pinctrl: msm: drop wake_irqs bitmap
  pinctrl-baytrail: add function mux checking in gpio pin request
  ...
parents 4dedde7c 43f23a06
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Documentation/devicetree/bindings/arm/marvell,dove.txt 0 → 100644
View file @ d64b3932
Marvell Dove Platforms Device Tree Bindings
-----------------------------------------------
Boards with a Marvell Dove SoC shall have the following properties:
Required root node property:
- compatible: must contain "marvell,dove";
* Global Configuration registers
Global Configuration registers of Dove SoC are shared by a syscon node.
Required properties:
- compatible: must contain "marvell,dove-global-config" and "syscon".
- reg: base address and size of the Global Configuration registers.
Example:
gconf: global-config@e802c {
compatible = "marvell,dove-global-config", "syscon";
reg = <0xe802c 0x14>;
};
Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
View file @ d64b3932
......@@ -5,6 +5,7 @@ part and usage.
Required properties:
- compatible: "marvell,88f6710-pinctrl"
- reg: register specifier of MPP registers
Available mpp pins/groups and functions:
Note: brackets (x) are not part of the mpp name for marvell,function and given
......
Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt 0 → 100644
View file @ d64b3932
* Marvell Armada 375 SoC pinctrl driver for mpp
Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
part and usage.
Required properties:
- compatible: "marvell,88f6720-pinctrl"
- reg: register specifier of MPP registers
Available mpp pins/groups and functions:
Note: brackets (x) are not part of the mpp name for marvell,function and given
only for more detailed description in this document.
name pins functions
================================================================================
mpp0 0 gpio, dev(ad2), spi0(cs1), spi1(cs1)
mpp1 1 gpio, dev(ad3), spi0(mosi), spi1(mosi)
mpp2 2 gpio, dev(ad4), ptp(eventreq), led(c0), audio(sdi)
mpp3 3 gpio, dev(ad5), ptp(triggen), led(p3), audio(mclk)
mpp4 4 gpio, dev(ad6), spi0(miso), spi1(miso)
mpp5 5 gpio, dev(ad7), spi0(cs2), spi1(cs2)
mpp6 6 gpio, dev(ad0), led(p1), audio(rclk)
mpp7 7 gpio, dev(ad1), ptp(clk), led(p2), audio(extclk)
mpp8 8 gpio, dev (bootcs), spi0(cs0), spi1(cs0)
mpp9 9 gpio, nf(wen), spi0(sck), spi1(sck)
mpp10 10 gpio, nf(ren), dram(vttctrl), led(c1)
mpp11 11 gpio, dev(a0), led(c2), audio(sdo)
mpp12 12 gpio, dev(a1), audio(bclk)
mpp13 13 gpio, dev(readyn), pcie0(rstoutn), pcie1(rstoutn)
mpp14 14 gpio, i2c0(sda), uart1(txd)
mpp15 15 gpio, i2c0(sck), uart1(rxd)
mpp16 16 gpio, uart0(txd)
mpp17 17 gpio, uart0(rxd)
mpp18 18 gpio, tdm(intn)
mpp19 19 gpio, tdm(rstn)
mpp20 20 gpio, tdm(pclk)
mpp21 21 gpio, tdm(fsync)
mpp22 22 gpio, tdm(drx)
mpp23 23 gpio, tdm(dtx)
mpp24 24 gpio, led(p0), ge1(rxd0), sd(cmd), uart0(rts)
mpp25 25 gpio, led(p2), ge1(rxd1), sd(d0), uart0(cts)
mpp26 26 gpio, pcie0(clkreq), ge1(rxd2), sd(d2), uart1(rts)
mpp27 27 gpio, pcie1(clkreq), ge1(rxd3), sd(d1), uart1(cts)
mpp28 28 gpio, led(p3), ge1(txctl), sd(clk)
mpp29 29 gpio, pcie1(clkreq), ge1(rxclk), sd(d3)
mpp30 30 gpio, ge1(txd0), spi1(cs0)
mpp31 31 gpio, ge1(txd1), spi1(mosi)
mpp32 32 gpio, ge1(txd2), spi1(sck), ptp(triggen)
mpp33 33 gpio, ge1(txd3), spi1(miso)
mpp34 34 gpio, ge1(txclkout), spi1(sck)
mpp35 35 gpio, ge1(rxctl), spi1(cs1), spi0(cs2)
mpp36 36 gpio, pcie0(clkreq)
mpp37 37 gpio, pcie0(clkreq), tdm(intn), ge(mdc)
mpp38 38 gpio, pcie1(clkreq), ge(mdio)
mpp39 39 gpio, ref(clkout)
mpp40 40 gpio, uart1(txd)
mpp41 41 gpio, uart1(rxd)
mpp42 42 gpio, spi1(cs2), led(c0)
mpp43 43 gpio, sata0(prsnt), dram(vttctrl)
mpp44 44 gpio, sata0(prsnt)
mpp45 45 gpio, spi0(cs2), pcie0(rstoutn)
mpp46 46 gpio, led(p0), ge0(txd0), ge1(txd0)
mpp47 47 gpio, led(p1), ge0(txd1), ge1(txd1)
mpp48 48 gpio, led(p2), ge0(txd2), ge1(txd2)
mpp49 49 gpio, led(p3), ge0(txd3), ge1(txd3)
mpp50 50 gpio, led(c0), ge0(rxd0), ge1(rxd0)
mpp51 51 gpio, led(c1), ge0(rxd1), ge1(rxd1)
mpp52 52 gpio, led(c2), ge0(rxd2), ge1(rxd2)
mpp53 53 gpio, pcie1(rstoutn), ge0(rxd3), ge1(rxd3)
mpp54 54 gpio, pcie0(rstoutn), ge0(rxctl), ge1(rxctl)
mpp55 55 gpio, ge0(rxclk), ge1(rxclk)
mpp56 56 gpio, ge0(txclkout), ge1(txclkout)
mpp57 57 gpio, ge0(txctl), ge1(txctl)
mpp58 58 gpio, led(c0)
mpp59 59 gpio, led(c1)
mpp60 60 gpio, uart1(txd), led(c2)
mpp61 61 gpio, i2c1(sda), uart1(rxd), spi1(cs2), led(p0)
mpp62 62 gpio, i2c1(sck), led(p1)
mpp63 63 gpio, ptp(triggen), led(p2)
mpp64 64 gpio, dram(vttctrl), led(p3)
mpp65 65 gpio, sata1(prsnt)
mpp66 66 gpio, ptp(eventreq), spi1(cs3)
Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt 0 → 100644
View file @ d64b3932
* Marvell Armada 380/385 SoC pinctrl driver for mpp
Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
part and usage.
Required properties:
- compatible: "marvell,88f6810-pinctrl", "marvell,88f6820-pinctrl" or
"marvell,88f6828-pinctrl" depending on the specific variant of the
SoC being used.
- reg: register specifier of MPP registers
Available mpp pins/groups and functions:
Note: brackets (x) are not part of the mpp name for marvell,function and given
only for more detailed description in this document.
name pins functions
================================================================================
mpp0 0 gpio, ua0(rxd)
mpp1 1 gpio, ua0(txd)
mpp2 2 gpio, i2c0(sck)
mpp3 3 gpio, i2c0(sda)
mpp4 4 gpio, ge(mdc), ua1(txd), ua0(rts)
mpp5 5 gpio, ge(mdio), ua1(rxd), ua0(cts)
mpp6 6 gpio, ge0(txclkout), ge0(crs), dev(cs3)
mpp7 7 gpio, ge0(txd0), dev(ad9)
mpp8 8 gpio, ge0(txd1), dev(ad10)
mpp9 9 gpio, ge0(txd2), dev(ad11)
mpp10 10 gpio, ge0(txd3), dev(ad12)
mpp11 11 gpio, ge0(txctl), dev(ad13)
mpp12 12 gpio, ge0(rxd0), pcie0(rstout), pcie1(rstout) [1], spi0(cs1), dev(ad14)
mpp13 13 gpio, ge0(rxd1), pcie0(clkreq), pcie1(clkreq) [1], spi0(cs2), dev(ad15)
mpp14 14 gpio, ge0(rxd2), ptp(clk), m(vtt_ctrl), spi0(cs3), dev(wen1)
mpp15 15 gpio, ge0(rxd3), ge(mdc slave), pcie0(rstout), spi0(mosi), pcie1(rstout) [1]
mpp16 16 gpio, ge0(rxctl), ge(mdio slave), m(decc_err), spi0(miso), pcie0(clkreq)
mpp17 17 gpio, ge0(rxclk), ptp(clk), ua1(rxd), spi0(sck), sata1(prsnt)
mpp18 18 gpio, ge0(rxerr), ptp(trig_gen), ua1(txd), spi0(cs0), pcie1(rstout) [1]
mpp19 19 gpio, ge0(col), ptp(event_req), pcie0(clkreq), sata1(prsnt), ua0(cts)
mpp20 20 gpio, ge0(txclk), ptp(clk), pcie1(rstout) [1], sata0(prsnt), ua0(rts)
mpp21 21 gpio, spi0(cs1), ge1(rxd0), sata0(prsnt), sd0(cmd), dev(bootcs)
mpp22 22 gpio, spi0(mosi), dev(ad0)
mpp23 23 gpio, spi0(sck), dev(ad2)
mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd0(d4), dev(ready)
mpp25 25 gpio, spi0(cs0), ua0(rts), ua1(txd), sd0(d5), dev(cs0)
mpp26 26 gpio, spi0(cs2), i2c1(sck), sd0(d6), dev(cs1)
mpp27 27 gpio, spi0(cs3), ge1(txclkout), i2c1(sda), sd0(d7), dev(cs2)
mpp28 28 gpio, ge1(txd0), sd0(clk), dev(ad5)
mpp29 29 gpio, ge1(txd1), dev(ale0)
mpp30 30 gpio, ge1(txd2), dev(oen)
mpp31 31 gpio, ge1(txd3), dev(ale1)
mpp32 32 gpio, ge1(txctl), dev(wen0)
mpp33 33 gpio, m(decc_err), dev(ad3)
mpp34 34 gpio, dev(ad1)
mpp35 35 gpio, ref(clk_out1), dev(a1)
mpp36 36 gpio, ptp(trig_gen), dev(a0)
mpp37 37 gpio, ptp(clk), ge1(rxclk), sd0(d3), dev(ad8)
mpp38 38 gpio, ptp(event_req), ge1(rxd1), ref(clk_out0), sd0(d0), dev(ad4)
mpp39 39 gpio, i2c1(sck), ge1(rxd2), ua0(cts), sd0(d1), dev(a2)
mpp40 40 gpio, i2c1(sda), ge1(rxd3), ua0(rts), sd0(d2), dev(ad6)
mpp41 41 gpio, ua1(rxd), ge1(rxctl), ua0(cts), spi1(cs3), dev(burst/last)
mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7)
mpp43 43 gpio, pcie0(clkreq), m(vtt_ctrl), m(decc_err), pcie0(rstout), dev(clkout)
mpp44 44 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [3], pcie0(rstout)
mpp45 45 gpio, ref(clk_out0), pcie0(rstout), pcie1(rstout) [1], pcie2(rstout), pcie3(rstout)
mpp46 46 gpio, ref(clk_out1), pcie0(rstout), pcie1(rstout) [1], pcie2(rstout), pcie3(rstout)
mpp47 47 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], spi1(cs2), sata3(prsnt) [2]
mpp48 48 gpio, sata0(prsnt), m(vtt_ctrl), tdm2c(pclk), audio(mclk), sd0(d4)
mpp49 49 gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm2c(fsync), audio(lrclk), sd0(d5)
mpp50 50 gpio, pcie0(rstout), pcie1(rstout) [1], tdm2c(drx), audio(extclk), sd0(cmd)
mpp51 51 gpio, tdm2c(dtx), audio(sdo), m(decc_err)
mpp52 52 gpio, pcie0(rstout), pcie1(rstout) [1], tdm2c(intn), audio(sdi), sd0(d6)
mpp53 53 gpio, sata1(prsnt), sata0(prsnt), tdm2c(rstn), audio(bclk), sd0(d7)
mpp54 54 gpio, sata0(prsnt), sata1(prsnt), pcie0(rstout), pcie1(rstout) [1], sd0(d3)
mpp55 55 gpio, ua1(cts), ge(mdio), pcie1(clkreq) [1], spi1(cs1), sd0(d0)
mpp56 56 gpio, ua1(rts), ge(mdc), m(decc_err), spi1(mosi)
mpp57 57 gpio, spi1(sck), sd0(clk)
mpp58 58 gpio, pcie1(clkreq) [1], i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1)
mpp59 59 gpio, pcie0(rstout), i2c1(sda), pcie1(rstout) [1], spi1(cs0), sd0(d2)
[1]: only available on 88F6820 and 88F6828
[2]: only available on 88F6828
Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
View file @ d64b3932
......@@ -6,6 +6,7 @@ part and usage.
Required properties:
- compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl",
"marvell,mv78460-pinctrl"
- reg: register specifier of MPP registers
This driver supports all Armada XP variants, i.e. mv78230, mv78260, and mv78460.
......
Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
View file @ d64b3932
......@@ -6,6 +6,7 @@ part and usage.
Required properties:
- compatible: "marvell,dove-pinctrl"
- clocks: (optional) phandle of pdma clock
- reg: register specifiers of MPP, MPP4, and PMU MPP registers
Available mpp pins/groups and functions:
Note: brackets (x) are not part of the mpp name for marvell,function and given
......
Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
View file @ d64b3932
......@@ -8,6 +8,7 @@ Required properties:
"marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
"marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl"
"marvell,98dx4122-pinctrl"
- reg: register specifier of MPP registers
This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628x.
It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs.
......
Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
View file @ d64b3932
......@@ -37,7 +37,7 @@ uart1: serial@12100 {
pinctrl: pinctrl@d0200 {
compatible = "marvell,dove-pinctrl";
reg = <0xd0200 0x20>;
reg = <0xd0200 0x14>, <0xd0440 0x04>, <0xd802c 0x08>;
pmx_uart1_sw: pmx-uart1-sw {
marvell,pins = "mpp_uart1";
......
Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
View file @ d64b3932
......@@ -63,6 +63,13 @@ Optional properties:
/* input, enable bits, disable bits, mask */
pinctrl-single,input-schmitt-enable = <0x30 0x40 0 0x70>;
- pinctrl-single,low-power-mode : array of value that are used to configure
low power mode of this pin. For some silicons, the low power mode will
control the output of the pin when the pad including the pin enter low
power mode.
/* low power mode value, mask */
pinctrl-single,low-power-mode = <0x288 0x388>;
- pinctrl-single,gpio-range : list of value that are used to configure a GPIO
range. They're value of subnode phandle, pin base in pinctrl device, pin
number in this range, GPIO function value of this GPIO range.
......
Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt
View file @ d64b3932
......@@ -11,18 +11,68 @@ Pull Up (PU) are driven by the related PIO block.
ST pinctrl driver controls PIO multiplexing block and also interacts with
gpio driver to configure a pin.
Required properties: (PIO multiplexing block)
GPIO bank can have one of the two possible types of interrupt-wirings.
First type is via irqmux, single interrupt is used by multiple gpio banks. This
reduces number of overall interrupts numbers required. All these banks belong to
a single pincontroller.
_________
| |----> [gpio-bank (n) ]
| |----> [gpio-bank (n + 1)]
[irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
| |----> [gpio-bank (... )]
|_________|----> [gpio-bank (n + 7)]
Second type has a dedicated interrupt per gpio bank.
[irqN]----> [gpio-bank (n)]
Pin controller node:
Required properties:
- compatible : should be "st,<SOC>-<pio-block>-pinctrl"
like st,stih415-sbc-pinctrl, st,stih415-front-pinctrl and so on.
- gpio-controller : Indicates this device is a GPIO controller
- #gpio-cells : Should be one. The first cell is the pin number.
- st,syscfg : Should be a phandle of the syscfg node.
- st,retime-pin-mask : Should be mask to specify which pins can be retimed.
If the property is not present, it is assumed that all the pins in the
bank are capable of retiming. Retiming is mainly used to improve the
IO timing margins of external synchronous interfaces.
- st,bank-name : Should be a name string for this bank as
specified in datasheet.
- st,syscfg : Should be a phandle of the syscfg node.
- ranges : defines mapping between pin controller node (parent) to gpio-bank
node (children).
Optional properties:
- interrupts : Interrupt number of the irqmux. If the interrupt is shared
with other gpio banks via irqmux.
a irqline and gpio banks.
- reg : irqmux memory resource. If irqmux is present.
- reg-names : irqmux resource should be named as "irqmux".
GPIO controller/bank node.
Required properties:
- gpio-controller : Indicates this device is a GPIO controller
- #gpio-cells : Should be one. The first cell is the pin number.
- st,bank-name : Should be a name string for this bank as specified in
datasheet.
Optional properties:
- interrupts : Interrupt number for this gpio bank. If there is a dedicated
interrupt wired up for this gpio bank.
- interrupt-controller : Indicates this device is a interrupt controller. GPIO
bank can be an interrupt controller iff one of the interrupt type either via
irqmux or a dedicated interrupt per bank is specified.
- #interrupt-cells: the value of this property should be 2.
- First Cell: represents the external gpio interrupt number local to the
gpio interrupt space of the controller.
- Second Cell: flags to identify the type of the interrupt
- 1 = rising edge triggered
- 2 = falling edge triggered
- 3 = rising and falling edge triggered
- 4 = high level triggered
- 8 = low level triggered
for related macros look in:
include/dt-bindings/interrupt-controller/irq.h
Example:
pin-controller-sbc {
......@@ -30,10 +80,17 @@ Example:
#size-cells = <1>;
compatible = "st,stih415-sbc-pinctrl";
st,syscfg = <&syscfg_sbc>;
reg = <0xfe61f080 0x4>;
reg-names = "irqmux";
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
interrupts-names = "irqmux";
ranges = <0 0xfe610000 0x5000>;
PIO0: gpio@fe610000 {
gpio-controller;
#gpio-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0 0x100>;
st,bank-name = "PIO0";
};
......@@ -105,6 +162,10 @@ pin-controller {
sdhci0:sdhci@fe810000{
...
interrupt-parent = <&PIO3>;
#interrupt-cells = <2>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; /* Interrupt line via PIO3-3 */
interrupts-names = "card-detect";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc>;
};
Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.txt
View file @ d64b3932
Qualcomm MSM8974 TLMM block
Required properties:
- compatible: "qcom,msm8x74-pinctrl"
- compatible: "qcom,msm8974-pinctrl"
- reg: Should be the base address and length of the TLMM block.
- interrupts: Should be the parent IRQ of the TLMM block.
- interrupt-controller: Marks the device node as an interrupt controller.
......@@ -42,14 +42,14 @@ Non-empty subnodes must specify the 'pins' property.
Note that not all properties are valid for all pins.
Valid values for qcom,pins are:
Valid values for pins are:
gpio0-gpio145
Supports mux, bias and drive-strength
sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data
Supports bias and drive-strength
Valid values for qcom,function are:
Valid values for function are:
blsp_i2c2, blsp_i2c6, blsp_i2c11, blsp_spi1, blsp_uart2, blsp_uart8, slimbus
(Note that this is not yet the complete list of functions)
......@@ -73,18 +73,18 @@ Example:
uart2_default: uart2_default {
mux {
qcom,pins = "gpio4", "gpio5";
qcom,function = "blsp_uart2";
pins = "gpio4", "gpio5";
function = "blsp_uart2";
};
tx {
qcom,pins = "gpio4";
pins = "gpio4";
drive-strength = <4>;
bias-disable;
};
rx {
qcom,pins = "gpio5";
pins = "gpio5";
drive-strength = <2>;
bias-pull-up;
};
......
Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
View file @ d64b3932
......@@ -16,6 +16,7 @@ Required Properties:
- "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller.
- "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller.
- "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller.
- "samsung,exynos5260-pinctrl": for Exynos5260 compatible pin-controller.
- "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller.
- reg: Base address of the pin controller hardware module and length of
......
arch/arm/boot/dts/r8a7791.dtsi
View file @ d64b3932
......@@ -429,7 +429,7 @@ R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
>;
clock-output-names =
"scifa2", "scifa1", "scifa0", "misof2", "scifb0",
"scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
"scifb1", "msiof1", "scifb2";
};
mstp3_clks: mstp3_clks@e615013c {
......
arch/blackfin/include/asm/irq.h
View file @ d64b3932
......@@ -20,15 +20,6 @@
/* SYS_IRQS and NR_IRQS are defined in <mach-bf5xx/irq.h> */
#include <mach/irq.h>
/*
* pm save bfin pint registers
*/
struct adi_pm_pint_save {
u32 assign;
u32 edge_set;
u32 invert_set;
};
#if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE)
# define NOP_PAD_ANOMALY_05000244 "nop; nop;"
#else
......
drivers/pinctrl/Kconfig
View file @ d64b3932
......@@ -224,7 +224,7 @@ config PINCTRL_MSM
config PINCTRL_MSM8X74
tristate "Qualcomm 8x74 pin controller driver"
depends on GPIOLIB && OF && OF_IRQ
depends on GPIOLIB && OF
select PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
......
drivers/pinctrl/devicetree.c
View file @ d64b3932
......@@ -186,7 +186,9 @@ int pinctrl_dt_to_map(struct pinctrl *p)
/* CONFIG_OF enabled, p->dev not instantiated from DT */
if (!np) {
dev_dbg(p->dev, "no of_node; not parsing pinctrl DT\n");
if (of_have_populated_dt())
dev_dbg(p->dev,
"no of_node; not parsing pinctrl DT\n");
return 0;
}
......
drivers/pinctrl/mvebu/Kconfig
View file @ d64b3932
......@@ -8,6 +8,7 @@ config PINCTRL_MVEBU
config PINCTRL_DOVE
bool
select PINCTRL_MVEBU
select MFD_SYSCON
config PINCTRL_KIRKWOOD
bool
......@@ -17,6 +18,14 @@ config PINCTRL_ARMADA_370
bool
select PINCTRL_MVEBU
config PINCTRL_ARMADA_375
bool
select PINCTRL_MVEBU
config PINCTRL_ARMADA_38X
bool
select PINCTRL_MVEBU
config PINCTRL_ARMADA_XP
bool
select PINCTRL_MVEBU
......
drivers/pinctrl/mvebu/Makefile
View file @ d64b3932
......@@ -2,4 +2,6 @@ obj-$(CONFIG_PINCTRL_MVEBU) += pinctrl-mvebu.o
obj-$(CONFIG_PINCTRL_DOVE) += pinctrl-dove.o
obj-$(CONFIG_PINCTRL_KIRKWOOD) += pinctrl-kirkwood.o
obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o
obj-$(CONFIG_PINCTRL_ARMADA_375) += pinctrl-armada-375.o
obj-$(CONFIG_PINCTRL_ARMADA_38X) += pinctrl-armada-38x.o
obj-$(CONFIG_PINCTRL_ARMADA_XP) += pinctrl-armada-xp.o
drivers/pinctrl/mvebu/pinctrl-armada-370.c
View file @ d64b3932
......@@ -23,6 +23,18 @@
#include "pinctrl-mvebu.h"
static void __iomem *mpp_base;
static int armada_370_mpp_ctrl_get(unsigned pid, unsigned long *config)
{
return default_mpp_ctrl_get(mpp_base, pid, config);
}
static int armada_370_mpp_ctrl_set(unsigned pid, unsigned long config)
{
return default_mpp_ctrl_set(mpp_base, pid, config);
}
static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = {
MPP_MODE(0,
MPP_FUNCTION(0x0, "gpio", NULL),
......@@ -373,7 +385,7 @@ static struct of_device_id armada_370_pinctrl_of_match[] = {
};
static struct mvebu_mpp_ctrl mv88f6710_mpp_controls[] = {
MPP_REG_CTRL(0, 65),
MPP_FUNC_CTRL(0, 65, NULL, armada_370_mpp_ctrl),
};
static struct pinctrl_gpio_range mv88f6710_mpp_gpio_ranges[] = {
......@@ -385,6 +397,12 @@ static struct pinctrl_gpio_range mv88f6710_mpp_gpio_ranges[] = {
static int armada_370_pinctrl_probe(struct platform_device *pdev)
{
struct mvebu_pinctrl_soc_info *soc = &armada_370_pinctrl_info;
struct resource *res;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
mpp_base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(mpp_base))
return PTR_ERR(mpp_base);
soc->variant = 0; /* no variants for Armada 370 */
soc->controls = mv88f6710_mpp_controls;
......
drivers/pinctrl/mvebu/pinctrl-armada-375.c 0 → 100644
View file @ d64b3932
This diff is collapsed.
drivers/pinctrl/mvebu/pinctrl-armada-38x.c 0 → 100644
View file @ d64b3932
This diff is collapsed.
drivers/pinctrl/mvebu/pinctrl-armada-xp.c
View file @ d64b3932
......@@ -33,6 +33,18 @@
#include "pinctrl-mvebu.h"
static void __iomem *mpp_base;
static int armada_xp_mpp_ctrl_get(unsigned pid, unsigned long *config)
{
return default_mpp_ctrl_get(mpp_base, pid, config);
}
static int armada_xp_mpp_ctrl_set(unsigned pid, unsigned long config)
{
return default_mpp_ctrl_set(mpp_base, pid, config);
}
enum armada_xp_variant {
V_MV78230 = BIT(0),
V_MV78260 = BIT(1),
......@@ -366,7 +378,7 @@ static struct of_device_id armada_xp_pinctrl_of_match[] = {
};
static struct mvebu_mpp_ctrl mv78230_mpp_controls[] = {
MPP_REG_CTRL(0, 48),
MPP_FUNC_CTRL(0, 48, NULL, armada_xp_mpp_ctrl),
};
static struct pinctrl_gpio_range mv78230_mpp_gpio_ranges[] = {
......@@ -375,7 +387,7 @@ static struct pinctrl_gpio_range mv78230_mpp_gpio_ranges[] = {
};
static struct mvebu_mpp_ctrl mv78260_mpp_controls[] = {
MPP_REG_CTRL(0, 66),
MPP_FUNC_CTRL(0, 66, NULL, armada_xp_mpp_ctrl),
};
static struct pinctrl_gpio_range mv78260_mpp_gpio_ranges[] = {
......@@ -385,7 +397,7 @@ static struct pinctrl_gpio_range mv78260_mpp_gpio_ranges[] = {
};
static struct mvebu_mpp_ctrl mv78460_mpp_controls[] = {
MPP_REG_CTRL(0, 66),
MPP_FUNC_CTRL(0, 66, NULL, armada_xp_mpp_ctrl),
};
static struct pinctrl_gpio_range mv78460_mpp_gpio_ranges[] = {
......@@ -399,10 +411,16 @@ static int armada_xp_pinctrl_probe(struct platform_device *pdev)
struct mvebu_pinctrl_soc_info *soc = &armada_xp_pinctrl_info;
const struct of_device_id *match =
of_match_device(armada_xp_pinctrl_of_match, &pdev->dev);
struct resource *res;
if (!match)
return -ENODEV;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
mpp_base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(mpp_base))
return PTR_ERR(mpp_base);
soc->variant = (unsigned) match->data & 0xff;
switch (soc->variant) {
......
drivers/pinctrl/mvebu/pinctrl-dove.c
View file @ d64b3932
This diff is collapsed.
drivers/pinctrl/mvebu/pinctrl-kirkwood.c
View file @ d64b3932
......@@ -21,6 +21,18 @@
#include "pinctrl-mvebu.h"
static void __iomem *mpp_base;
static int kirkwood_mpp_ctrl_get(unsigned pid, unsigned long *config)
{
return default_mpp_ctrl_get(mpp_base, pid, config);
}
static int kirkwood_mpp_ctrl_set(unsigned pid, unsigned long config)
{
return default_mpp_ctrl_set(mpp_base, pid, config);
}
#define V(f6180, f6190, f6192, f6281, f6282, dx4122) \
((f6180 << 0) | (f6190 << 1) | (f6192 << 2) | \
(f6281 << 3) | (f6282 << 4) | (dx4122 << 5))
......@@ -359,7 +371,7 @@ static struct mvebu_mpp_mode mv88f6xxx_mpp_modes[] = {
};
static struct mvebu_mpp_ctrl mv88f6180_mpp_controls[] = {
MPP_REG_CTRL(0, 29),
MPP_FUNC_CTRL(0, 29, NULL, kirkwood_mpp_ctrl),
};
static struct pinctrl_gpio_range mv88f6180_gpio_ranges[] = {
......@@ -367,7 +379,7 @@ static struct pinctrl_gpio_range mv88f6180_gpio_ranges[] = {
};
static struct mvebu_mpp_ctrl mv88f619x_mpp_controls[] = {
MPP_REG_CTRL(0, 35),
MPP_FUNC_CTRL(0, 35, NULL, kirkwood_mpp_ctrl),
};
static struct pinctrl_gpio_range mv88f619x_gpio_ranges[] = {
......@@ -376,7 +388,7 @@ static struct pinctrl_gpio_range mv88f619x_gpio_ranges[] = {
};
static struct mvebu_mpp_ctrl mv88f628x_mpp_controls[] = {
MPP_REG_CTRL(0, 49),
MPP_FUNC_CTRL(0, 49, NULL, kirkwood_mpp_ctrl),
};
static struct pinctrl_gpio_range mv88f628x_gpio_ranges[] = {
......@@ -456,9 +468,16 @@ static struct of_device_id kirkwood_pinctrl_of_match[] = {
static int kirkwood_pinctrl_probe(struct platform_device *pdev)
{
struct resource *res;
const struct of_device_id *match =
of_match_device(kirkwood_pinctrl_of_match, &pdev->dev);
pdev->dev.platform_data = (void *)match->data;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
mpp_base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(mpp_base))
return PTR_ERR(mpp_base);
return mvebu_pinctrl_probe(pdev);
}
......
drivers/pinctrl/mvebu/pinctrl-mvebu.c
View file @ d64b3932
......@@ -50,7 +50,6 @@ struct mvebu_pinctrl {
struct device *dev;
struct pinctrl_dev *pctldev;
struct pinctrl_desc desc;
void __iomem *base;
struct mvebu_pinctrl_group *groups;
unsigned num_groups;
struct mvebu_pinctrl_function *functions;
......@@ -138,43 +137,6 @@ static struct mvebu_pinctrl_function *mvebu_pinctrl_find_function_by_name(
return NULL;
}
/*
* Common mpp pin configuration registers on MVEBU are
* registers of eight 4-bit values for each mpp setting.
* Register offset and bit mask are calculated accordingly below.
*/
static int mvebu_common_mpp_get(struct mvebu_pinctrl *pctl,
struct mvebu_pinctrl_group *grp,
unsigned long *config)
{
unsigned pin = grp->gid;
unsigned off = (pin / MPPS_PER_REG) * MPP_BITS;
unsigned shift = (pin % MPPS_PER_REG) * MPP_BITS;
*config = readl(pctl->base + off);
*config >>= shift;
*config &= MPP_MASK;
return 0;
}
static int mvebu_common_mpp_set(struct mvebu_pinctrl *pctl,
struct mvebu_pinctrl_group *grp,
unsigned long config)
{
unsigned pin = grp->gid;
unsigned off = (pin / MPPS_PER_REG) * MPP_BITS;
unsigned shift = (pin % MPPS_PER_REG) * MPP_BITS;
unsigned long reg;
reg = readl(pctl->base + off);
reg &= ~(MPP_MASK << shift);
reg |= (config << shift);
writel(reg, pctl->base + off);
return 0;
}
static int mvebu_pinconf_group_get(struct pinctrl_dev *pctldev,
unsigned gid, unsigned long *config)
{
......@@ -184,10 +146,7 @@ static int mvebu_pinconf_group_get(struct pinctrl_dev *pctldev,
if (!grp->ctrl)
return -EINVAL;
if (grp->ctrl->mpp_get)
return grp->ctrl->mpp_get(grp->ctrl, config);
return mvebu_common_mpp_get(pctl, grp, config);
return grp->ctrl->mpp_get(grp->pins[0], config);
}
static int mvebu_pinconf_group_set(struct pinctrl_dev *pctldev,
......@@ -202,11 +161,7 @@ static int mvebu_pinconf_group_set(struct pinctrl_dev *pctldev,
return -EINVAL;
for (i = 0; i < num_configs; i++) {
if (grp->ctrl->mpp_set)
ret = grp->ctrl->mpp_set(grp->ctrl, configs[i]);
else
ret = mvebu_common_mpp_set(pctl, grp, configs[i]);
ret = grp->ctrl->mpp_set(grp->pins[0], configs[i]);
if (ret)
return ret;
} /* for each config */
......@@ -347,7 +302,7 @@ static int mvebu_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
return -EINVAL;
if (grp->ctrl->mpp_gpio_req)
return grp->ctrl->mpp_gpio_req(grp->ctrl, offset);
return grp->ctrl->mpp_gpio_req(offset);
setting = mvebu_pinctrl_find_gpio_setting(pctl, grp);
if (!setting)
......@@ -370,7 +325,7 @@ static int mvebu_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
return -EINVAL;
if (grp->ctrl->mpp_gpio_dir)
return grp->ctrl->mpp_gpio_dir(grp->ctrl, offset, input);
return grp->ctrl->mpp_gpio_dir(offset, input);
setting = mvebu_pinctrl_find_gpio_setting(pctl, grp);
if (!setting)
......@@ -593,11 +548,12 @@ static int mvebu_pinctrl_build_functions(struct platform_device *pdev,
int mvebu_pinctrl_probe(struct platform_device *pdev)
{
struct mvebu_pinctrl_soc_info *soc = dev_get_platdata(&pdev->dev);
struct resource *res;
struct mvebu_pinctrl *pctl;
void __iomem *base;
struct pinctrl_pin_desc *pdesc;
unsigned gid, n, k;
unsigned size, noname = 0;
char *noname_buf;
void *p;
int ret;
if (!soc || !soc->controls || !soc->modes) {
......@@ -605,11 +561,6 @@ int mvebu_pinctrl_probe(struct platform_device *pdev)
return -EINVAL;
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(base))
return PTR_ERR(base);
pctl = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pinctrl),
GFP_KERNEL);
if (!pctl) {
......@@ -623,7 +574,6 @@ int mvebu_pinctrl_probe(struct platform_device *pdev)
pctl->desc.pmxops = &mvebu_pinmux_ops;
pctl->desc.confops = &mvebu_pinconf_ops;
pctl->variant = soc->variant;
pctl->base = base;
pctl->dev = &pdev->dev;
platform_set_drvdata(pdev, pctl);
......@@ -633,33 +583,23 @@ int mvebu_pinctrl_probe(struct platform_device *pdev)
pctl->desc.npins = 0;
for (n = 0; n < soc->ncontrols; n++) {
struct mvebu_mpp_ctrl *ctrl = &soc->controls[n];
char *names;
pctl->desc.npins += ctrl->npins;
/* initial control pins */
/* initialize control's pins[] array */
for (k = 0; k < ctrl->npins; k++)
ctrl->pins[k] = ctrl->pid + k;
/* special soc specific control */
if (ctrl->mpp_get || ctrl->mpp_set) {
if (!ctrl->name || !ctrl->mpp_get || !ctrl->mpp_set) {
dev_err(&pdev->dev, "wrong soc control info\n");
return -EINVAL;
}
/*
* We allow to pass controls with NULL name that we treat
* as a range of one-pin groups with generic mvebu register
* controls.
*/
if (!ctrl->name) {
pctl->num_groups += ctrl->npins;
noname += ctrl->npins;
} else {
pctl->num_groups += 1;
continue;
}
/* generic mvebu register control */
names = devm_kzalloc(&pdev->dev, ctrl->npins * 8, GFP_KERNEL);
if (!names) {
dev_err(&pdev->dev, "failed to alloc mpp names\n");
return -ENOMEM;
}
for (k = 0; k < ctrl->npins; k++)
sprintf(names + 8*k, "mpp%d", ctrl->pid+k);
ctrl->name = names;
pctl->num_groups += ctrl->npins;
}
pdesc = devm_kzalloc(&pdev->dev, pctl->desc.npins *
......@@ -673,12 +613,17 @@ int mvebu_pinctrl_probe(struct platform_device *pdev)
pdesc[n].number = n;
pctl->desc.pins = pdesc;
pctl->groups = devm_kzalloc(&pdev->dev, pctl->num_groups *
sizeof(struct mvebu_pinctrl_group), GFP_KERNEL);
if (!pctl->groups) {
dev_err(&pdev->dev, "failed to alloc pinctrl groups\n");
/*
* allocate groups and name buffers for unnamed groups.
*/
size = pctl->num_groups * sizeof(*pctl->groups) + noname * 8;
p = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
if (!p) {
dev_err(&pdev->dev, "failed to alloc group data\n");
return -ENOMEM;
}
pctl->groups = p;
noname_buf = p + pctl->num_groups * sizeof(*pctl->groups);
/* assign mpp controls to groups */
gid = 0;
......@@ -690,17 +635,26 @@ int mvebu_pinctrl_probe(struct platform_device *pdev)
pctl->groups[gid].pins = ctrl->pins;
pctl->groups[gid].npins = ctrl->npins;
/* generic mvebu register control maps to a number of groups */
if (!ctrl->mpp_get && !ctrl->mpp_set) {
/*
* We treat unnamed controls as a range of one-pin groups
* with generic mvebu register controls. Use one group for
* each in this range and assign a default group name.
*/
if (!ctrl->name) {
pctl->groups[gid].name = noname_buf;
pctl->groups[gid].npins = 1;
sprintf(noname_buf, "mpp%d", ctrl->pid+0);
noname_buf += 8;
for (k = 1; k < ctrl->npins; k++) {
gid++;
pctl->groups[gid].gid = gid;
pctl->groups[gid].ctrl = ctrl;
pctl->groups[gid].name = &ctrl->name[8*k];
pctl->groups[gid].name = noname_buf;
pctl->groups[gid].pins = &ctrl->pins[k];
pctl->groups[gid].npins = 1;
sprintf(noname_buf, "mpp%d", ctrl->pid+k);
noname_buf += 8;
}
}
gid++;
......
drivers/pinctrl/mvebu/pinctrl-mvebu.h
View file @ d64b3932
......@@ -28,20 +28,19 @@
* between two or more different settings, e.g. assign mpp pin 13 to
* uart1 or sata.
*
* If optional mpp_get/_set functions are set these are used to get/set
* a specific mode. Otherwise it is assumed that the mpp control is based
* on 4-bit groups in subsequent registers. The optional mpp_gpio_req/_dir
* functions can be used to allow pin settings with varying gpio pins.
* The mpp_get/_set functions are mandatory and are used to get/set a
* specific mode. The optional mpp_gpio_req/_dir functions can be used
* to allow pin settings with varying gpio pins.
*/
struct mvebu_mpp_ctrl {
const char *name;
u8 pid;
u8 npins;
unsigned *pins;
int (*mpp_get)(struct mvebu_mpp_ctrl *ctrl, unsigned long *config);
int (*mpp_set)(struct mvebu_mpp_ctrl *ctrl, unsigned long config);
int (*mpp_gpio_req)(struct mvebu_mpp_ctrl *ctrl, u8 pid);
int (*mpp_gpio_dir)(struct mvebu_mpp_ctrl *ctrl, u8 pid, bool input);
int (*mpp_get)(unsigned pid, unsigned long *config);
int (*mpp_set)(unsigned pid, unsigned long config);
int (*mpp_gpio_req)(unsigned pid);
int (*mpp_gpio_dir)(unsigned pid, bool input);
};
/**
......@@ -114,18 +113,6 @@ struct mvebu_pinctrl_soc_info {
int ngpioranges;
};
#define MPP_REG_CTRL(_idl, _idh) \
{ \
.name = NULL, \
.pid = _idl, \
.npins = _idh - _idl + 1, \
.pins = (unsigned[_idh - _idl + 1]) { }, \
.mpp_get = NULL, \
.mpp_set = NULL, \
.mpp_gpio_req = NULL, \
.mpp_gpio_dir = NULL, \
}
#define MPP_FUNC_CTRL(_idl, _idh, _name, _func) \
{ \
.name = _name, \
......@@ -186,6 +173,34 @@ struct mvebu_pinctrl_soc_info {
.npins = _npins, \
}
#define MVEBU_MPPS_PER_REG 8
#define MVEBU_MPP_BITS 4
#define MVEBU_MPP_MASK 0xf
static inline int default_mpp_ctrl_get(void __iomem *base, unsigned int pid,
unsigned long *config)
{
unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
*config = (readl(base + off) >> shift) & MVEBU_MPP_MASK;
return 0;
}
static inline int default_mpp_ctrl_set(void __iomem *base, unsigned int pid,
unsigned long config)
{
unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
unsigned long reg;
reg = readl(base + off) & ~(MVEBU_MPP_MASK << shift);
writel(reg | (config << shift), base + off);
return 0;
}
int mvebu_pinctrl_probe(struct platform_device *pdev);
int mvebu_pinctrl_remove(struct platform_device *pdev);
......
drivers/pinctrl/pinctrl-adi2-bf54x.c
View file @ d64b3932
......@@ -309,39 +309,6 @@ static const unsigned keys_8x8_pins[] = {
GPIO_PE4, GPIO_PE5, GPIO_PE6, GPIO_PE7,
};
static const struct adi_pin_group adi_pin_groups[] = {
ADI_PIN_GROUP("uart0grp", uart0_pins),
ADI_PIN_GROUP("uart1grp", uart1_pins),
ADI_PIN_GROUP("uart1ctsrtsgrp", uart1_ctsrts_pins),
ADI_PIN_GROUP("uart2grp", uart2_pins),
ADI_PIN_GROUP("uart3grp", uart3_pins),
ADI_PIN_GROUP("uart3ctsrtsgrp", uart3_ctsrts_pins),
ADI_PIN_GROUP("rsi0grp", rsi0_pins),
ADI_PIN_GROUP("spi0grp", spi0_pins),
ADI_PIN_GROUP("spi1grp", spi1_pins),
ADI_PIN_GROUP("twi0grp", twi0_pins),
ADI_PIN_GROUP("twi1grp", twi1_pins),
ADI_PIN_GROUP("rotarygrp", rotary_pins),
ADI_PIN_GROUP("can0grp", can0_pins),
ADI_PIN_GROUP("can1grp", can1_pins),
ADI_PIN_GROUP("smc0grp", smc0_pins),
ADI_PIN_GROUP("sport0grp", sport0_pins),
ADI_PIN_GROUP("sport1grp", sport1_pins),
ADI_PIN_GROUP("sport2grp", sport2_pins),
ADI_PIN_GROUP("sport3grp", sport3_pins),
ADI_PIN_GROUP("ppi0_8bgrp", ppi0_8b_pins),
ADI_PIN_GROUP("ppi0_16bgrp", ppi0_16b_pins),
ADI_PIN_GROUP("ppi0_24bgrp", ppi0_24b_pins),
ADI_PIN_GROUP("ppi1_8bgrp", ppi1_8b_pins),
ADI_PIN_GROUP("ppi1_16bgrp", ppi1_16b_pins),
ADI_PIN_GROUP("ppi2_8bgrp", ppi2_8b_pins),
ADI_PIN_GROUP("atapigrp", atapi_pins),
ADI_PIN_GROUP("atapialtergrp", atapi_alter_pins),
ADI_PIN_GROUP("nfc0grp", nfc0_pins),
ADI_PIN_GROUP("keys_4x4grp", keys_4x4_pins),
ADI_PIN_GROUP("keys_8x8grp", keys_8x8_pins),
};
static const unsigned short uart0_mux[] = {
P_UART0_TX, P_UART0_RX,
0
......@@ -513,6 +480,39 @@ static const unsigned short keys_8x8_mux[] = {
0
};
static const struct adi_pin_group adi_pin_groups[] = {
ADI_PIN_GROUP("uart0grp", uart0_pins, uart0_mux),
ADI_PIN_GROUP("uart1grp", uart1_pins, uart1_mux),
ADI_PIN_GROUP("uart1ctsrtsgrp", uart1_ctsrts_pins, uart1_ctsrts_mux),
ADI_PIN_GROUP("uart2grp", uart2_pins, uart2_mux),
ADI_PIN_GROUP("uart3grp", uart3_pins, uart3_mux),
ADI_PIN_GROUP("uart3ctsrtsgrp", uart3_ctsrts_pins, uart3_ctsrts_mux),
ADI_PIN_GROUP("rsi0grp", rsi0_pins, rsi0_mux),
ADI_PIN_GROUP("spi0grp", spi0_pins, spi0_mux),
ADI_PIN_GROUP("spi1grp", spi1_pins, spi1_mux),
ADI_PIN_GROUP("twi0grp", twi0_pins, twi0_mux),
ADI_PIN_GROUP("twi1grp", twi1_pins, twi1_mux),
ADI_PIN_GROUP("rotarygrp", rotary_pins, rotary_mux),
ADI_PIN_GROUP("can0grp", can0_pins, can0_mux),
ADI_PIN_GROUP("can1grp", can1_pins, can1_mux),
ADI_PIN_GROUP("smc0grp", smc0_pins, smc0_mux),
ADI_PIN_GROUP("sport0grp", sport0_pins, sport0_mux),
ADI_PIN_GROUP("sport1grp", sport1_pins, sport1_mux),
ADI_PIN_GROUP("sport2grp", sport2_pins, sport2_mux),
ADI_PIN_GROUP("sport3grp", sport3_pins, sport3_mux),
ADI_PIN_GROUP("ppi0_8bgrp", ppi0_8b_pins, ppi0_8b_mux),
ADI_PIN_GROUP("ppi0_16bgrp", ppi0_16b_pins, ppi0_16b_mux),
ADI_PIN_GROUP("ppi0_24bgrp", ppi0_24b_pins, ppi0_24b_mux),
ADI_PIN_GROUP("ppi1_8bgrp", ppi1_8b_pins, ppi1_8b_mux),
ADI_PIN_GROUP("ppi1_16bgrp", ppi1_16b_pins, ppi1_16b_mux),
ADI_PIN_GROUP("ppi2_8bgrp", ppi2_8b_pins, ppi2_8b_mux),
ADI_PIN_GROUP("atapigrp", atapi_pins, atapi_mux),
ADI_PIN_GROUP("atapialtergrp", atapi_alter_pins, atapi_alter_mux),
ADI_PIN_GROUP("nfc0grp", nfc0_pins, nfc0_mux),
ADI_PIN_GROUP("keys_4x4grp", keys_4x4_pins, keys_4x4_mux),
ADI_PIN_GROUP("keys_8x8grp", keys_8x8_pins, keys_8x8_mux),
};
static const char * const uart0grp[] = { "uart0grp" };
static const char * const uart1grp[] = { "uart1grp" };
static const char * const uart1ctsrtsgrp[] = { "uart1ctsrtsgrp" };
......@@ -532,49 +532,45 @@ static const char * const sport0grp[] = { "sport0grp" };
static const char * const sport1grp[] = { "sport1grp" };
static const char * const sport2grp[] = { "sport2grp" };
static const char * const sport3grp[] = { "sport3grp" };
static const char * const ppi0_8bgrp[] = { "ppi0_8bgrp" };
static const char * const ppi0_16bgrp[] = { "ppi0_16bgrp" };
static const char * const ppi0_24bgrp[] = { "ppi0_24bgrp" };
static const char * const ppi1_8bgrp[] = { "ppi1_8bgrp" };
static const char * const ppi1_16bgrp[] = { "ppi1_16bgrp" };
static const char * const ppi2_8bgrp[] = { "ppi2_8bgrp" };
static const char * const ppi0grp[] = { "ppi0_8bgrp",
"ppi0_16bgrp",
"ppi0_24bgrp" };
static const char * const ppi1grp[] = { "ppi1_8bgrp",
"ppi1_16bgrp" };
static const char * const ppi2grp[] = { "ppi2_8bgrp" };
static const char * const atapigrp[] = { "atapigrp" };
static const char * const atapialtergrp[] = { "atapialtergrp" };
static const char * const nfc0grp[] = { "nfc0grp" };
static const char * const keys_4x4grp[] = { "keys_4x4grp" };
static const char * const keys_8x8grp[] = { "keys_8x8grp" };
static const char * const keysgrp[] = { "keys_4x4grp",
"keys_8x8grp" };
static const struct adi_pmx_func adi_pmx_functions[] = {
ADI_PMX_FUNCTION("uart0", uart0grp, uart0_mux),
ADI_PMX_FUNCTION("uart1", uart1grp, uart1_mux),
ADI_PMX_FUNCTION("uart1_ctsrts", uart1ctsrtsgrp, uart1_ctsrts_mux),
ADI_PMX_FUNCTION("uart2", uart2grp, uart2_mux),
ADI_PMX_FUNCTION("uart3", uart3grp, uart3_mux),
ADI_PMX_FUNCTION("uart3_ctsrts", uart3ctsrtsgrp, uart3_ctsrts_mux),
ADI_PMX_FUNCTION("rsi0", rsi0grp, rsi0_mux),
ADI_PMX_FUNCTION("spi0", spi0grp, spi0_mux),
ADI_PMX_FUNCTION("spi1", spi1grp, spi1_mux),
ADI_PMX_FUNCTION("twi0", twi0grp, twi0_mux),
ADI_PMX_FUNCTION("twi1", twi1grp, twi1_mux),
ADI_PMX_FUNCTION("rotary", rotarygrp, rotary_mux),
ADI_PMX_FUNCTION("can0", can0grp, can0_mux),
ADI_PMX_FUNCTION("can1", can1grp, can1_mux),
ADI_PMX_FUNCTION("smc0", smc0grp, smc0_mux),
ADI_PMX_FUNCTION("sport0", sport0grp, sport0_mux),
ADI_PMX_FUNCTION("sport1", sport1grp, sport1_mux),
ADI_PMX_FUNCTION("sport2", sport2grp, sport2_mux),
ADI_PMX_FUNCTION("sport3", sport3grp, sport3_mux),
ADI_PMX_FUNCTION("ppi0_8b", ppi0_8bgrp, ppi0_8b_mux),
ADI_PMX_FUNCTION("ppi0_16b", ppi0_16bgrp, ppi0_16b_mux),
ADI_PMX_FUNCTION("ppi0_24b", ppi0_24bgrp, ppi0_24b_mux),
ADI_PMX_FUNCTION("ppi1_8b", ppi1_8bgrp, ppi1_8b_mux),
ADI_PMX_FUNCTION("ppi1_16b", ppi1_16bgrp, ppi1_16b_mux),
ADI_PMX_FUNCTION("ppi2_8b", ppi2_8bgrp, ppi2_8b_mux),
ADI_PMX_FUNCTION("atapi", atapigrp, atapi_mux),
ADI_PMX_FUNCTION("atapi_alter", atapialtergrp, atapi_alter_mux),
ADI_PMX_FUNCTION("nfc0", nfc0grp, nfc0_mux),
ADI_PMX_FUNCTION("keys_4x4", keys_4x4grp, keys_4x4_mux),
ADI_PMX_FUNCTION("keys_8x8", keys_8x8grp, keys_8x8_mux),
ADI_PMX_FUNCTION("uart0", uart0grp),
ADI_PMX_FUNCTION("uart1", uart1grp),
ADI_PMX_FUNCTION("uart1_ctsrts", uart1ctsrtsgrp),
ADI_PMX_FUNCTION("uart2", uart2grp),
ADI_PMX_FUNCTION("uart3", uart3grp),
ADI_PMX_FUNCTION("uart3_ctsrts", uart3ctsrtsgrp),
ADI_PMX_FUNCTION("rsi0", rsi0grp),
ADI_PMX_FUNCTION("spi0", spi0grp),
ADI_PMX_FUNCTION("spi1", spi1grp),
ADI_PMX_FUNCTION("twi0", twi0grp),
ADI_PMX_FUNCTION("twi1", twi1grp),
ADI_PMX_FUNCTION("rotary", rotarygrp),
ADI_PMX_FUNCTION("can0", can0grp),
ADI_PMX_FUNCTION("can1", can1grp),
ADI_PMX_FUNCTION("smc0", smc0grp),
ADI_PMX_FUNCTION("sport0", sport0grp),
ADI_PMX_FUNCTION("sport1", sport1grp),
ADI_PMX_FUNCTION("sport2", sport2grp),
ADI_PMX_FUNCTION("sport3", sport3grp),
ADI_PMX_FUNCTION("ppi0", ppi0grp),
ADI_PMX_FUNCTION("ppi1", ppi1grp),
ADI_PMX_FUNCTION("ppi2", ppi2grp),
ADI_PMX_FUNCTION("atapi", atapigrp),
ADI_PMX_FUNCTION("atapi_alter", atapialtergrp),
ADI_PMX_FUNCTION("nfc0", nfc0grp),
ADI_PMX_FUNCTION("keys", keysgrp),
};
static const struct adi_pinctrl_soc_data adi_bf54x_soc = {
......
drivers/pinctrl/pinctrl-adi2-bf60x.c
View file @ d64b3932
......@@ -259,37 +259,6 @@ static const unsigned lp3_pins[] = {
GPIO_PF12, GPIO_PF13, GPIO_PF14, GPIO_PF15,
};
static const struct adi_pin_group adi_pin_groups[] = {
ADI_PIN_GROUP("uart0grp", uart0_pins),
ADI_PIN_GROUP("uart0ctsrtsgrp", uart0_ctsrts_pins),
ADI_PIN_GROUP("uart1grp", uart1_pins),
ADI_PIN_GROUP("uart1ctsrtsgrp", uart1_ctsrts_pins),
ADI_PIN_GROUP("rsi0grp", rsi0_pins),
ADI_PIN_GROUP("eth0grp", eth0_pins),
ADI_PIN_GROUP("eth1grp", eth1_pins),
ADI_PIN_GROUP("spi0grp", spi0_pins),
ADI_PIN_GROUP("spi1grp", spi1_pins),
ADI_PIN_GROUP("twi0grp", twi0_pins),
ADI_PIN_GROUP("twi1grp", twi1_pins),
ADI_PIN_GROUP("rotarygrp", rotary_pins),
ADI_PIN_GROUP("can0grp", can0_pins),
ADI_PIN_GROUP("smc0grp", smc0_pins),
ADI_PIN_GROUP("sport0grp", sport0_pins),
ADI_PIN_GROUP("sport1grp", sport1_pins),
ADI_PIN_GROUP("sport2grp", sport2_pins),
ADI_PIN_GROUP("ppi0_8bgrp", ppi0_8b_pins),
ADI_PIN_GROUP("ppi0_16bgrp", ppi0_16b_pins),
ADI_PIN_GROUP("ppi0_24bgrp", ppi0_24b_pins),
ADI_PIN_GROUP("ppi1_8bgrp", ppi1_8b_pins),
ADI_PIN_GROUP("ppi1_16bgrp", ppi1_16b_pins),
ADI_PIN_GROUP("ppi2_8bgrp", ppi2_8b_pins),
ADI_PIN_GROUP("ppi2_16bgrp", ppi2_16b_pins),
ADI_PIN_GROUP("lp0grp", lp0_pins),
ADI_PIN_GROUP("lp1grp", lp1_pins),
ADI_PIN_GROUP("lp2grp", lp2_pins),
ADI_PIN_GROUP("lp3grp", lp3_pins),
};
static const unsigned short uart0_mux[] = {
P_UART0_TX, P_UART0_RX,
0
......@@ -446,6 +415,37 @@ static const unsigned short lp3_mux[] = {
0
};
static const struct adi_pin_group adi_pin_groups[] = {
ADI_PIN_GROUP("uart0grp", uart0_pins, uart0_mux),
ADI_PIN_GROUP("uart0ctsrtsgrp", uart0_ctsrts_pins, uart0_ctsrts_mux),
ADI_PIN_GROUP("uart1grp", uart1_pins, uart1_mux),
ADI_PIN_GROUP("uart1ctsrtsgrp", uart1_ctsrts_pins, uart1_ctsrts_mux),
ADI_PIN_GROUP("rsi0grp", rsi0_pins, rsi0_mux),
ADI_PIN_GROUP("eth0grp", eth0_pins, eth0_mux),
ADI_PIN_GROUP("eth1grp", eth1_pins, eth1_mux),
ADI_PIN_GROUP("spi0grp", spi0_pins, spi0_mux),
ADI_PIN_GROUP("spi1grp", spi1_pins, spi1_mux),
ADI_PIN_GROUP("twi0grp", twi0_pins, twi0_mux),
ADI_PIN_GROUP("twi1grp", twi1_pins, twi1_mux),
ADI_PIN_GROUP("rotarygrp", rotary_pins, rotary_mux),
ADI_PIN_GROUP("can0grp", can0_pins, can0_mux),
ADI_PIN_GROUP("smc0grp", smc0_pins, smc0_mux),
ADI_PIN_GROUP("sport0grp", sport0_pins, sport0_mux),
ADI_PIN_GROUP("sport1grp", sport1_pins, sport1_mux),
ADI_PIN_GROUP("sport2grp", sport2_pins, sport2_mux),
ADI_PIN_GROUP("ppi0_8bgrp", ppi0_8b_pins, ppi0_8b_mux),
ADI_PIN_GROUP("ppi0_16bgrp", ppi0_16b_pins, ppi0_16b_mux),
ADI_PIN_GROUP("ppi0_24bgrp", ppi0_24b_pins, ppi0_24b_mux),
ADI_PIN_GROUP("ppi1_8bgrp", ppi1_8b_pins, ppi1_8b_mux),
ADI_PIN_GROUP("ppi1_16bgrp", ppi1_16b_pins, ppi1_16b_mux),
ADI_PIN_GROUP("ppi2_8bgrp", ppi2_8b_pins, ppi2_8b_mux),
ADI_PIN_GROUP("ppi2_16bgrp", ppi2_16b_pins, ppi2_16b_mux),
ADI_PIN_GROUP("lp0grp", lp0_pins, lp0_mux),
ADI_PIN_GROUP("lp1grp", lp1_pins, lp1_mux),
ADI_PIN_GROUP("lp2grp", lp2_pins, lp2_mux),
ADI_PIN_GROUP("lp3grp", lp3_pins, lp3_mux),
};
static const char * const uart0grp[] = { "uart0grp" };
static const char * const uart0ctsrtsgrp[] = { "uart0ctsrtsgrp" };
static const char * const uart1grp[] = { "uart1grp" };
......@@ -463,47 +463,43 @@ static const char * const smc0grp[] = { "smc0grp" };
static const char * const sport0grp[] = { "sport0grp" };
static const char * const sport1grp[] = { "sport1grp" };
static const char * const sport2grp[] = { "sport2grp" };
static const char * const ppi0_8bgrp[] = { "ppi0_8bgrp" };
static const char * const ppi0_16bgrp[] = { "ppi0_16bgrp" };
static const char * const ppi0_24bgrp[] = { "ppi0_24bgrp" };
static const char * const ppi1_8bgrp[] = { "ppi1_8bgrp" };
static const char * const ppi1_16bgrp[] = { "ppi1_16bgrp" };
static const char * const ppi2_8bgrp[] = { "ppi2_8bgrp" };
static const char * const ppi2_16bgrp[] = { "ppi2_16bgrp" };
static const char * const ppi0grp[] = { "ppi0_8bgrp",
"ppi0_16bgrp",
"ppi0_24bgrp" };
static const char * const ppi1grp[] = { "ppi1_8bgrp",
"ppi1_16bgrp" };
static const char * const ppi2grp[] = { "ppi2_8bgrp",
"ppi2_16bgrp" };
static const char * const lp0grp[] = { "lp0grp" };
static const char * const lp1grp[] = { "lp1grp" };
static const char * const lp2grp[] = { "lp2grp" };
static const char * const lp3grp[] = { "lp3grp" };
static const struct adi_pmx_func adi_pmx_functions[] = {
ADI_PMX_FUNCTION("uart0", uart0grp, uart0_mux),
ADI_PMX_FUNCTION("uart0_ctsrts", uart0ctsrtsgrp, uart0_ctsrts_mux),
ADI_PMX_FUNCTION("uart1", uart1grp, uart1_mux),
ADI_PMX_FUNCTION("uart1_ctsrts", uart1ctsrtsgrp, uart1_ctsrts_mux),
ADI_PMX_FUNCTION("rsi0", rsi0grp, rsi0_mux),
ADI_PMX_FUNCTION("eth0", eth0grp, eth0_mux),
ADI_PMX_FUNCTION("eth1", eth1grp, eth1_mux),
ADI_PMX_FUNCTION("spi0", spi0grp, spi0_mux),
ADI_PMX_FUNCTION("spi1", spi1grp, spi1_mux),
ADI_PMX_FUNCTION("twi0", twi0grp, twi0_mux),
ADI_PMX_FUNCTION("twi1", twi1grp, twi1_mux),
ADI_PMX_FUNCTION("rotary", rotarygrp, rotary_mux),
ADI_PMX_FUNCTION("can0", can0grp, can0_mux),
ADI_PMX_FUNCTION("smc0", smc0grp, smc0_mux),
ADI_PMX_FUNCTION("sport0", sport0grp, sport0_mux),
ADI_PMX_FUNCTION("sport1", sport1grp, sport1_mux),
ADI_PMX_FUNCTION("sport2", sport2grp, sport2_mux),
ADI_PMX_FUNCTION("ppi0_8b", ppi0_8bgrp, ppi0_8b_mux),
ADI_PMX_FUNCTION("ppi0_16b", ppi0_16bgrp, ppi0_16b_mux),
ADI_PMX_FUNCTION("ppi0_24b", ppi0_24bgrp, ppi0_24b_mux),
ADI_PMX_FUNCTION("ppi1_8b", ppi1_8bgrp, ppi1_8b_mux),
ADI_PMX_FUNCTION("ppi1_16b", ppi1_16bgrp, ppi1_16b_mux),
ADI_PMX_FUNCTION("ppi2_8b", ppi2_8bgrp, ppi2_8b_mux),
ADI_PMX_FUNCTION("ppi2_16b", ppi2_16bgrp, ppi2_16b_mux),
ADI_PMX_FUNCTION("lp0", lp0grp, lp0_mux),
ADI_PMX_FUNCTION("lp1", lp1grp, lp1_mux),
ADI_PMX_FUNCTION("lp2", lp2grp, lp2_mux),
ADI_PMX_FUNCTION("lp3", lp3grp, lp3_mux),
ADI_PMX_FUNCTION("uart0", uart0grp),
ADI_PMX_FUNCTION("uart0_ctsrts", uart0ctsrtsgrp),
ADI_PMX_FUNCTION("uart1", uart1grp),
ADI_PMX_FUNCTION("uart1_ctsrts", uart1ctsrtsgrp),
ADI_PMX_FUNCTION("rsi0", rsi0grp),
ADI_PMX_FUNCTION("eth0", eth0grp),
ADI_PMX_FUNCTION("eth1", eth1grp),
ADI_PMX_FUNCTION("spi0", spi0grp),
ADI_PMX_FUNCTION("spi1", spi1grp),
ADI_PMX_FUNCTION("twi0", twi0grp),
ADI_PMX_FUNCTION("twi1", twi1grp),
ADI_PMX_FUNCTION("rotary", rotarygrp),
ADI_PMX_FUNCTION("can0", can0grp),
ADI_PMX_FUNCTION("smc0", smc0grp),
ADI_PMX_FUNCTION("sport0", sport0grp),
ADI_PMX_FUNCTION("sport1", sport1grp),
ADI_PMX_FUNCTION("sport2", sport2grp),
ADI_PMX_FUNCTION("ppi0", ppi0grp),
ADI_PMX_FUNCTION("ppi1", ppi1grp),
ADI_PMX_FUNCTION("ppi2", ppi2grp),
ADI_PMX_FUNCTION("lp0", lp0grp),
ADI_PMX_FUNCTION("lp1", lp1grp),
ADI_PMX_FUNCTION("lp2", lp2grp),
ADI_PMX_FUNCTION("lp3", lp3grp),
};
static const struct adi_pinctrl_soc_data adi_bf60x_soc = {
......
drivers/pinctrl/pinctrl-adi2.c
View file @ d64b3932
......@@ -89,6 +89,19 @@ struct gpio_port_saved {
u32 mux;
};
/*
* struct gpio_pint_saved - PINT registers saved in PM operations
*
* @assign: ASSIGN register
* @edge_set: EDGE_SET register
* @invert_set: INVERT_SET register
*/
struct gpio_pint_saved {
u32 assign;
u32 edge_set;
u32 invert_set;
};
/**
* struct gpio_pint - Pin interrupt controller device. Multiple ADI GPIO
* banks can be mapped into one Pin interrupt controller.
......@@ -114,7 +127,7 @@ struct gpio_pint {
int irq;
struct irq_domain *domain[2];
struct gpio_pint_regs *regs;
struct adi_pm_pint_save saved_data;
struct gpio_pint_saved saved_data;
int map_count;
spinlock_t lock;
......@@ -160,7 +173,7 @@ struct adi_pinctrl {
struct gpio_port {
struct list_head node;
void __iomem *base;
unsigned int irq_base;
int irq_base;
unsigned int width;
struct gpio_port_t *regs;
struct gpio_port_saved saved_data;
......@@ -605,8 +618,8 @@ static struct pinctrl_ops adi_pctrl_ops = {
.get_group_pins = adi_get_group_pins,
};
static int adi_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector,
unsigned group)
static int adi_pinmux_enable(struct pinctrl_dev *pctldev, unsigned func_id,
unsigned group_id)
{
struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
struct gpio_port *port;
......@@ -614,7 +627,7 @@ static int adi_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector,
unsigned long flags;
unsigned short *mux, pin;
mux = (unsigned short *)pinctrl->soc->functions[selector].mux;
mux = (unsigned short *)pinctrl->soc->groups[group_id].mux;
while (*mux) {
pin = P_IDENT(*mux);
......@@ -628,7 +641,7 @@ static int adi_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector,
spin_lock_irqsave(&port->lock, flags);
portmux_setup(port, pin_to_offset(range, pin),
P_FUNCT2MUX(*mux));
P_FUNCT2MUX(*mux));
port_setup(port, pin_to_offset(range, pin), false);
mux++;
......@@ -638,8 +651,8 @@ static int adi_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector,
return 0;
}
static void adi_pinmux_disable(struct pinctrl_dev *pctldev, unsigned selector,
unsigned group)
static void adi_pinmux_disable(struct pinctrl_dev *pctldev, unsigned func_id,
unsigned group_id)
{
struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
struct gpio_port *port;
......@@ -647,7 +660,7 @@ static void adi_pinmux_disable(struct pinctrl_dev *pctldev, unsigned selector,
unsigned long flags;
unsigned short *mux, pin;
mux = (unsigned short *)pinctrl->soc->functions[selector].mux;
mux = (unsigned short *)pinctrl->soc->groups[group_id].mux;
while (*mux) {
pin = P_IDENT(*mux);
......
drivers/pinctrl/pinctrl-adi2.h
View file @ d64b3932
......@@ -21,13 +21,15 @@ struct adi_pin_group {
const char *name;
const unsigned *pins;
const unsigned num;
const unsigned short *mux;
};
#define ADI_PIN_GROUP(n, p) \
#define ADI_PIN_GROUP(n, p, m) \
{ \
.name = n, \
.pins = p, \
.num = ARRAY_SIZE(p), \
.mux = m, \
}
/**
......@@ -41,15 +43,13 @@ struct adi_pmx_func {
const char *name;
const char * const *groups;
const unsigned num_groups;
const unsigned short *mux;
};
#define ADI_PMX_FUNCTION(n, g, m) \
#define ADI_PMX_FUNCTION(n, g) \
{ \
.name = n, \
.groups = g, \
.num_groups = ARRAY_SIZE(g), \
.mux = m, \
}
/**
......
drivers/pinctrl/pinctrl-at91.c
View file @ d64b3932
......@@ -1137,6 +1137,17 @@ static void at91_gpio_free(struct gpio_chip *chip, unsigned offset)
pinctrl_free_gpio(gpio);
}
static int at91_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
{
struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
void __iomem *pio = at91_gpio->regbase;
unsigned mask = 1 << offset;
u32 osr;
osr = readl_relaxed(pio + PIO_OSR);
return !(osr & mask);
}
static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
......@@ -1325,6 +1336,31 @@ static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
return 0;
}
static unsigned int gpio_irq_startup(struct irq_data *d)
{
struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
unsigned pin = d->hwirq;
int ret;
ret = gpio_lock_as_irq(&at91_gpio->chip, pin);
if (ret) {
dev_err(at91_gpio->chip.dev, "unable to lock pind %lu IRQ\n",
d->hwirq);
return ret;
}
gpio_irq_unmask(d);
return 0;
}
static void gpio_irq_shutdown(struct irq_data *d)
{
struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
unsigned pin = d->hwirq;
gpio_irq_mask(d);
gpio_unlock_as_irq(&at91_gpio->chip, pin);
}
#ifdef CONFIG_PM
static u32 wakeups[MAX_GPIO_BANKS];
......@@ -1399,6 +1435,8 @@ void at91_pinctrl_gpio_resume(void)
static struct irq_chip gpio_irqchip = {
.name = "GPIO",
.irq_startup = gpio_irq_startup,
.irq_shutdown = gpio_irq_shutdown,
.irq_disable = gpio_irq_mask,
.irq_mask = gpio_irq_mask,
.irq_unmask = gpio_irq_unmask,
......@@ -1543,6 +1581,7 @@ static int at91_gpio_of_irq_setup(struct device_node *node,
static struct gpio_chip at91_gpio_template = {
.request = at91_gpio_request,
.free = at91_gpio_free,
.get_direction = at91_gpio_get_direction,
.direction_input = at91_gpio_direction_input,
.get = at91_gpio_get,
.direction_output = at91_gpio_direction_output,
......
drivers/pinctrl/pinctrl-baytrail.c
View file @ d64b3932
......@@ -60,6 +60,10 @@
#define BYT_NGPIO_NCORE 28
#define BYT_NGPIO_SUS 44
#define BYT_SCORE_ACPI_UID "1"
#define BYT_NCORE_ACPI_UID "2"
#define BYT_SUS_ACPI_UID "3"
/*
* Baytrail gpio controller consist of three separate sub-controllers called
* SCORE, NCORE and SUS. The sub-controllers are identified by their acpi UID.
......@@ -102,17 +106,17 @@ static unsigned const sus_pins[BYT_NGPIO_SUS] = {
static struct pinctrl_gpio_range byt_ranges[] = {
{
.name = "1", /* match with acpi _UID in probe */
.name = BYT_SCORE_ACPI_UID, /* match with acpi _UID in probe */
.npins = BYT_NGPIO_SCORE,
.pins = score_pins,
},
{
.name = "2",
.name = BYT_NCORE_ACPI_UID,
.npins = BYT_NGPIO_NCORE,
.pins = ncore_pins,
},
{
.name = "3",
.name = BYT_SUS_ACPI_UID,
.npins = BYT_NGPIO_SUS,
.pins = sus_pins,
},
......@@ -145,9 +149,41 @@ static void __iomem *byt_gpio_reg(struct gpio_chip *chip, unsigned offset,
return vg->reg_base + reg_offset + reg;
}
static bool is_special_pin(struct byt_gpio *vg, unsigned offset)
{
/* SCORE pin 92-93 */
if (!strcmp(vg->range->name, BYT_SCORE_ACPI_UID) &&
offset >= 92 && offset <= 93)
return true;
/* SUS pin 11-21 */
if (!strcmp(vg->range->name, BYT_SUS_ACPI_UID) &&
offset >= 11 && offset <= 21)
return true;
return false;
}
static int byt_gpio_request(struct gpio_chip *chip, unsigned offset)
{
struct byt_gpio *vg = to_byt_gpio(chip);
void __iomem *reg = byt_gpio_reg(chip, offset, BYT_CONF0_REG);
u32 value;
bool special;
/*
* In most cases, func pin mux 000 means GPIO function.
* But, some pins may have func pin mux 001 represents
* GPIO function. Only allow user to export pin with
* func pin mux preset as GPIO function by BIOS/FW.
*/
value = readl(reg) & BYT_PIN_MUX;
special = is_special_pin(vg, offset);
if ((special && value != 1) || (!special && value)) {
dev_err(&vg->pdev->dev,
"pin %u cannot be used as GPIO.\n", offset);
return -EINVAL;
}
pm_runtime_get(&vg->pdev->dev);
......
drivers/pinctrl/pinctrl-exynos.c
View file @ d64b3932
......@@ -1042,6 +1042,88 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
},
};
/* pin banks of exynos5260 pin-controller 0 */
static struct samsung_pin_bank exynos5260_pin_banks0[] = {
EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00),
EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04),
EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10),
EXYNOS_PIN_BANK_EINTG(5, 0x0a0, "gpb2", 0x14),
EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpb3", 0x18),
EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpb4", 0x1c),
EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpb5", 0x20),
EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd0", 0x24),
EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpd1", 0x28),
EXYNOS_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c),
EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe0", 0x30),
EXYNOS_PIN_BANK_EINTG(5, 0x1a0, "gpe1", 0x34),
EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpf0", 0x38),
EXYNOS_PIN_BANK_EINTG(8, 0x1e0, "gpf1", 0x3c),
EXYNOS_PIN_BANK_EINTG(2, 0x200, "gpk0", 0x40),
EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00),
EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04),
EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08),
EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c),
};
/* pin banks of exynos5260 pin-controller 1 */
static struct samsung_pin_bank exynos5260_pin_banks1[] = {
EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00),
EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04),
EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),
EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpc4", 0x10),
};
/* pin banks of exynos5260 pin-controller 2 */
static struct samsung_pin_bank exynos5260_pin_banks2[] = {
EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
};
/*
* Samsung pinctrl driver data for Exynos5260 SoC. Exynos5260 SoC includes
* three gpio/pin-mux/pinconfig controllers.
*/
struct samsung_pin_ctrl exynos5260_pin_ctrl[] = {
{
/* pin-controller instance 0 data */
.pin_banks = exynos5260_pin_banks0,
.nr_banks = ARRAY_SIZE(exynos5260_pin_banks0),
.geint_con = EXYNOS_GPIO_ECON_OFFSET,
.geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
.geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
.weint_con = EXYNOS_WKUP_ECON_OFFSET,
.weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
.weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
.svc = EXYNOS_SVC_OFFSET,
.eint_gpio_init = exynos_eint_gpio_init,
.eint_wkup_init = exynos_eint_wkup_init,
.label = "exynos5260-gpio-ctrl0",
}, {
/* pin-controller instance 1 data */
.pin_banks = exynos5260_pin_banks1,
.nr_banks = ARRAY_SIZE(exynos5260_pin_banks1),
.geint_con = EXYNOS_GPIO_ECON_OFFSET,
.geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
.geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
.svc = EXYNOS_SVC_OFFSET,
.eint_gpio_init = exynos_eint_gpio_init,
.label = "exynos5260-gpio-ctrl1",
}, {
/* pin-controller instance 2 data */
.pin_banks = exynos5260_pin_banks2,
.nr_banks = ARRAY_SIZE(exynos5260_pin_banks2),
.geint_con = EXYNOS_GPIO_ECON_OFFSET,
.geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
.geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
.svc = EXYNOS_SVC_OFFSET,
.eint_gpio_init = exynos_eint_gpio_init,
.label = "exynos5260-gpio-ctrl2",
},
};
/* pin banks of exynos5420 pin-controller 0 */
static struct samsung_pin_bank exynos5420_pin_banks0[] = {
EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00),
......
drivers/pinctrl/pinctrl-imx.c
View file @ d64b3932
......@@ -491,7 +491,7 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
pin->mux_mode |= IOMUXC_CONFIG_SION;
pin->config = config & ~IMX_PAD_SION;
dev_dbg(info->dev, "%s: %d 0x%08lx", info->pins[i].name,
dev_dbg(info->dev, "%s: %d 0x%08lx", info->pins[pin_id].name,
pin->mux_mode, pin->config);
}
......
drivers/pinctrl/pinctrl-msm.c
View file @ d64b3932
......@@ -28,7 +28,6 @@
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/of_irq.h>
#include <linux/spinlock.h>
#include "core.h"
......@@ -50,7 +49,6 @@
* @enabled_irqs: Bitmap of currently enabled irqs.
* @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge
* detection.
* @wake_irqs: Bitmap of irqs with requested as wakeup source.
* @soc; Reference to soc_data of platform specific data.
* @regs: Base address for the TLMM register map.
*/
......@@ -65,7 +63,6 @@ struct msm_pinctrl {
DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO);
DECLARE_BITMAP(wake_irqs, MAX_NR_GPIO);
const struct msm_pinctrl_soc_data *soc;
void __iomem *regs;
......@@ -203,42 +200,29 @@ static const struct pinmux_ops msm_pinmux_ops = {
static int msm_config_reg(struct msm_pinctrl *pctrl,
const struct msm_pingroup *g,
unsigned param,
s16 *reg,
unsigned *mask,
unsigned *bit)
{
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
*reg = g->ctl_reg;
*bit = g->pull_bit;
*mask = 3;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
*reg = g->ctl_reg;
*bit = g->pull_bit;
*mask = 3;
break;
case PIN_CONFIG_BIAS_PULL_UP:
*reg = g->ctl_reg;
*bit = g->pull_bit;
*mask = 3;
break;
case PIN_CONFIG_DRIVE_STRENGTH:
*reg = g->ctl_reg;
*bit = g->drv_bit;
*mask = 7;
break;
case PIN_CONFIG_OUTPUT:
*bit = g->oe_bit;
*mask = 1;
break;
default:
dev_err(pctrl->dev, "Invalid config param %04x\n", param);
return -ENOTSUPP;
}
if (*reg < 0) {
dev_err(pctrl->dev, "Config param %04x not supported on group %s\n",
param, g->name);
return -ENOTSUPP;
}
return 0;
}
......@@ -261,8 +245,10 @@ static int msm_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
#define MSM_PULL_DOWN 1
#define MSM_PULL_UP 3
static const unsigned msm_regval_to_drive[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
static const unsigned msm_drive_to_regval[] = { -1, -1, 0, -1, 1, -1, 2, -1, 3, -1, 4, -1, 5, -1, 6, -1, 7 };
static unsigned msm_regval_to_drive(u32 val)
{
return (val + 1) * 2;
}
static int msm_config_group_get(struct pinctrl_dev *pctldev,
unsigned int group,
......@@ -274,17 +260,16 @@ static int msm_config_group_get(struct pinctrl_dev *pctldev,
unsigned mask;
unsigned arg;
unsigned bit;
s16 reg;
int ret;
u32 val;
g = &pctrl->soc->groups[group];
ret = msm_config_reg(pctrl, g, param, &reg, &mask, &bit);
ret = msm_config_reg(pctrl, g, param, &mask, &bit);
if (ret < 0)
return ret;
val = readl(pctrl->regs + reg);
val = readl(pctrl->regs + g->ctl_reg);
arg = (val >> bit) & mask;
/* Convert register value to pinconf value */
......@@ -299,7 +284,15 @@ static int msm_config_group_get(struct pinctrl_dev *pctldev,
arg = arg == MSM_PULL_UP;
break;
case PIN_CONFIG_DRIVE_STRENGTH:
arg = msm_regval_to_drive[arg];
arg = msm_regval_to_drive(arg);
break;
case PIN_CONFIG_OUTPUT:
/* Pin is not output */
if (!arg)
return -EINVAL;
val = readl(pctrl->regs + g->io_reg);
arg = !!(val & BIT(g->in_bit));
break;
default:
dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
......@@ -324,7 +317,6 @@ static int msm_config_group_set(struct pinctrl_dev *pctldev,
unsigned mask;
unsigned arg;
unsigned bit;
s16 reg;
int ret;
u32 val;
int i;
......@@ -335,7 +327,7 @@ static int msm_config_group_set(struct pinctrl_dev *pctldev,
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
ret = msm_config_reg(pctrl, g, param, &reg, &mask, &bit);
ret = msm_config_reg(pctrl, g, param, &mask, &bit);
if (ret < 0)
return ret;
......@@ -352,10 +344,24 @@ static int msm_config_group_set(struct pinctrl_dev *pctldev,
break;
case PIN_CONFIG_DRIVE_STRENGTH:
/* Check for invalid values */
if (arg >= ARRAY_SIZE(msm_drive_to_regval))
if (arg > 16 || arg < 2 || (arg % 2) != 0)
arg = -1;
else
arg = msm_drive_to_regval[arg];
arg = (arg / 2) - 1;
break;
case PIN_CONFIG_OUTPUT:
/* set output value */
spin_lock_irqsave(&pctrl->lock, flags);
val = readl(pctrl->regs + g->io_reg);
if (arg)
val |= BIT(g->out_bit);
else
val &= ~BIT(g->out_bit);
writel(val, pctrl->regs + g->io_reg);
spin_unlock_irqrestore(&pctrl->lock, flags);
/* enable output */
arg = 1;
break;
default:
dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
......@@ -370,10 +376,10 @@ static int msm_config_group_set(struct pinctrl_dev *pctldev,
}
spin_lock_irqsave(&pctrl->lock, flags);
val = readl(pctrl->regs + reg);
val = readl(pctrl->regs + g->ctl_reg);
val &= ~(mask << bit);
val |= arg << bit;
writel(val, pctrl->regs + reg);
writel(val, pctrl->regs + g->ctl_reg);
spin_unlock_irqrestore(&pctrl->lock, flags);
}
......@@ -402,8 +408,6 @@ static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
u32 val;
g = &pctrl->soc->groups[offset];
if (WARN_ON(g->io_reg < 0))
return -EINVAL;
spin_lock_irqsave(&pctrl->lock, flags);
......@@ -424,8 +428,6 @@ static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, in
u32 val;
g = &pctrl->soc->groups[offset];
if (WARN_ON(g->io_reg < 0))
return -EINVAL;
spin_lock_irqsave(&pctrl->lock, flags);
......@@ -452,8 +454,6 @@ static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
u32 val;
g = &pctrl->soc->groups[offset];
if (WARN_ON(g->io_reg < 0))
return -EINVAL;
val = readl(pctrl->regs + g->io_reg);
return !!(val & BIT(g->in_bit));
......@@ -467,8 +467,6 @@ static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
u32 val;
g = &pctrl->soc->groups[offset];
if (WARN_ON(g->io_reg < 0))
return;
spin_lock_irqsave(&pctrl->lock, flags);
......@@ -534,7 +532,7 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
pull = (ctl_reg >> g->pull_bit) & 3;
seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func);
seq_printf(s, " %dmA", msm_regval_to_drive[drive]);
seq_printf(s, " %dmA", msm_regval_to_drive(drive));
seq_printf(s, " %s", pulls[pull]);
}
......@@ -617,8 +615,6 @@ static void msm_gpio_irq_mask(struct irq_data *d)
pctrl = irq_data_get_irq_chip_data(d);
g = &pctrl->soc->groups[d->hwirq];
if (WARN_ON(g->intr_cfg_reg < 0))
return;
spin_lock_irqsave(&pctrl->lock, flags);
......@@ -640,8 +636,6 @@ static void msm_gpio_irq_unmask(struct irq_data *d)
pctrl = irq_data_get_irq_chip_data(d);
g = &pctrl->soc->groups[d->hwirq];
if (WARN_ON(g->intr_status_reg < 0))
return;
spin_lock_irqsave(&pctrl->lock, flags);
......@@ -667,8 +661,6 @@ static void msm_gpio_irq_ack(struct irq_data *d)
pctrl = irq_data_get_irq_chip_data(d);
g = &pctrl->soc->groups[d->hwirq];
if (WARN_ON(g->intr_status_reg < 0))
return;
spin_lock_irqsave(&pctrl->lock, flags);
......@@ -693,8 +685,6 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
pctrl = irq_data_get_irq_chip_data(d);
g = &pctrl->soc->groups[d->hwirq];
if (WARN_ON(g->intr_cfg_reg < 0))
return -EINVAL;
spin_lock_irqsave(&pctrl->lock, flags);
......@@ -783,22 +773,12 @@ static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
{
struct msm_pinctrl *pctrl;
unsigned long flags;
unsigned ngpio;
pctrl = irq_data_get_irq_chip_data(d);
ngpio = pctrl->chip.ngpio;
spin_lock_irqsave(&pctrl->lock, flags);
if (on) {
if (bitmap_empty(pctrl->wake_irqs, ngpio))
enable_irq_wake(pctrl->irq);
set_bit(d->hwirq, pctrl->wake_irqs);
} else {
clear_bit(d->hwirq, pctrl->wake_irqs);
if (bitmap_empty(pctrl->wake_irqs, ngpio))
disable_irq_wake(pctrl->irq);
}
irq_set_irq_wake(pctrl->irq, on);
spin_unlock_irqrestore(&pctrl->lock, flags);
......@@ -869,6 +849,12 @@ static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
chained_irq_exit(chip, desc);
}
/*
* This lock class tells lockdep that GPIO irqs are in a different
* category than their parents, so it won't report false recursion.
*/
static struct lock_class_key gpio_lock_class;
static int msm_gpio_init(struct msm_pinctrl *pctrl)
{
struct gpio_chip *chip;
......@@ -876,10 +862,14 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
int ret;
int i;
int r;
unsigned ngpio = pctrl->soc->ngpios;
if (WARN_ON(ngpio > MAX_NR_GPIO))
return -EINVAL;
chip = &pctrl->chip;
chip->base = 0;
chip->ngpio = pctrl->soc->ngpios;
chip->ngpio = ngpio;
chip->label = dev_name(pctrl->dev);
chip->dev = pctrl->dev;
chip->owner = THIS_MODULE;
......@@ -907,6 +897,7 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
for (i = 0; i < chip->ngpio; i++) {
irq = irq_create_mapping(pctrl->domain, i);
irq_set_lockdep_class(irq, &gpio_lock_class);
irq_set_chip_and_handler(irq, &msm_gpio_irq_chip, handle_edge_irq);
irq_set_chip_data(irq, pctrl);
}
......
drivers/pinctrl/pinctrl-msm.h
View file @ d64b3932
......@@ -13,10 +13,7 @@
#ifndef __PINCTRL_MSM_H__
#define __PINCTRL_MSM_H__
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/machine.h>
struct pinctrl_pin_desc;
/**
* struct msm_function - a pinmux function
......
drivers/pinctrl/pinctrl-msm8x74.c
View file @ d64b3932
......@@ -15,7 +15,6 @@
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "pinctrl-msm.h"
......@@ -406,6 +405,7 @@ enum msm8x74_functions {
MSM_MUX_blsp_i2c6,
MSM_MUX_blsp_i2c11,
MSM_MUX_blsp_spi1,
MSM_MUX_blsp_spi8,
MSM_MUX_blsp_uart2,
MSM_MUX_blsp_uart8,
MSM_MUX_slimbus,
......@@ -416,6 +416,9 @@ static const char * const blsp_i2c2_groups[] = { "gpio6", "gpio7" };
static const char * const blsp_i2c6_groups[] = { "gpio29", "gpio30" };
static const char * const blsp_i2c11_groups[] = { "gpio83", "gpio84" };
static const char * const blsp_spi1_groups[] = { "gpio0", "gpio1", "gpio2", "gpio3" };
static const char * const blsp_spi8_groups[] = {
"gpio45", "gpio46", "gpio47", "gpio48"
};
static const char * const blsp_uart2_groups[] = { "gpio4", "gpio5" };
static const char * const blsp_uart8_groups[] = { "gpio45", "gpio46" };
static const char * const slimbus_groups[] = { "gpio70", "gpio71" };
......@@ -425,6 +428,7 @@ static const struct msm_function msm8x74_functions[] = {
FUNCTION(blsp_i2c6),
FUNCTION(blsp_i2c11),
FUNCTION(blsp_spi1),
FUNCTION(blsp_spi8),
FUNCTION(blsp_uart2),
FUNCTION(blsp_uart8),
FUNCTION(slimbus),
......@@ -476,10 +480,10 @@ static const struct msm_pingroup msm8x74_groups[] = {
PINGROUP(42, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(43, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(44, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(45, NA, blsp_uart8, NA, NA, NA, NA, NA),
PINGROUP(46, NA, blsp_uart8, NA, NA, NA, NA, NA),
PINGROUP(47, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(48, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(45, blsp_spi8, blsp_uart8, NA, NA, NA, NA, NA),
PINGROUP(46, blsp_spi8, blsp_uart8, NA, NA, NA, NA, NA),
PINGROUP(47, blsp_spi8, NA, NA, NA, NA, NA, NA),
PINGROUP(48, blsp_spi8, NA, NA, NA, NA, NA, NA),
PINGROUP(49, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(50, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(51, NA, NA, NA, NA, NA, NA, NA),
......
drivers/pinctrl/pinctrl-nomadik.c
View file @ d64b3932
......@@ -2035,27 +2035,29 @@ static const struct of_device_id nmk_pinctrl_match[] = {
{},
};
static int nmk_pinctrl_suspend(struct platform_device *pdev, pm_message_t state)
#ifdef CONFIG_PM_SLEEP
static int nmk_pinctrl_suspend(struct device *dev)
{
struct nmk_pinctrl *npct;
npct = platform_get_drvdata(pdev);
npct = dev_get_drvdata(dev);
if (!npct)
return -EINVAL;
return pinctrl_force_sleep(npct->pctl);
}
static int nmk_pinctrl_resume(struct platform_device *pdev)
static int nmk_pinctrl_resume(struct device *dev)
{
struct nmk_pinctrl *npct;
npct = platform_get_drvdata(pdev);
npct = dev_get_drvdata(dev);
if (!npct)
return -EINVAL;
return pinctrl_force_default(npct->pctl);
}
#endif
static int nmk_pinctrl_probe(struct platform_device *pdev)
{
......@@ -2144,17 +2146,18 @@ static struct platform_driver nmk_gpio_driver = {
.probe = nmk_gpio_probe,
};
static SIMPLE_DEV_PM_OPS(nmk_pinctrl_pm_ops,
nmk_pinctrl_suspend,
nmk_pinctrl_resume);
static struct platform_driver nmk_pinctrl_driver = {
.driver = {
.owner = THIS_MODULE,
.name = "pinctrl-nomadik",
.of_match_table = nmk_pinctrl_match,
.pm = &nmk_pinctrl_pm_ops,
},
.probe = nmk_pinctrl_probe,
#ifdef CONFIG_PM
.suspend = nmk_pinctrl_suspend,
.resume = nmk_pinctrl_resume,
#endif
};
static int __init nmk_gpio_init(void)
......
drivers/pinctrl/pinctrl-samsung.c
View file @ d64b3932
......@@ -1120,6 +1120,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
.data = (void *)exynos4x12_pin_ctrl },
{ .compatible = "samsung,exynos5250-pinctrl",
.data = (void *)exynos5250_pin_ctrl },
{ .compatible = "samsung,exynos5260-pinctrl",
.data = (void *)exynos5260_pin_ctrl },
{ .compatible = "samsung,exynos5420-pinctrl",
.data = (void *)exynos5420_pin_ctrl },
{ .compatible = "samsung,s5pv210-pinctrl",
......
drivers/pinctrl/pinctrl-samsung.h
View file @ d64b3932
......@@ -254,6 +254,7 @@ struct samsung_pmx_func {
extern struct samsung_pin_ctrl exynos4210_pin_ctrl[];
extern struct samsung_pin_ctrl exynos4x12_pin_ctrl[];
extern struct samsung_pin_ctrl exynos5250_pin_ctrl[];
extern struct samsung_pin_ctrl exynos5260_pin_ctrl[];
extern struct samsung_pin_ctrl exynos5420_pin_ctrl[];
extern struct samsung_pin_ctrl s3c64xx_pin_ctrl[];
extern struct samsung_pin_ctrl s3c2412_pin_ctrl[];
......
drivers/pinctrl/pinctrl-single.c
View file @ d64b3932
......@@ -662,6 +662,7 @@ static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
break;
case PIN_CONFIG_DRIVE_STRENGTH:
case PIN_CONFIG_SLEW_RATE:
case PIN_CONFIG_LOW_POWER_MODE:
default:
*config = data;
break;
......@@ -699,6 +700,7 @@ static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
case PIN_CONFIG_INPUT_SCHMITT:
case PIN_CONFIG_DRIVE_STRENGTH:
case PIN_CONFIG_SLEW_RATE:
case PIN_CONFIG_LOW_POWER_MODE:
shift = ffs(func->conf[i].mask) - 1;
data &= ~func->conf[i].mask;
data |= (arg << shift) & func->conf[i].mask;
......@@ -1101,6 +1103,7 @@ static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
{ "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, },
{ "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, },
{ "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, },
{ "pinctrl-single,low-power-mode", PIN_CONFIG_LOW_POWER_MODE, },
};
struct pcs_conf_type prop4[] = {
{ "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, },
......
drivers/pinctrl/pinctrl-st.c
View file @ d64b3932
This diff is collapsed.
drivers/pinctrl/pinctrl-sunxi-pins.h
View file @ d64b3932
......@@ -1932,27 +1932,27 @@ static const struct sunxi_desc_pin sun5i_a13_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x4, "mmc0")), /* D1 */
SUNXI_FUNCTION(0x2, "mmc0")), /* D1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x4, "mmc0")), /* D0 */
SUNXI_FUNCTION(0x2, "mmc0")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x4, "mmc0")), /* CLK */
SUNXI_FUNCTION(0x2, "mmc0")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x4, "mmc0")), /* CMD */
SUNXI_FUNCTION(0x2, "mmc0")), /* CMD */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x4, "mmc0")), /* D3 */
SUNXI_FUNCTION(0x2, "mmc0")), /* D3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x4, "mmc0")), /* D2 */
SUNXI_FUNCTION(0x2, "mmc0")), /* D2 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
SUNXI_FUNCTION(0x0, "gpio_in"),
......
drivers/pinctrl/pinctrl-tegra.c
View file @ d64b3932
......@@ -39,6 +39,7 @@ struct tegra_pmx {
struct pinctrl_dev *pctl;
const struct tegra_pinctrl_soc_data *soc;
const char **group_pins;
int nbanks;
void __iomem **regs;
......@@ -620,6 +621,8 @@ int tegra_pinctrl_probe(struct platform_device *pdev,
struct tegra_pmx *pmx;
struct resource *res;
int i;
const char **group_pins;
int fn, gn, gfn;
pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
if (!pmx) {
......@@ -629,6 +632,41 @@ int tegra_pinctrl_probe(struct platform_device *pdev,
pmx->dev = &pdev->dev;
pmx->soc = soc_data;
/*
* Each mux group will appear in 4 functions' list of groups.
* This over-allocates slightly, since not all groups are mux groups.
*/
pmx->group_pins = devm_kzalloc(&pdev->dev,
soc_data->ngroups * 4 * sizeof(*pmx->group_pins),
GFP_KERNEL);
if (!pmx->group_pins)
return -ENOMEM;
group_pins = pmx->group_pins;
for (fn = 0; fn < soc_data->nfunctions; fn++) {
struct tegra_function *func = &soc_data->functions[fn];
func->groups = group_pins;
for (gn = 0; gn < soc_data->ngroups; gn++) {
const struct tegra_pingroup *g = &soc_data->groups[gn];
if (g->mux_reg == -1)
continue;
for (gfn = 0; gfn < 4; gfn++)
if (g->funcs[gfn] == fn)
break;
if (gfn == 4)
continue;
BUG_ON(group_pins - pmx->group_pins >=
soc_data->ngroups * 4);
*group_pins++ = g->name;
func->ngroups++;
}
}
tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios;
tegra_pinctrl_desc.name = dev_name(&pdev->dev);
tegra_pinctrl_desc.pins = pmx->soc->pins;
......
drivers/pinctrl/pinctrl-tegra.h
View file @ d64b3932
......@@ -72,7 +72,7 @@ enum tegra_pinconf_tristate {
*/
struct tegra_function {
const char *name;
const char * const *groups;
const char **groups;
unsigned ngroups;
};
......@@ -193,7 +193,7 @@ struct tegra_pinctrl_soc_data {
unsigned ngpios;
const struct pinctrl_pin_desc *pins;
unsigned npins;
const struct tegra_function *functions;
struct tegra_function *functions;
unsigned nfunctions;
const struct tegra_pingroup *groups;
unsigned ngroups;
......
drivers/pinctrl/pinctrl-tegra114.c
View file @ d64b3932
This diff is collapsed.
drivers/pinctrl/pinctrl-tegra124.c
View file @ d64b3932
This diff is collapsed.
drivers/pinctrl/pinctrl-tegra20.c
View file @ d64b3932
......@@ -1894,637 +1894,12 @@ enum tegra_mux {
TEGRA_MUX_XIO,
};
static const char * const ahb_clk_groups[] = {
"cdev2",
};
static const char * const apb_clk_groups[] = {
"cdev2",
};
static const char * const audio_sync_groups[] = {
"cdev1",
};
static const char * const crt_groups[] = {
"crtp",
"lm1",
};
static const char * const dap1_groups[] = {
"dap1",
};
static const char * const dap2_groups[] = {
"dap2",
};
static const char * const dap3_groups[] = {
"dap3",
};
static const char * const dap4_groups[] = {
"dap4",
};
static const char * const dap5_groups[] = {
"gme",
};
static const char * const displaya_groups[] = {
"lcsn",
"ld0",
"ld1",
"ld10",
"ld11",
"ld12",
"ld13",
"ld14",
"ld15",
"ld16",
"ld17",
"ld2",
"ld3",
"ld4",
"ld5",
"ld6",
"ld7",
"ld8",
"ld9",
"ldc",
"ldi",
"lhp0",
"lhp1",
"lhp2",
"lhs",
"lm0",
"lm1",
"lpp",
"lpw0",
"lpw1",
"lpw2",
"lsc0",
"lsc1",
"lsck",
"lsda",
"lsdi",
"lspi",
"lvp0",
"lvp1",
"lvs",
};
static const char * const displayb_groups[] = {
"lcsn",
"ld0",
"ld1",
"ld10",
"ld11",
"ld12",
"ld13",
"ld14",
"ld15",
"ld16",
"ld17",
"ld2",
"ld3",
"ld4",
"ld5",
"ld6",
"ld7",
"ld8",
"ld9",
"ldc",
"ldi",
"lhp0",
"lhp1",
"lhp2",
"lhs",
"lm0",
"lm1",
"lpp",
"lpw0",
"lpw1",
"lpw2",
"lsc0",
"lsc1",
"lsck",
"lsda",
"lsdi",
"lspi",
"lvp0",
"lvp1",
"lvs",
};
static const char * const emc_test0_dll_groups[] = {
"kbca",
};
static const char * const emc_test1_dll_groups[] = {
"kbcc",
};
static const char * const gmi_groups[] = {
"ata",
"atb",
"atc",
"atd",
"ate",
"dap1",
"dap2",
"dap4",
"gma",
"gmb",
"gmc",
"gmd",
"gme",
"gpu",
"irrx",
"irtx",
"pta",
"spia",
"spib",
"spic",
"spid",
"spie",
"uca",
"ucb",
};
static const char * const gmi_int_groups[] = {
"gmb",
};
static const char * const hdmi_groups[] = {
"hdint",
"lpw0",
"lpw2",
"lsc1",
"lsck",
"lsda",
"lspi",
"pta",
};
static const char * const i2cp_groups[] = {
"i2cp",
};
static const char * const i2c1_groups[] = {
"rm",
"spdi",
"spdo",
"spig",
"spih",
};
static const char * const i2c2_groups[] = {
"ddc",
"pta",
};
static const char * const i2c3_groups[] = {
"dtf",
};
static const char * const ide_groups[] = {
"ata",
"atb",
"atc",
"atd",
"ate",
"gmb",
};
static const char * const irda_groups[] = {
"uad",
};
static const char * const kbc_groups[] = {
"kbca",
"kbcb",
"kbcc",
"kbcd",
"kbce",
"kbcf",
};
static const char * const mio_groups[] = {
"kbcb",
"kbcd",
"kbcf",
};
static const char * const mipi_hs_groups[] = {
"uaa",
"uab",
};
static const char * const nand_groups[] = {
"ata",
"atb",
"atc",
"atd",
"ate",
"gmb",
"gmd",
"kbca",
"kbcb",
"kbcc",
"kbcd",
"kbce",
"kbcf",
};
static const char * const osc_groups[] = {
"cdev1",
"cdev2",
};
static const char * const owr_groups[] = {
"kbce",
"owc",
"uac",
};
static const char * const pcie_groups[] = {
"gpv",
"slxa",
"slxk",
};
static const char * const plla_out_groups[] = {
"cdev1",
};
static const char * const pllc_out1_groups[] = {
"csus",
};
static const char * const pllm_out1_groups[] = {
"cdev1",
};
static const char * const pllp_out2_groups[] = {
"csus",
};
static const char * const pllp_out3_groups[] = {
"csus",
};
static const char * const pllp_out4_groups[] = {
"cdev2",
};
static const char * const pwm_groups[] = {
"gpu",
"sdb",
"sdc",
"sdd",
"ucb",
};
static const char * const pwr_intr_groups[] = {
"pmc",
};
static const char * const pwr_on_groups[] = {
"pmc",
};
static const char * const rsvd1_groups[] = {
"dta",
"dtb",
"dtc",
"dtd",
"dte",
"gmd",
"gme",
};
static const char * const rsvd2_groups[] = {
"crtp",
"dap1",
"dap3",
"dap4",
"ddc",
"dtb",
"dtc",
"dte",
"dtf",
"gpu7",
"gpv",
"hdint",
"i2cp",
"owc",
"rm",
"sdio1",
"spdi",
"spdo",
"uac",
"uca",
"uda",
};
static const char * const rsvd3_groups[] = {
"crtp",
"dap2",
"dap3",
"ddc",
"gpu7",
"gpv",
"hdint",
"i2cp",
"ld17",
"ldc",
"ldi",
"lhp0",
"lhp1",
"lhp2",
"lm1",
"lpp",
"lpw1",
"lvp0",
"lvp1",
"owc",
"pmc",
"rm",
"uac",
};
static const char * const rsvd4_groups[] = {
"ata",
"ate",
"crtp",
"dap3",
"dap4",
"ddc",
"dta",
"dtc",
"dtd",
"dtf",
"gpu",
"gpu7",
"gpv",
"hdint",
"i2cp",
"kbce",
"lcsn",
"ld0",
"ld1",
"ld2",
"ld3",
"ld4",
"ld5",
"ld6",
"ld7",
"ld8",
"ld9",
"ld10",
"ld11",
"ld12",
"ld13",
"ld14",
"ld15",
"ld16",
"ld17",
"ldc",
"ldi",
"lhp0",
"lhp1",
"lhp2",
"lhs",
"lm0",
"lpp",
"lpw1",
"lsc0",
"lsdi",
"lvp0",
"lvp1",
"lvs",
"owc",
"pmc",
"pta",
"rm",
"spif",
"uac",
"uca",
"ucb",
};
static const char * const rtck_groups[] = {
"gpu7",
};
static const char * const sdio1_groups[] = {
"sdio1",
};
static const char * const sdio2_groups[] = {
"dap1",
"dta",
"dtd",
"kbca",
"kbcb",
"kbcd",
"spdi",
"spdo",
};
static const char * const sdio3_groups[] = {
"sdb",
"sdc",
"sdd",
"slxa",
"slxc",
"slxd",
"slxk",
};
static const char * const sdio4_groups[] = {
"atb",
"atc",
"atd",
"gma",
"gme",
};
static const char * const sflash_groups[] = {
"gmc",
"gmd",
};
static const char * const spdif_groups[] = {
"slxc",
"slxd",
"spdi",
"spdo",
"uad",
};
static const char * const spi1_groups[] = {
"dtb",
"dte",
"spia",
"spib",
"spic",
"spid",
"spie",
"spif",
"uda",
};
static const char * const spi2_groups[] = {
"sdb",
"slxa",
"slxc",
"slxd",
"slxk",
"spia",
"spib",
"spic",
"spid",
"spie",
"spif",
"spig",
"spih",
"uab",
};
static const char * const spi2_alt_groups[] = {
"spid",
"spie",
"spig",
"spih",
};
static const char * const spi3_groups[] = {
"gma",
"lcsn",
"lm0",
"lpw0",
"lpw2",
"lsc1",
"lsck",
"lsda",
"lsdi",
"sdc",
"sdd",
"spia",
"spib",
"spic",
"spif",
"spig",
"spih",
"uaa",
};
static const char * const spi4_groups[] = {
"gmc",
"irrx",
"irtx",
"slxa",
"slxc",
"slxd",
"slxk",
"uad",
};
static const char * const trace_groups[] = {
"kbcc",
"kbcf",
};
static const char * const twc_groups[] = {
"dap2",
"sdc",
};
static const char * const uarta_groups[] = {
"gpu",
"irrx",
"irtx",
"sdb",
"sdd",
"sdio1",
"uaa",
"uab",
"uad",
};
static const char * const uartb_groups[] = {
"irrx",
"irtx",
};
static const char * const uartc_groups[] = {
"uca",
"ucb",
};
static const char * const uartd_groups[] = {
"gmc",
"uda",
};
static const char * const uarte_groups[] = {
"gma",
"sdio1",
};
static const char * const ulpi_groups[] = {
"uaa",
"uab",
"uda",
};
static const char * const vi_groups[] = {
"dta",
"dtb",
"dtc",
"dtd",
"dte",
"dtf",
};
static const char * const vi_sensor_clk_groups[] = {
"csus",
};
static const char * const xio_groups[] = {
"ld0",
"ld1",
"ld10",
"ld11",
"ld12",
"ld13",
"ld14",
"ld15",
"ld16",
"ld2",
"ld3",
"ld4",
"ld5",
"ld6",
"ld7",
"ld8",
"ld9",
"lhs",
"lsc0",
"lspi",
"lvs",
};
#define FUNCTION(fname) \
{ \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
static const struct tegra_function tegra20_functions[] = {
static struct tegra_function tegra20_functions[] = {
FUNCTION(ahb_clk),
FUNCTION(apb_clk),
FUNCTION(audio_sync),
......@@ -2881,18 +2256,7 @@ static struct platform_driver tegra20_pinctrl_driver = {
.probe = tegra20_pinctrl_probe,
.remove = tegra_pinctrl_remove,
};
static int __init tegra20_pinctrl_init(void)
{
return platform_driver_register(&tegra20_pinctrl_driver);
}
arch_initcall(tegra20_pinctrl_init);
static void __exit tegra20_pinctrl_exit(void)
{
platform_driver_unregister(&tegra20_pinctrl_driver);
}
module_exit(tegra20_pinctrl_exit);
module_platform_driver(tegra20_pinctrl_driver);
MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
MODULE_DESCRIPTION("NVIDIA Tegra20 pinctrl driver");
......
drivers/pinctrl/pinctrl-tegra30.c
View file @ d64b3932
This diff is collapsed.
drivers/pinctrl/sh-pfc/pfc-r8a7790.c
View file @ d64b3932
This diff is collapsed.
drivers/pinctrl/sh-pfc/pfc-r8a7791.c
View file @ d64b3932
This diff is collapsed.
drivers/pinctrl/sirf/pinctrl-atlas6.c
View file @ d64b3932
/*
* pinctrl pads, groups, functions for CSR SiRFatlasVI
*
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
* Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
* company.
*
* Licensed under GPLv2 or later.
*/
......@@ -529,6 +530,40 @@ static const struct sirfsoc_padmux usp0_padmux = {
static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 };
static const struct sirfsoc_muxmask usp0_only_utfs_muxmask[] = {
{
.group = 1,
.mask = BIT(19) | BIT(20) | BIT(21) | BIT(22),
},
};
static const struct sirfsoc_padmux usp0_only_utfs_padmux = {
.muxmask_counts = ARRAY_SIZE(usp0_only_utfs_muxmask),
.muxmask = usp0_only_utfs_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(1) | BIT(2) | BIT(6),
.funcval = 0,
};
static const unsigned usp0_only_utfs_pins[] = { 51, 52, 53, 54 };
static const struct sirfsoc_muxmask usp0_only_urfs_muxmask[] = {
{
.group = 1,
.mask = BIT(19) | BIT(20) | BIT(21) | BIT(23),
},
};
static const struct sirfsoc_padmux usp0_only_urfs_padmux = {
.muxmask_counts = ARRAY_SIZE(usp0_only_urfs_muxmask),
.muxmask = usp0_only_urfs_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(1) | BIT(2) | BIT(9),
.funcval = 0,
};
static const unsigned usp0_only_urfs_pins[] = { 51, 52, 53, 55 };
static const struct sirfsoc_muxmask usp0_uart_nostreamctrl_muxmask[] = {
{
.group = 1,
......@@ -905,6 +940,8 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
SIRFSOC_PIN_GROUP("usp0grp", usp0_pins),
SIRFSOC_PIN_GROUP("usp0_uart_nostreamctrl_grp",
usp0_uart_nostreamctrl_pins),
SIRFSOC_PIN_GROUP("usp0_only_utfs_grp", usp0_only_utfs_pins),
SIRFSOC_PIN_GROUP("usp0_only_urfs_grp", usp0_only_urfs_pins),
SIRFSOC_PIN_GROUP("usp1grp", usp1_pins),
SIRFSOC_PIN_GROUP("usp1_uart_nostreamctrl_grp",
usp1_uart_nostreamctrl_pins),
......@@ -953,6 +990,9 @@ static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" };
static const char * const usp0_uart_nostreamctrl_grp[] = {
"usp0_uart_nostreamctrl_grp" };
static const char * const usp0grp[] = { "usp0grp" };
static const char * const usp0_only_utfs_grp[] = { "usp0_only_utfs_grp" };
static const char * const usp0_only_urfs_grp[] = { "usp0_only_urfs_grp" };
static const char * const usp1grp[] = { "usp1grp" };
static const char * const usp1_uart_nostreamctrl_grp[] = {
"usp1_uart_nostreamctrl_grp" };
......@@ -1003,6 +1043,10 @@ static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl",
usp0_uart_nostreamctrl_grp,
usp0_uart_nostreamctrl_padmux),
SIRFSOC_PMX_FUNCTION("usp0_only_utfs", usp0_only_utfs_grp,
usp0_only_utfs_padmux),
SIRFSOC_PMX_FUNCTION("usp0_only_urfs", usp0_only_urfs_grp,
usp0_only_urfs_padmux),
SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux),
SIRFSOC_PMX_FUNCTION("usp1_uart_nostreamctrl",
usp1_uart_nostreamctrl_grp,
......
drivers/pinctrl/sirf/pinctrl-prima2.c
View file @ d64b3932
/*
* pinctrl pads, groups, functions for CSR SiRFprimaII
*
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
* Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
* company.
*
* Licensed under GPLv2 or later.
*/
......
drivers/pinctrl/sirf/pinctrl-sirf.c
View file @ d64b3932
/*
* pinmux driver for CSR SiRFprimaII
*
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
* Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
* company.
*
* Licensed under GPLv2 or later.
*/
......
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