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Commit ea368183 authored by Jay Cornwall's avatar Jay Cornwall Committed by Alex Deucher
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drm/amdkfd: Fix spurious debug exception on gfx10 

s_barrier triggers a debug exception when issued with PRIV=1,
DEBUG_EN=1. This causes spurious notifications to rocm-gdb.

Clear MODE before issuing s_barrier and restore MODE afterwards
in the context restore handler.
Signed-off-by: default avatarJay Cornwall <jay.cornwall@amd.com>
Tested-by: default avatarLaurent Morichetti <laurent.morichetti@amd.com>
Reviewed-by: default avatarFelix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: default avatarFelix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 059ea10a
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Showing with 95 additions and 90 deletions
drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
View file @ ea368183
...@@ -911,7 +911,7 @@ static const uint32_t cwsr_trap_nv1x_hex[] = { ...@@ -911,7 +911,7 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {
0xe0704000, 0x705d0000, 0xe0704000, 0x705d0000,
0x807c817c, 0x8070ff70, 0x807c817c, 0x8070ff70,
0x00000080, 0xbf0a7b7c, 0x00000080, 0xbf0a7b7c,
0xbf85fff8, 0xbf820150, 0xbf85fff8, 0xbf820152,
0xbef4037e, 0x8775ff7f, 0xbef4037e, 0x8775ff7f,
0x0000ffff, 0x8875ff75, 0x0000ffff, 0x8875ff75,
0x00040000, 0xbef60380, 0x00040000, 0xbef60380,
...@@ -1024,62 +1024,63 @@ static const uint32_t cwsr_trap_nv1x_hex[] = { ...@@ -1024,62 +1024,63 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {
0xbe863106, 0xbe883108, 0xbe863106, 0xbe883108,
0xbe8a310a, 0xbe8c310c, 0xbe8a310a, 0xbe8c310c,
0xbe8e310e, 0xbf06807c, 0xbe8e310e, 0xbf06807c,
0xbf84fff0, 0xb9782a05, 0xbf84fff0, 0xba80f801,
0x80788178, 0xbf0d9972, 0x00000000, 0xbf8a0000,
0xbf850002, 0x8f788978, 0xb9782a05, 0x80788178,
0xbf820001, 0x8f788a78, 0xbf0d9972, 0xbf850002,
0xb96e1e06, 0x8f6e8a6e, 0x8f788978, 0xbf820001,
0x80786e78, 0x8078ff78, 0x8f788a78, 0xb96e1e06,
0x00000200, 0xbef603ff, 0x8f6e8a6e, 0x80786e78,
0x01000000, 0xf4211bfa, 0x8078ff78, 0x00000200,
0xbef603ff, 0x01000000,
0xf4211bfa, 0xf0000000,
0x80788478, 0xf4211b3a,
0xf0000000, 0x80788478, 0xf0000000, 0x80788478,
0xf4211b3a, 0xf0000000, 0xf4211b7a, 0xf0000000,
0x80788478, 0xf4211b7a, 0x80788478, 0xf4211c3a,
0xf0000000, 0x80788478, 0xf0000000, 0x80788478,
0xf4211c3a, 0xf0000000, 0xf4211c7a, 0xf0000000,
0x80788478, 0xf4211c7a, 0x80788478, 0xf4211eba,
0xf0000000, 0x80788478, 0xf0000000, 0x80788478,
0xf4211eba, 0xf0000000, 0xf4211efa, 0xf0000000,
0x80788478, 0xf4211efa, 0x80788478, 0xf4211e7a,
0xf0000000, 0x80788478, 0xf0000000, 0x80788478,
0xf4211e7a, 0xf0000000, 0x80788478, 0xf4211cfa,
0x80788478, 0x80788478,
0xf4211cfa, 0xf0000000,
0x80788478, 0xf4211bba,
0xf0000000, 0x80788478, 0xf0000000, 0x80788478,
0xbf8cc07f, 0xb9eef814,
0xf4211bba, 0xf0000000, 0xf4211bba, 0xf0000000,
0x80788478, 0xbf8cc07f, 0x80788478, 0xbf8cc07f,
0xb9eef815, 0xbefc036f, 0xb9eef814, 0xf4211bba,
0xbefe0370, 0xbeff0371, 0xf0000000, 0x80788478,
0x876f7bff, 0x000003ff, 0xbf8cc07f, 0xb9eef815,
0xb9ef4803, 0xb9f9f816, 0xbefc036f, 0xbefe0370,
0x876f7bff, 0xfffff800, 0xbeff0371, 0x876f7bff,
0x906f8b6f, 0xb9efa2c3, 0x000003ff, 0xb9ef4803,
0xb9f3f801, 0xb96e2a05, 0xb9f9f816, 0x876f7bff,
0x806e816e, 0xbf0d9972, 0xfffff800, 0x906f8b6f,
0xbf850002, 0x8f6e896e, 0xb9efa2c3, 0xb9f3f801,
0xbf820001, 0x8f6e8a6e, 0xb96e2a05, 0x806e816e,
0x806eff6e, 0x00000200, 0xbf0d9972, 0xbf850002,
0x806e746e, 0x826f8075, 0x8f6e896e, 0xbf820001,
0x876fff6f, 0x0000ffff, 0x8f6e8a6e, 0x806eff6e,
0xf4091c37, 0xfa000050, 0x00000200, 0x806e746e,
0xf4091d37, 0xfa000060, 0x826f8075, 0x876fff6f,
0xf4011e77, 0xfa000074, 0x0000ffff, 0xf4091c37,
0xbf8cc07f, 0x876fff6d, 0xfa000050, 0xf4091d37,
0xfc000000, 0x906f9a6f, 0xfa000060, 0xf4011e77,
0x8f6f906f, 0xbeee0380, 0xfa000074, 0xbf8cc07f,
0x876fff6d, 0xfc000000,
0x906f9a6f, 0x8f6f906f,
0xbeee0380, 0x886e6f6e,
0x876fff6d, 0x02000000,
0x906f996f, 0x8f6f8f6f,
0x886e6f6e, 0x876fff6d, 0x886e6f6e, 0x876fff6d,
0x02000000, 0x906f996f, 0x01000000, 0x906f986f,
0x8f6f8f6f, 0x886e6f6e, 0x8f6f996f, 0x886e6f6e,
0x876fff6d, 0x01000000, 0x876fff7a, 0x00800000,
0x906f986f, 0x8f6f996f, 0x906f976f, 0xb9eef807,
0x886e6f6e, 0x876fff7a, 0x876dff6d, 0x0000ffff,
0x00800000, 0x906f976f, 0x87fe7e7e, 0x87ea6a6a,
0xb9eef807, 0x876dff6d, 0xb9faf802, 0xbe80226c,
0x0000ffff, 0x87fe7e7e,
0x87ea6a6a, 0xb9faf802,
0xbf8a0000, 0xbe80226c,
0xbf810000, 0xbf9f0000, 0xbf810000, 0xbf9f0000,
0xbf9f0000, 0xbf9f0000, 0xbf9f0000, 0xbf9f0000,
0xbf9f0000, 0xbf9f0000, 0xbf9f0000, 0xbf9f0000,
...@@ -1808,7 +1809,7 @@ static const uint32_t cwsr_trap_gfx10_hex[] = { ...@@ -1808,7 +1809,7 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {
0xe0704000, 0x705d0000, 0xe0704000, 0x705d0000,
0x807c817c, 0x8070ff70, 0x807c817c, 0x8070ff70,
0x00000080, 0xbf0a7b7c, 0x00000080, 0xbf0a7b7c,
0xbf85fff8, 0xbf82013b, 0xbf85fff8, 0xbf82013d,
0xbef4037e, 0x8775ff7f, 0xbef4037e, 0x8775ff7f,
0x0000ffff, 0x8875ff75, 0x0000ffff, 0x8875ff75,
0x00040000, 0xbef60380, 0x00040000, 0xbef60380,
...@@ -1921,51 +1922,52 @@ static const uint32_t cwsr_trap_gfx10_hex[] = { ...@@ -1921,51 +1922,52 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {
0xbe863106, 0xbe883108, 0xbe863106, 0xbe883108,
0xbe8a310a, 0xbe8c310c, 0xbe8a310a, 0xbe8c310c,
0xbe8e310e, 0xbf06807c, 0xbe8e310e, 0xbf06807c,
0xbf84fff0, 0xb9782a05, 0xbf84fff0, 0xba80f801,
0x80788178, 0xbf0d9972, 0x00000000, 0xbf8a0000,
0xbf850002, 0x8f788978, 0xb9782a05, 0x80788178,
0xbf820001, 0x8f788a78, 0xbf0d9972, 0xbf850002,
0xb96e1e06, 0x8f6e8a6e, 0x8f788978, 0xbf820001,
0x80786e78, 0x8078ff78, 0x8f788a78, 0xb96e1e06,
0x00000200, 0xbef603ff, 0x8f6e8a6e, 0x80786e78,
0x01000000, 0xf4211bfa, 0x8078ff78, 0x00000200,
0xbef603ff, 0x01000000,
0xf4211bfa, 0xf0000000,
0x80788478, 0xf4211b3a,
0xf0000000, 0x80788478, 0xf0000000, 0x80788478,
0xf4211b3a, 0xf0000000, 0xf4211b7a, 0xf0000000,
0x80788478, 0xf4211b7a, 0x80788478, 0xf4211c3a,
0xf0000000, 0x80788478, 0xf0000000, 0x80788478,
0xf4211c3a, 0xf0000000, 0xf4211c7a, 0xf0000000,
0x80788478, 0xf4211c7a, 0x80788478, 0xf4211eba,
0xf0000000, 0x80788478, 0xf0000000, 0x80788478,
0xf4211eba, 0xf0000000, 0xf4211efa, 0xf0000000,
0x80788478, 0xf4211efa, 0x80788478, 0xf4211e7a,
0xf0000000, 0x80788478, 0xf0000000, 0x80788478,
0xf4211e7a, 0xf0000000, 0x80788478, 0xf4211cfa,
0x80788478, 0x80788478,
0xf4211cfa, 0xf0000000,
0x80788478, 0xf4211bba,
0xf0000000, 0x80788478, 0xf0000000, 0x80788478,
0xbf8cc07f, 0xb9eef814,
0xf4211bba, 0xf0000000, 0xf4211bba, 0xf0000000,
0x80788478, 0xbf8cc07f, 0x80788478, 0xbf8cc07f,
0xb9eef815, 0xbefc036f, 0xb9eef814, 0xf4211bba,
0xbefe0370, 0xbeff0371, 0xf0000000, 0x80788478,
0x876f7bff, 0x000003ff, 0xbf8cc07f, 0xb9eef815,
0xb9ef4803, 0x876f7bff, 0xbefc036f, 0xbefe0370,
0xfffff800, 0x906f8b6f, 0xbeff0371, 0x876f7bff,
0xb9efa2c3, 0xb9f3f801, 0x000003ff, 0xb9ef4803,
0xb96e2a05, 0x806e816e, 0x876f7bff, 0xfffff800,
0xbf0d9972, 0xbf850002, 0x906f8b6f, 0xb9efa2c3,
0x8f6e896e, 0xbf820001, 0xb9f3f801, 0xb96e2a05,
0x8f6e8a6e, 0x806eff6e, 0x806e816e, 0xbf0d9972,
0x00000200, 0x806e746e, 0xbf850002, 0x8f6e896e,
0x826f8075, 0x876fff6f, 0xbf820001, 0x8f6e8a6e,
0x0000ffff, 0xf4091c37, 0x806eff6e, 0x00000200,
0xfa000050, 0xf4091d37, 0x806e746e, 0x826f8075,
0xfa000060, 0xf4011e77, 0x876fff6f, 0x0000ffff,
0xfa000074, 0xbf8cc07f, 0xf4091c37, 0xfa000050,
0x876dff6d, 0x0000ffff, 0xf4091d37, 0xfa000060,
0x87fe7e7e, 0x87ea6a6a, 0xf4011e77, 0xfa000074,
0xb9faf802, 0xbf8a0000, 0xbf8cc07f, 0x876dff6d,
0x0000ffff, 0x87fe7e7e,
0x87ea6a6a, 0xb9faf802,
0xbe80226c, 0xbf810000, 0xbe80226c, 0xbf810000,
0xbf9f0000, 0xbf9f0000, 0xbf9f0000, 0xbf9f0000,
0xbf9f0000, 0xbf9f0000, 0xbf9f0000, 0xbf9f0000,
......
drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm
View file @ ea368183
...@@ -895,6 +895,11 @@ L_RESTORE_SGPR: ...@@ -895,6 +895,11 @@ L_RESTORE_SGPR:
s_cmp_eq_u32 m0, 0 //scc = (m0 < s_sgpr_save_num) ? 1 : 0 s_cmp_eq_u32 m0, 0 //scc = (m0 < s_sgpr_save_num) ? 1 : 0
s_cbranch_scc0 L_RESTORE_SGPR_LOOP s_cbranch_scc0 L_RESTORE_SGPR_LOOP
// s_barrier with MODE.DEBUG_EN=1, STATUS.PRIV=1 incorrectly asserts debug exception.
// Clear DEBUG_EN before and restore MODE after the barrier.
s_setreg_imm32_b32 hwreg(HW_REG_MODE), 0
s_barrier //barrier to ensure the readiness of LDS before access attemps from any other wave in the same TG
/* restore HW registers */ /* restore HW registers */
L_RESTORE_HWREG: L_RESTORE_HWREG:
// HWREG SR memory offset : size(VGPR)+size(SVGPR)+size(SGPR) // HWREG SR memory offset : size(VGPR)+size(SVGPR)+size(SGPR)
...@@ -978,8 +983,6 @@ L_RESTORE_HWREG: ...@@ -978,8 +983,6 @@ L_RESTORE_HWREG:
s_and_b64 vcc, vcc, vcc // Restore STATUS.VCCZ, not writable by s_setreg_b32 s_and_b64 vcc, vcc, vcc // Restore STATUS.VCCZ, not writable by s_setreg_b32
s_setreg_b32 hwreg(HW_REG_STATUS), s_restore_status // SCC is included, which is changed by previous salu s_setreg_b32 hwreg(HW_REG_STATUS), s_restore_status // SCC is included, which is changed by previous salu
s_barrier //barrier to ensure the readiness of LDS before access attemps from any other wave in the same TG
s_rfe_b64 s_restore_pc_lo //Return to the main shader program and resume execution s_rfe_b64 s_restore_pc_lo //Return to the main shader program and resume execution
L_END_PGM: L_END_PGM:
......
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