- 28 Aug, 2015 40 commits
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Ben Skeggs authored
Signed-off-by:Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
Only a handful of machines have this enabled by default, where it's been proven to work. The workaround can be explicitly enabled with a module option also. Still waiting on feedback from NVIDIA for a proper idea of exactly what this fix is doing, and how to implement it properly. Signed-off-by: -
Ben Skeggs authored
Fixes 2-lane DP on Quadro K620. Signed-off-by: -
Ben Skeggs authored
We only need to mask 0x0f on GM2xx, and want to keep the higher bits on earlier cards. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
We previously assumed that the values "2" and "4" were new in DCB 4.1, however, there's at least one GM107 DCB 4.0 board (Quadro K620) that uses the newer values. Signed-off-by: -
Ilia Mirkin authored
Signed-off-by:
Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by:
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Hans de Goede authored
MSI interrupts appear to not work for nv46 based cards. Change the mc subdev oclass for these cards from nv44 to nv4c, the nv4c mc code is identical to the nv44 mc code except that it does not use msi (it does not define a msi_rearm callback). BugLink: https://bugs.freedesktop.org/show_bug.cgi?id=90435Signed-off-by:
Hans de Goede <hdegoede@redhat.com> Signed-off-by:
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Samuel Pitoiset authored
High level hardware events related to PBFB will monitor all partitions. While we are at it, fix bitfield for this mux. Signed-off-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by:
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Samuel Pitoiset authored
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Samuel Pitoiset authored
This mux only exists on GF108+ (except for GF110 one), but since it is not used by the userspace we can drop it for now. Signed-off-by:
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Samuel Pitoiset authored
Hardware signals index 0x00 are defined for some domains and they have to be allowed to enable sources like the others. Signed-off-by:
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Samuel Pitoiset authored
I thought that using TPC[0x0] like for G84:GT215 was sufficient on G80, but it's actually not the case. According to NVIDIA PerfKit on Windows, we have to configure PGRAPH related muxs on TPC[0x3] for this chipset. Signed-off-by:
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Samuel Pitoiset authored
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Ilia Mirkin authored
No known VBIOSes use these, but they are present in the actual VBIOS table parsing logic. No harm in adding these too. Signed-off-by:
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Alexandre Courbot authored
Allow the platform driver to recognize GM20B. Signed-off-by:
Alexandre Courbot <acourbot@nvidia.com> Signed-off-by:
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Alexandre Courbot authored
Recognize GM20B and assign the right engines and subdevs. Signed-off-by:
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Alexandre Courbot authored
Add support for GM20B's graphics engine, based on GK20A. Note that this code alone will not allow the engine to initialize on released devices which require PMU-assisted secure boot. Signed-off-by:
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Alexandre Courbot authored
GM20B has a 512-channels FIFO similar to GK104. Signed-off-by:
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Alexandre Courbot authored
GK20A's initialization was based on GK104, but differences exist in the way the initial context is built and the initialization process itself. This patch follows the same initialization sequence as nvgpu performs to avoid bad surprises. Since the register bundles initialization also differ considerably from GK104, the register packs are now loaded from firmware files, again similarly to what is done with nvgpu. Signed-off-by:
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Alexandre Courbot authored
NVIDIA will officially start providing GR firmwares through linux-firmware for GPUs that require it. Change the GR firmware lookup function to use these files. Signed-off-by:
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Samuel Pitoiset authored
These signals and sources have been reverse engineered from CUPTI (Linux). Graphics signals exposed by PerfKit (Windows only) will be added later. I need to reverse engineer them and it's a bit painful. Signed-off-by:
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Samuel Pitoiset authored
gk104_pm_ctor() is equal to gf100_pm_ctor(). Signed-off-by:
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Samuel Pitoiset authored
This trivial patch makes thing more consistent since hardware signals names are prefixed by 'pcXX'. Signed-off-by:
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Samuel Pitoiset authored
This is going to be very useful for GF100+ because each GPC can have its own domain of counters. Signed-off-by:
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Wei Ni authored
According to the tstate calculation in nvkm_clk_tstate(), the range of tstate is from -(clk->state_nr - 1) to 0, it mean the tstate is negative value. But in nvkm_pstate_work(), it use (clk->state_nr - 1 - clk->tstate) to limit pstate, it's not correct. This patch fix it to use (clk->state_nr - 1 + clk->tstate) to limit pstate. Signed-off-by:
Wei Ni <wni@nvidia.com> Signed-off-by:
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Samuel Pitoiset authored
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Samuel Pitoiset authored
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Samuel Pitoiset authored
These signals and sources have been reverse engineered from CUPTI (Linux). Graphics signals exposed by PerfKit (Windows only) will be added later. I need to reverse engineer them and it's a bit painful. This commit also adds a new class for GF108 and GF117. Signed-off-by:
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Samuel Pitoiset authored
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Ben Skeggs authored
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Ben Skeggs authored
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Samuel Pitoiset authored
These signals and sources have been reverse engineered from NVIDIA PerfKit (Windows) and CUPTI (Linux), they will be used to build complex hardware events from the userspace. This commit also adds a new class for GT200. Signed-off-by:
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Samuel Pitoiset authored
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com> Signed-off-by: -
Samuel Pitoiset authored
Configuring counters from the userspace require the kernel to handle some logic related to performance counters. Basically, it has to find a free slot to assign a counter, to handle extra counting modes like B4/B6 and it must return and error when it can't configure a counter. In my opinion, the kernel should not handle all of that logic but it should only write the configuration sent by the userspace without checking anything. In other words, it should overwrite the configuration even if it's already counting and do not return any errors. This patch allows the userspace to configure a domain instead of separate counters. This has the advantage to move all of the logic to the userspace. Signed-off-by:
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Samuel Pitoiset authored
This adds a new method NVIF_PERFCTR_V0_INIT which starts a batch of hardware counters for sampling. This will allow the userspace to start a monitoring session using the INIT method and to stop it with SAMPLE, for example before and after a frame is rendered. This commit temporarily breaks nv_perfmon but this is going to be fixed with the upcoming patch. Signed-off-by:
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Samuel Pitoiset authored
This allows to query the ID, the mask and the user-readable name of sources for each signal. Signed-off-by:
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Samuel Pitoiset authored
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Samuel Pitoiset authored
A source (or multiplexer) is a tuple addr+mask+shift which allows to control a block of signals. The maximum number of sources that a signal can define is arbitrary limited to 8 and this should be large enough. This patch allows to define multi-level of sources for a signal. Each different sources are stored to a global list and will be exposed to the userspace through the nvif interface in order to avoid conflicts. Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com> Signed-off-by: -
Samuel Pitoiset authored
This signal index must be always allowed even if it's not clearly defined in a domain in order to monitor a counter like 0x03020100 because it's the default value of signals. Signed-off-by:
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