- 28 May, 2016 34 commits
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James Hogan authored
To allow simplification of macros which use inline assembly to explicitly encode instructions, add a few simple abstractions to mipsregs.h which expand to specific microMIPS or normal MIPS encodings depending on what type of kernel is being built: _ASM_INSN_IF_MIPS(_enc) : Emit a 32bit MIPS instruction if microMIPS is not enabled. _ASM_INSN32_IF_MM(_enc) : Emit a 32bit microMIPS instruction if enabled. _ASM_INSN16_IF_MM(_enc) : Emit a 16bit microMIPS instruction if enabled. The macros can be used one after another since the MIPS / microMIPS macros are mutually exclusive, for example: __asm__ __volatile__( ".set push\n\t" ".set noat\n\t" "# mfgc0 $1, $%1, %2\n\t" _ASM_INSN_IF_MIPS(0x40610000 | %1 << 11 | %2) _ASM_INSN32_IF_MM(0x002004fc | %1 << 16 | %2 << 11) "move %0, $1\n\t" ".set pop" : "=r" (__res) : "i" (source), "i" (sel)); Signed-off-by:James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13310/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
As noticed by Sergei in the discussion of Andrea Gelmini's patch series. Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
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Andrea Gelmini authored
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Andrea Gelmini <andrea.gelmini@gelma.net> Cc: trivial@kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13338/Signed-off-by:
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Andrea Gelmini authored
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Andrea Gelmini authored
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Andrea Gelmini authored
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Andrea Gelmini authored
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Andrea Gelmini authored
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Andrea Gelmini authored
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Andrea Gelmini authored
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Andrea Gelmini authored
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Andrea Gelmini authored
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Andrea Gelmini authored
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Andrea Gelmini authored
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Andrea Gelmini authored
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Andrea Gelmini authored
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Andrea Gelmini authored
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Dan Carpenter authored
These should be ">=" instead of ">" or we go past the end of the pvc_lines[] array. Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Cc: linux-mips@linux-mips.org Cc: kernel-janitors@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/6124/Signed-off-by:
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Álvaro Fernández Rojas authored
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Álvaro Fernández Rojas <noltari@gmail.com> Cc: john@phrozen.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13308/Signed-off-by:
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Álvaro Fernández Rojas authored
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Álvaro Fernández Rojas authored
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James Hogan authored
The versions of the __write_{32,64}bit_gc0_register() macros for when there is no virt support in the assembler use the "J" inline asm constraint to allow integer zero, but this needs to be accompanied by the "z" formatting string so that it turns into $0. Fix both macros to do this. Fixes: bad50d79 ("MIPS: Fix VZ probe gas errors with binutils <2.24") Signed-off-by: -
Matt Redfearn authored
When starting secondary VPEs which support EVA and the SegCtl registers, copy the memory segmentation configuration from the running VPE to ensure that all VPEs in the core have a consistent virtual memory map. The EVA configuration of secondary cores is dealt with when starting the core via the CM. Signed-off-by:
Matt Redfearn <matt.redfearn@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13291/Signed-off-by:
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Matt Redfearn authored
The SegCtl registers are standard for MIPSr3..MIPSr5. Add definitions of these registers and use them rather than constants Signed-off-by:
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Purna Chandra Mandal authored
Update binding example based on new clock binding scheme. [1] Documentation/devicetree/bindings/clock/microchip,pic32.txt Signed-off-by:
Purna Chandra Mandal <purna.mandal@microchip.com> Acked-by:
Rob Herring <robh@kernel.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Kumar Gala <galak@codeaurora.org> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: linux-gpio@vger.kernel.org Cc: Mark Rutland <mark.rutland@arm.com> Cc: Alexandre Courbot <gnurou@gmail.com> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13270/Signed-off-by:
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Purna Chandra Mandal authored
Update binding example based on new clock binding scheme. [1] Documentation/devicetree/bindings/clock/microchip,pic32.txt Signed-off-by:
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Purna Chandra Mandal authored
Update binding example based on new clock binding scheme. [1] Documentation/devicetree/bindings/clock/microchip,pic32.txt Signed-off-by:
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Purna Chandra Mandal authored
Update binding example based on new clock binding scheme. [1] Documentation/devicetree/bindings/clock/microchip,pic32.txt Signed-off-by:
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Purna Chandra Mandal authored
Update binding example based on new clock binding scheme. [1] Documentation/devicetree/bindings/clock/microchip,pic32.txt Signed-off-by:
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Purna Chandra Mandal authored
Update binding example based on new clock binding documentation. [1] Documentation/devicetree/bindings/clock/microchip,pic32.txt Signed-off-by:
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James Hogan authored
Commit 12822570 ("MIPS: Separate XPA CPU feature into LPA and MVH") wasn't fully applied, possibly due to a conflict with commit f270d881 ("MIPS: Detect MIPSr6 Virtual Processor support"). This left decode_config5() referring to the non-existent MIPS_CPU_XPA, which breaks the build when XPA is enabled: arch/mips/kernel/cpu-probe.c In function ‘decode_config5’: arch/mips/kernel/cpu-probe.c:838:17: error: ‘MIPS_CPU_XPA’ undeclared (first use in this function) c->options |= MIPS_CPU_XPA; ^ Apply the missing hunk, dropping the CONFIG_XPA ifdef and setting the MIPS_CPU_MVH option when Config5.MVH is set. Fixes: 12822570 ("MIPS: Separate XPA CPU feature into LPA and MVH") Signed-off-by:
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Paul Burton authored
When EIC mode is in use (cpu_has_veic is true) enable it on each CPU during GIC initialisation. Otherwise there may be a mismatch between the hardware default interrupt model & that expected by the kernel. Signed-off-by:
Paul Burton <paul.burton@imgtec.com> Reviewed-by:
Thomas Gleixner <tglx@linutronix.de> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13274/Signed-off-by:
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Paul Burton authored
When using an external interrupt controller (EIC) the interrupt mask bits in the cop0 Status register are reused for the Interrupt Priority Level, and any interrupts with a priority lower than the field will be ignored. Clear the field to 0 by default such that all interrupts are serviced. Signed-off-by:
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Paul Burton authored
When using an external interrupt controller (EIC) the interrupt mask bits in the cop0 Status register are reused for the Interrupt Priority Level, and any interrupts with a priority lower than the field will be ignored. Clear the field to 0 by default such that all interrupts are serviced. Without doing so we default to arbitrarily ignoring all or some subset of interrupts. Signed-off-by:
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- 17 May, 2016 6 commits
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Purna Chandra Mandal authored
PIC32 clock driver is now implemented as platform driver instead of as part of of_clk_init(). It meants all the clock modules are available quite late in the boot sequence. So request for CPU clock by clk_get_sys() and clk_get_rate() to find c0_timer rate fails. To fix this use PIC32 specific early clock functions implemented for early console support. Signed-off-by:
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Felix Fietkau authored
ath79_ddr_pci_win_base has the type void __iomem *, so register offsets need to be a multiple of 4. Cc: Alban Bedel <albeu@free.fr> Fixes: 24b0e3e8 ("MIPS: ath79: Improve the DDR controller interface") Signed-off-by:
Felix Fietkau <nbd@nbd.name> Cc: sergei.shtylyov@cogentembedded.com Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13258/Signed-off-by:
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Felix Fietkau authored
AR913x, AR724x and AR933x are the only SoCs where the ath79_ddr_wb_flush_base starts at 0x7c, all newer SoCs use 0x9c Invert the logic to make the code compatible with AR95xx Signed-off-by:
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James Hogan authored
The VZ guest register & TLB access macros introduced in commit "MIPS: Add guest CP0 accessors" use VZ ASE specific instructions that aren't understood by versions of binutils prior to 2.24. Add a check for whether the toolchain supports the -mvirt option, similar to the MSA toolchain check, and implement the accessors using .word if not. Due to difficulty in converting compiler specified registers (e.g. "$3") to usable numbers (e.g. "3") in inline asm, we need to copy to/from a temporary register, namely the assembler temporary (at/$1), and specify guest CP0 registers numerically in the gc0 macros. Fixes: 7eb91118 ("MIPS: Add guest CP0 accessors") Signed-off-by:
Guenter Roeck <linux@roeck-us.net> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: linux-next@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13255/Signed-off-by:
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James Hogan authored
Fix perf hardware performance counter event numbers for I6400. This core does not follow the performance event numbering scheme of previous MIPS cores. All performance counters (both odd and even) are capable of counting any of the available events. Fixes: 4e88a862 ("MIPS: Add cases for CPU_I6400") Signed-off-by:
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Maciej W. Rozycki authored
Fix a modular `declance' regression caused by LMO commit bb46bf30d13f ("DECstation SCSI driver clean-ups.") Signed-off-by:Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13256/Signed-off-by:
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