- 26 Sep, 2018 40 commits
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Marcel Ziswiler authored
Move dr_mode property from USB PHY node to controller. Signed-off-by:
Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by:
Thierry Reding <treding@nvidia.com>
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Marcel Ziswiler authored
White-space clean-up. Signed-off-by:
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Marcel Ziswiler authored
Annotate UARTs and move the serial UART "nvidia,tegra30-hsuart" compatible definitions from the carrier board to the module level device trees. One could still override this in a custom carrier board device tree if required. Signed-off-by:
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Marcel Ziswiler authored
Add missing regulators: - reg_module_3v3_audio being VDDA supply of SGTL5000 - VDDD supply of SGTL5000 actually being reg_1v8_vio - reg_lan_v_bus being USB Ethernet chip vbus supply - carrier board HDMI supply being reg_5v0 - carrier board reg_3v3 actually being backlight and panel power supply Signed-off-by:
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Marcel Ziswiler authored
Just cosmetic regulator clean-up. Signed-off-by:
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Marcel Ziswiler authored
Reorder Host1x/HDMI properties. Signed-off-by:
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Marcel Ziswiler authored
Add empty local-mac-address property to be filled in by boot loader (e.g. U-Boot). Signed-off-by:
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Marcel Ziswiler authored
Support the V1.1 hardware revisions with the following change: Changed power rail for MMC1 interface to a 3.3V/1.8V switchable rail in order to be able to run UHS SD cards in ultra high speed 1.8V mode. [ 207.502011] mmc2: host does not support reading read-only switch, assuming write-enable [ 207.517011] mmc2: new ultra high speed SDR104 SDHC card at address aaaa [ 207.534190] mmcblk2: mmc2:aaaa SE32G 29.7 GiB [ 207.545096] mmcblk2: p1 root@apalis-t30:~# cat /sys/kernel/debug/mmc2/ios clock: 208000000 Hz actual clock: 204000000 Hz vdd: 21 (3.3 ~ 3.4 V) bus mode: 2 (push-pull) chip select: 0 (don't care) power mode: 2 (on) bus width: 2 (4 bits) timing spec: 6 (sd uhs SDR104) signal voltage: 1 (1.80 V) driver type: 0 (driver type B) root@apalis-t30:~# hdparm -t /dev/mmcblk2 /dev/mmcblk2: Timing buffered disk reads: 256 MB in 3.02 seconds = 84.71 MB/sec Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Marcel Ziswiler authored
Move the hda node from the carrier board to the module level device tree. Signed-off-by:
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Marcel Ziswiler authored
Fix the MCP2515 SPI CAN controller interrupt polarity which according to its datasheet defaults to low-active aka falling edge. Signed-off-by:
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Marcel Ziswiler authored
Rename a few nodes using more common names: - rename tps65911@2d to pmic@2d - rename stmpe811@41 to touchscreen@41 - rename tps62362@60 to regulator@60 Signed-off-by:
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Marcel Ziswiler authored
Rename hdmiddc to hdmi_ddc to be more in-line with other device trees. Signed-off-by:
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Marcel Ziswiler authored
The Apalis Evaluation Board uses Apalis GPIO7 on MXM3 pin 15 as reset signal for its PLX PEX 8605 PCIe Switch. Signed-off-by:
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Marcel Ziswiler authored
Drop obsolete spidev device tree nodes as nowadays one should do this by binding the spidev driver to specific instances/chip selects at runtime. Signed-off-by:
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Marcel Ziswiler authored
Drop model and compatible nodes from the module level device tree as they get overridden by the carrier board device tree anyway. Signed-off-by:
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Marcel Ziswiler authored
PLX Technology meanwhile got bought by Broadcom Corporation but the vendor prefix plx is still used in 8 current device trees. This silences the following checkpatch.pl warning: WARNING: DT compatible string vendor "plx" appears un-documented -- check ./Documentation/devicetree/bindings/vendor-prefixes.txt Signed-off-by:
Andreas Färber <afaerber@suse.de> Acked-by:
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Marcel Ziswiler authored
Line break long compatible property line. Signed-off-by:
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Marcel Ziswiler authored
Get rid of the fake clocks simple bus and use node names as per the actual schematics. Signed-off-by:
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Marcel Ziswiler authored
Add mmc-ddr-1_8v property enabling eMMC DDR52 mode. root@apalis-t30:~# cat /sys/kernel/debug/mmc1/ios clock: 52000000 Hz actual clock: 52000000 Hz vdd: 21 (3.3 ~ 3.4 V) bus mode: 2 (push-pull) chip select: 0 (don't care) power mode: 2 (on) bus width: 3 (8 bits) timing spec: 8 (mmc DDR52) signal voltage: 1 (1.80 V) driver type: 0 (driver type B) root@apalis-t30:~# hdparm -t /dev/mmcblk1 /dev/mmcblk1: Timing buffered disk reads: 232 MB in 3.01 seconds = 77.10 MB/sec Signed-off-by:
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Marcel Ziswiler authored
Add proper eMMC vmmc and vqmmc supplies e.g. fixing signalling voltage. Signed-off-by:
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Marcel Ziswiler authored
Add i2c-thermtrip which would set the DEV_OFF bit in the DCDC control register of the TPS65911 PMIC. Signed-off-by:
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Marcel Ziswiler authored
Further LM95245 temperature sensor annotation. Signed-off-by:
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Marcel Ziswiler authored
Use proper irq-gpio for stmpe811 touch controller. Signed-off-by:
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Marcel Ziswiler authored
Explicitly mux all T30 SoC balls now: - Apalis GPIO - Apalis HDMI1 - Apalis I2C1 - Apalis I2C2 (DDC) - Apalis LCD1 - Apalis Parallel Camera - Apalis SATA1_ACT# - Apalis SPDIF1 - Apalis TS (Low-speed type specific) - Apalis USBH_EN - Apalis USBH_OC# - Apalis VGA1 - on-module i210/i211 LAN control signals - not connected and therefore disabled signals Signed-off-by:
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Marcel Ziswiler authored
Clean-up pinmuxing: - white-space clean-up - explicitly disable input of BKL1_ON, BKL1_PWM and BKL1_PWM_EN# - annotate Apalis I2C3 usage for CAM - get rid of nvidia,lock property - add missing eMMC sdmmc4_cmd_pt7 and explicitly enable input - explicitly disable lcd_dc1_pd2 (e.g. LM95245 I2C address pin) - annotate TOUCH_PEN_INT# being on-module - As underscores in node names are not recommended replace them all where possible with dashes. Signed-off-by:
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Marcel Ziswiler authored
Drop pwmleds in favour of using regular PWMs. Signed-off-by:
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Marcel Ziswiler authored
Reorder backlight properties. Signed-off-by:
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Marcel Ziswiler authored
Move dr_mode property from USB PHY node to controller. Signed-off-by:
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Marcel Ziswiler authored
Annotate MMC1/SD1. Signed-off-by:
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Marcel Ziswiler authored
Drop unused mmc1/sd1 labels. Signed-off-by:
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Marcel Ziswiler authored
White-space and newline clean-up. Signed-off-by:
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Marcel Ziswiler authored
Drop unused cami2c label. Signed-off-by:
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Marcel Ziswiler authored
Annotate UARTs and move the serial UART "nvidia,tegra30-hsuart" compatible definitions from the carrier board to the module level device trees. One could still override this in a custom carrier board device tree if required. Signed-off-by:
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Marcel Ziswiler authored
Add missing regulators: - reg_module_3v3_audio being VDDA supply of SGTL5000 - VDDD supply of SGTL5000 actually being reg_1v8_vio - carrier board HDMI supply being reg_5v0 - carrier board reg_3v3 actually being backlight and panel power supply Signed-off-by:
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Marcel Ziswiler authored
Just cosmetic regulator clean-up. Signed-off-by:
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Marcel Ziswiler authored
Reorder Host1x/HDMI properties. Signed-off-by:
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Marcel Ziswiler authored
Annotate PCIe port nodes and clean-up PCIe controller/port status' with respect to carrier board vs. module level device trees. As port 3 connects to the on-module Gigabit Ethernet MACPHY it is always enabled together with the PCIe controller itself. Signed-off-by:
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Marcel Ziswiler authored
Reorder PCIe properties. Signed-off-by:
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Marcel Ziswiler authored
Add empty local-mac-address property to be filled in by boot loader (e.g. U-Boot). Signed-off-by:
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Marcel Ziswiler authored
In order to avoid any floating SD card detect pins as may e.g. happen on Ixora V1.1A pull them all up. Signed-off-by:
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