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  1. 22 May, 2020 2 commits
  3. 20 May, 2020 5 commits
  5. 19 May, 2020 1 commit
  7. 15 May, 2020 8 commits
    • Serge Semin's avatar
      spi: dw: Add Tx/Rx DMA properties · 7db097dc
      Serge Semin authored 
      Since commit 22d48ad7 ("spi: dw: Add Elkhart Lake PSE DMA support")
the spi-dw-mid.c module supports a platform DMA engine handling the DW APB
SSI controller requests. Lets alter the DW SPI bindings file to accept the
Rx and Tx DMA line specifiers.
Signed-off-by: default avatarSerge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Cc: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Allison Randal <allison@lohutok.net>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Gareth Williams <gareth.williams.jx@renesas.com>
Cc: linux-mips@vger.kernel.org
Link: https://lore.kernel.org/r/20200515104758.6934-2-Sergey.Semin@baikalelectronics.ruSigned-off-by: default avatarMark Brown <broonie@kernel.org>
      7db097dc
    • Mark Brown's avatar
      Merge series "spi: dw: Add generic DW DMA controller support" from Serge Semin... · b271cf33
      Mark Brown authored 
      Merge series "spi: dw: Add generic DW DMA controller support" from Serge Semin <Sergey.Semin@baikalelectronics.ru>:

Baikal-T1 SoC provides a DW DMA controller to perform low-speed peripherals
Mem-to-Dev and Dev-to-Mem transaction. This is also applicable to the DW
APB SSI devices embedded into the SoC. Currently the DMA-based transfers
are supported by the DW APB SPI driver only as a middle layer code for
Intel MID/Elkhart PCI devices. Seeing the same code can be used for normal
platform DMAC device we introduced a set of patches to fix it within this
series.

First of all we need to add the Tx and Rx DMA channels support into the DW
APB SSI binding. Then there are several fixes and cleanups provided as a
initial preparation for the Generic DMA support integration: add Tx/Rx
finish wait methods, clear DMAC register when done or stopped, Fix native
CS being unset, enable interrupts in accordance with DMA xfer mode,
discard static DW DMA slave structures, discard unused void priv pointer
and dma_width member of the dw_spi structure, provide the DMA Tx/Rx burst
length parametrisation and make sure it's optionally set in accordance
with the DMA max-burst capability.

In order to have the DW APB SSI MMIO driver working with DMA we need to
initialize the paddr field with the physical base address of the DW APB SSI
registers space. Then we unpin the Intel MID specific code from the
generic DMA one and placed it into the spi-dw-pci.c driver, which is a
better place for it anyway. After that the naming cleanups are performed
since the code is going to be used for a generic DMAC device. Finally the
Generic DMA initialization can be added to the generic version of the
DW APB SSI IP.

Last but not least we traditionally convert the legacy plain text-based
dt-binding file with yaml-based one and as a cherry on a cake replace
the manually written DebugFS registers read method with a ready-to-use
for the same purpose regset32 DebugFS interface usage.

This patchset is rebased and tested on the spi/for-next (5.7-rc5):
base-commit: fe9fce6b2cf3 ("Merge remote-tracking branch 'spi/for-5.8' into spi-next")
Co-developed-by: default avatarGeorgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Signed-off-by: default avatarGeorgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Co-developed-by: default avatarRamil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Signed-off-by: default avatarRamil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Signed-off-by: default avatarSerge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Maxim Kaurkin <Maxim.Kaurkin@baikalelectronics.ru>
Cc: Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>
Cc: Ekaterina Skachko <Ekaterina.Skachko@baikalelectronics.ru>
Cc: Vadim Vlasov <V.Vlasov@baikalelectronics.ru>
Cc: Alexey Kolotnikov <Alexey.Kolotnikov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Allison Randal <allison@lohutok.net>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Gareth Williams <gareth.williams.jx@renesas.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: linux-spi@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org

---

Changelog v2:
- Rebase on top of the spi repository for-next branch.
- Move bindings conversion patch to the tail of the series.
- Move fixes to the head of the series.
- Apply as many changes as possible to be applied the Generic DMA
  functionality support is added and the spi-dw-mid is moved to the
  spi-dw-dma driver.
- Discard patch "spi: dw: Fix dma_slave_config used partly uninitialized"
  since the problem has already been fixed.
- Add new patch "spi: dw: Discard unused void priv pointer".
- Add new patch "spi: dw: Discard dma_width member of the dw_spi structure".
  n_bytes member of the DW SPI data can be used instead.
- Build the DMA functionality into the DW APB SSI core if required instead
  of creating a separate kernel module.
- Use conditional statement instead of the ternary operator in the ref
  clock getter.

Serge Semin (19):
  dt-bindings: spi: dw: Add Tx/Rx DMA properties
  spi: dw: Add Tx/Rx finish wait methods to the MID DMA
  spi: dw: Clear DMAC register when done or stopped
  spi: dw: Fix native CS being unset
  spi: dw: Enable interrupts in accordance with DMA xfer mode
  spi: dw: Discard static DW DMA slave structures
  spi: dw: Discard unused void priv pointer
  spi: dw: Discard dma_width member of the dw_spi structure
  spi: dw: Parameterize the DMA Rx/Tx burst length
  spi: dw: Use DMA max burst to set the request thresholds
  spi: dw: Initialize paddr in DW SPI MMIO private data
  spi: dw: Fix Rx-only DMA transfers
  spi: dw: Move Non-DMA code to the DW PCIe-SPI driver
  spi: dw: Remove DW DMA code dependency from DW_DMAC_PCI
  spi: dw: Add DW SPI DMA/PCI/MMIO dependency on the DW SPI core
  spi: dw: Cleanup generic DW DMA code namings
  spi: dw: Add DMA support to the DW SPI MMIO driver
  spi: dw: Use regset32 DebugFS method to create regdump file
  dt-bindings: spi: Convert DW SPI binding to DT schema

 .../bindings/spi/snps,dw-apb-ssi.txt          |  42 ---
 .../bindings/spi/snps,dw-apb-ssi.yaml         | 127 +++++++++
 .../devicetree/bindings/spi/spi-dw.txt        |  24 --
 drivers/spi/Kconfig                           |  15 +-
 drivers/spi/Makefile                          |   7 +-
 drivers/spi/{spi-dw-mid.c => spi-dw-dma.c}    | 257 ++++++++++--------
 drivers/spi/spi-dw-mmio.c                     |   9 +-
 drivers/spi/spi-dw-pci.c                      |  50 +++-
 drivers/spi/spi-dw.c                          |  98 +++----
 drivers/spi/spi-dw.h                          |  33 ++-
 10 files changed, 405 insertions(+), 257 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
 create mode 100644 Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
 delete mode 100644 Documentation/devicetree/bindings/spi/spi-dw.txt
 rename drivers/spi/{spi-dw-mid.c => spi-dw-dma.c} (53%)

--
2.25.1
      b271cf33
    • Chris Ruehl's avatar
      spi: spi-rockchip: use num-cs property and ctlr->enable_gpiods · eb1262e3
      Chris Ruehl authored 
      The original implementation set num_chipselect to ROCKCHIP_SPI_MAX_CS_NUM (2)
which seems wrong here. spi0 has 2 native cs, all others just one. With
enable and use of cs_gpiods / GPIO CS, its correct to set the num_chipselect
from the num-cs property and set max_native_cs with the define.
If num-cs is missing the default set to num_chipselect = 1.
Signed-off-by: default avatarChris Ruehl <chris.ruehl@gtsys.com.hk>
Link: https://lore.kernel.org/r/20200511083022.23678-4-chris.ruehl@gtsys.com.hkSigned-off-by: default avatarMark Brown <broonie@kernel.org>
      eb1262e3
    • Chris Ruehl's avatar
      spi: spi-rockchip: add support for spi slave mode · d065f41a
      Chris Ruehl authored 
      Add support for spi slave mode in spi-rockchip. The register map has an entry
for it. If spi-slave is set in dts, set this corresponding bit and add to
mode_bits the SPI_NO_CS, allow slave mode without explicit CS use.
Slave abort function had been added.
Signed-off-by: default avatarChris Ruehl <chris.ruehl@gtsys.com.hk>
Link: https://lore.kernel.org/r/20200511083022.23678-3-chris.ruehl@gtsys.com.hkSigned-off-by: default avatarMark Brown <broonie@kernel.org>
      d065f41a
    • Chris Ruehl's avatar
      spi: spi-rockchip: cleanup use struct spi_controller · d66571a2
      Chris Ruehl authored 
      Cleanup, move from the compatibily layer struct spi_master over
to struct spi_controller, and rename the related function calls.
Signed-off-by: default avatarChris Ruehl <chris.ruehl@gtsys.com.hk>
Link: https://lore.kernel.org/r/20200511083022.23678-2-chris.ruehl@gtsys.com.hkSigned-off-by: default avatarMark Brown <broonie@kernel.org>
      d66571a2
    • Serge Semin's avatar
      spi: dw: Clear DMAC register when done or stopped · 0327f0b8
      Serge Semin authored 
      If DMAC register is left uncleared any further DMAless transfers
may cause the DMAC hardware handshaking interface getting activated.
So the next DMA-based Rx/Tx transaction will be started right
after the dma_async_issue_pending() method is invoked even if no
DMATDLR/DMARDLR conditions are met. This at the same time may cause
the Tx/Rx FIFO buffers underrun/overrun. In order to fix this we
must clear DMAC register after a current DMA-based transaction is
finished.
Co-developed-by: default avatarGeorgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Signed-off-by: default avatarGeorgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Signed-off-by: default avatarSerge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20200515104758.6934-4-Sergey.Semin@baikalelectronics.ruSigned-off-by: default avatarMark Brown <broonie@kernel.org>
      0327f0b8
    • Serge Semin's avatar
      spi: dw: Initialize paddr in DW SPI MMIO private data · 77810d48
      Serge Semin authored 
      This field is used only for the DW SPI DMA code initialization, that's
why there were no problems with it being uninitialized in Dw SPI MMIO
driver. Since in a further patch we are going to introduce the DW SPI DMA
support in the MMIO version of the driver, lets set the field with the
physical address of the DW SPI controller registers region.
Co-developed-by: default avatarGeorgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Co-developed-by: default avatarRamil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Signed-off-by: default avatarGeorgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Signed-off-by: default avatarRamil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Signed-off-by: default avatarSerge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20200515104758.6934-12-Sergey.Semin@baikalelectronics.ruSigned-off-by: default avatarMark Brown <broonie@kernel.org>
      77810d48
    • Serge Semin's avatar
      spi: dw: Fix native CS being unset · 9aea644c
      Serge Semin authored 
      Commit 6e0a32d6 ("spi: dw: Fix default polarity of native
chipselect") attempted to fix the problem when GPIO active-high
chip-select is utilized to communicate with some SPI slave. It fixed
the problem, but broke the normal native CS support. At the same time
the reversion commit ada9e3fc ("spi: dw: Correct handling of native
chipselect") didn't solve the problem either, since it just inverted
the set_cs() polarity perception without taking into account that
CS-high might be applicable. Here is what is done to finally fix the
problem.

DW SPI controller demands any native CS being set in order to proceed
with data transfer. So in order to activate the SPI communications we
must set any bit in the Slave Select DW SPI controller register no
matter whether the platform requests the GPIO- or native CS. Preferably
it should be the bit corresponding to the SPI slave CS number. But
currently the dw_spi_set_cs() method activates the chip-select
only if the second argument is false. Since the second argument of the
set_cs callback is expected to be a boolean with "is-high" semantics
(actual chip-select pin state value), the bit in the DW SPI Slave
Select register will be set only if SPI core requests the driver
to set the CS in the low state. So this will work for active-low
GPIO-based CS case, and won't work for active-high CS setting
the bit when SPI core actually needs to deactivate the CS.

This commit fixes the problem for all described cases. So no matter
whether an SPI slave needs GPIO- or native-based CS with active-high
or low signal the corresponding bit will be set in SER.
Signed-off-by: default avatarSerge Semin <Sergey.Semin@baikalelectronics.ru>
Fixes: ada9e3fc ("spi: dw: Correct handling of native chipselect")
Fixes: 6e0a32d6 ("spi: dw: Fix default polarity of native chipselect")
Reviewed-by: default avatarCharles Keepax <ckeepax@opensource.cirrus.com>
Reviewed-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: default avatarLinus Walleij <linus.walleij@linaro.org>

Link: https://lore.kernel.org/r/20200515104758.6934-5-Sergey.Semin@baikalelectronics.ruSigned-off-by: default avatarMark Brown <broonie@kernel.org>
      9aea644c
  9. 12 May, 2020 2 commits
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  13. 07 May, 2020 2 commits
  15. 06 May, 2020 10 commits
  17. 05 May, 2020 6 commits
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