- 01 Jul, 2020 40 commits
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Yongqiang Sun authored
[Why & How] Add emul specific hw function to dmub, in case of emulator is created, we can runtime switch between dmub emulator or dmub uC via is_virtual flag in dmub. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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po-tchen authored
[Why] The SDP deadline indicate the vertical time to send CRC infopacket in PSR. Signed-off-by:
po-tchen <po-ting.chen@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Martin Tsai authored
[Why] Some sprcified monitor scalar cannot recognize timing change on demand. Once the link phy disable and enable during a short period then the Sink protection mechanism could keep the screen in blank and cannot be recoverred. [How] To add 100ms delay between enable link phy and link training. Signed-off-by:
Martin Tsai <martin.tsai@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
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Aric Cyr authored
Signed-off-by:
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Anthony Koo authored
[Header Changes] - Add SDP transmission deadline for PSR config cmd Signed-off-by: -
Charlene Liu authored
[why] for audio on real TV issue. [how] -add wall clock programming for DPREF based when Pixel clock is done by DP DTO. Signed-off-by:
Charlene Liu <Charlene.Liu@amd.com> Reviewed-by:
Chris Park <Chris.Park@amd.com> Acked-by:
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Nicholas Kazlauskas authored
[Why] DML failures occur for 420 modes with dynamic pipe splitting enabled because the ChromaViewport exceeds the ChromaSurfaceWidth. This is caused by adding the viewport_width instead of the viewport_width_c. This similarly occurs for rotated modes due to the use of viewport_height instead of viewport_height_c. [How] Correct the calculations. Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Hugo Hu authored
This reverts commmit fd0293dd. Signed-off-by:
Hugo Hu <hugo.hu@amd.com> Reviewed-by:
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Roman Li authored
[Why] SOC_BOUNDING_BOX_VALID is unused and not required for dcn21. [How] Remove it. Signed-off-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by:
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Nicholas Kazlauskas authored
[Why] DSC calculations fail because the u16 bits_per_pixel from the DRM struct is being casted to the u8 drm_bpp parameters and locals. Integer wraparound is happening because this value is greater than 255. [How] Use u16 to match what's in the structure instead of u8. Signed-off-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by:
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Wesley Chalmers authored
[WHY] Disabling DPG should happen after setting watermarks and clocks Signed-off-by:
Wesley Chalmers <wchalmer@amd.com> Reviewed-by:
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Anthony Koo authored
[Header Changes] - Version bump to 1.0.13 Signed-off-by: -
Michael Strauss authored
[WHY] Typos cause bandwidth calculation errors, one of which can cause infinite loop on dcn1 with eDP Signed-off-by:
Michael Strauss <michael.strauss@amd.com> Reviewed-by:
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Rodrigo Siqueira authored
When we want to use float point operation on Linux we need to use within special kernel protection (`kernel_fpu_{begin,end}()`.), otherwise the kernel can clobber userspace FPU register state. For detecting these issues we use a tool named objtool (with -Ffa flags) to highlight the FPU problems, all warnings can be summed up as follows: ./tools/objtool/objtool check -Ffa drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.o [..] dc/dsc/rc_calc.o: warning: objtool: get_qp_set()+0x2f8: FPU instruction outside of kernel_fpu_{begin,end}() [..] dc/dsc/rc_calc.o: warning: objtool: dsc_roundf()+0x5: FPU instruction outside of kernel_fpu_{begin,end}() [..] dc/dsc/rc_calc.o: warning: objtool: dsc_ceil()+0x5: FPU instruction outside of kernel_fpu_{begin,end}() [..] dc/dsc/rc_calc.o: warning: objtool: get_ofs_set()+0x3eb: FPU instruction outside of kernel_fpu_{begin,end}() [..] dc/dsc/rc_calc.o: warning: objtool: calc_rc_params()+0x3c: FPU instruction outside of kernel_fpu_{begin,end}() [..] dc/dsc/dc_dsc.o: warning: objtool: get_dsc_bandwidth_range.isra.0()+0x8d: FPU instruction outside of kernel_fpu_{begin,end}() [..] dc/dsc/dc_dsc.o: warning: objtool: setup_dsc_config()+0x2ef: FPU instruction outside of kernel_fpu_{begin,end}() [..] dc/dsc/rc_calc_dpi.o: warning: objtool:copy_pps_fields()+0xbb: FPU instruction outside of kernel_fpu_{begin,end}() [..] dc/dsc/rc_calc_dpi.o: warning: objtool: dscc_compute_dsc_parameters()+0x7b: FPU instruction outside of kernel_fpu_{begin,end}() This commit fixes the above issues by rework DSC as described: 1. Isolate all FPU operations in a single file; 2. Use FPU flags only in the file that handles FPU operations; 3. Isolate all functions that require float point operation in static functions; 4. Add a mid-layer function that does not use any float point operation, and that could be safely invoked in other parts of the code. 5. Keep float point operation under DC_FP_{START/END} macro. CC: Christian König <christian.koenig@amd.com> CC: Alexander Deucher <Alexander.Deucher@amd.com> CC: Peter Zijlstra <peterz@infradead.org> CC: Tony Cheng <tony.cheng@amd.com> CC: Harry Wentland <hwentlan@amd.com> Signed-off-by:Mikita Lipski <Mikita.Lipski@amd.com> Acked-by:
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Charlene Liu authored
[why] for following new format, no alpha SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT/_FIX: SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT/_FIX same as case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: Signed-off-by: -
Tom St Denis authored
Even though they are technically MMIO registers I put the bits with the sqind block for organizational purposes. Requested for UMR debugging. Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
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James Zhu authored
Fix race condition issue when multiple jpeg starts are called. Signed-off-by:
James Zhu <James.Zhu@amd.com> Acked-by:
Nirmoy Das <nirmoy.das@amd.com> Reviewed-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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Emily Deng authored
As will clear vf fw during unload driver, to avoid idle fail. Need to clear KIQ portion also. Signed-off-by:
Emily Deng <Emily.Deng@amd.com> Ack-by:
Monk.liu <monk.liu@amd.com> Signed-off-by:
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Emily Deng authored
Signed-off-by:
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Emily Deng authored
Guest VM issue the PSP clear_vf_fw command at 2 points: 1.On VF driver loading, after VF message PSP to setup rings, the next command is “clear_vf_fw” 2.On VF driver unload before VF message to destroy rings Signed-off-by:
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Prike.Liang authored
Fixes: c1cf79ca ("drm/amdgpu: use IP discovery table for renoir") This nullptr issue should be specific on the Renoir series during try access the PWR_MISC_CNTL_STATUS when PWR IP not been detected by discovery table. Moreover the PWR IP not existing in Renoir series is expected therefore just avoid access PWR register in Renoir series. Signed-off-by:
Prike.Liang <Prike.Liang@amd.com> Acked-by:
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Sandeep Raghuraman authored
Initializes Powertune data for a specific Hawaii card by fixing what looks like a typo in the code. The device ID 66B1 is not a supported device ID for this driver, and is not mentioned elsewhere. 67B1 is a valid device ID, and is a Hawaii Pro GPU. I have tested on my R9 390 which has device ID 67B1, and it works fine without problems. Signed-off-by:
Sandeep Raghuraman <sandy.8925@gmail.com> Signed-off-by:
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Dan Carpenter authored
The comments say that the serial number is a 16-digit HEX string so the buffer needs to be at least 17 characters to hold the NUL terminator. The other issue is that "size" returned from sprintf() is the number of characters before the NUL terminator so the memcpy() wasn't copying the terminator. The serial number needs to be NUL terminated so that it doesn't lead to a read overflow in amdgpu_device_get_serial_number(). Also it's just cleaner and faster to sprintf() directly to adev->serial[] instead of using a temporary buffer. Fixes: 81a16241 ("drm/amdgpu: Add unique_id and serial_number for Arcturus v3") Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
Evan Quan <evan.quan@amd.com>
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Evan Quan authored
Move the common code to amdgpu_smu.c instead of having one copy in both smu_v11_0.c and smu_v12_0.c. Signed-off-by:
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Evan Quan authored
Update the calling chain from "amdgpu_smu.c -> ${asic}_ppt.c -> smu_v11/12_0.c -> amdgpu_smu.c (smu_common_read_sensor())" to " "amdgpu_smu.c -> ${asic}_ppt.c -> smu_v11/12_0.c". This can help to maintain clear code layers. More similar changes will be coming. Signed-off-by: -
Evan Quan authored
Since SMU_MSG_GetDpmClockFreq is known to be supported for Vega20 and before ASICs only. For those ASICs supporting swSMU, it is not supported. Signed-off-by:
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Evan Quan authored
Since .populate_smc_tables is just a wrapper of .set_default_dpm_table. Signed-off-by:
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Evan Quan authored
It has exactly the same functionality as .set_deep_sleep_dcefclk. V2: correct the macro name for better trace Signed-off-by:
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Colton Lewis authored
Silence documentation warnings by correcting kernel-doc comments. ./drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:3388: warning: Excess function parameter 'suspend' description in 'amdgpu_device_suspend' ./drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:3485: warning: Excess function parameter 'resume' description in 'amdgpu_device_resume' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:418: warning: Excess function parameter 'tbo' description in 'amdgpu_vram_mgr_del' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:418: warning: Excess function parameter 'place' description in 'amdgpu_vram_mgr_del' ./drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c:279: warning: Excess function parameter 'tbo' description in 'amdgpu_gtt_mgr_del' ./drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c:279: warning: Excess function parameter 'place' description in 'amdgpu_gtt_mgr_del' ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:332: warning: Function parameter or member 'hdcp_workqueue' not described in 'amdgpu_display_manager' ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:332: warning: Function parameter or member 'cached_dc_state' not described in 'amdgpu_display_manager' Signed-off-by:
Colton Lewis <colton.w.lewis@protonmail.com> Signed-off-by:
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Tom St Denis authored
Requested for UMR support. (v2): Also add reg/bits for gfx9 headers Signed-off-by:
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Liu ChengZhe authored
if guest driver failed to enter full GPU access, amdgpu_driver_load_kms will unload kms and free dev->dev_private, drm_dev_register would access null pointer. Driver will enter an error state and can't be unloaded. Signed-off-by:
Liu ChengZhe <ChengZhe.Liu@amd.com> Reviewed-by:
Madhav Chauhan <madhav.chauhan@amd.com> Signed-off-by:
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Evan Quan authored
Since DAL settings come between .hw_init and .late_init of SMU. And DAL needs to know the maximum sustainable clocks. Signed-off-by:
Flora Cui <flora.cui@amd.com> Acked-by:
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Evan Quan authored
Before counting the OD percent into max power limit margin. Signed-off-by:
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Evan Quan authored
Instead of hard coding it as SMU_POWER_SOURCE_AC. Signed-off-by:
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Evan Quan authored
Drop unused APIs, variables and argument. Signed-off-by:
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Evan Quan authored
Use the cached max/current power limit and move the input check to the top layer. Signed-off-by:
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Evan Quan authored
Use the cached max/current power limit for other cases except .late_init. Signed-off-by:
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Evan Quan authored
Also cache the current and max power limits. Signed-off-by:
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Evan Quan authored
Minor code cleanup. Signed-off-by:
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Evan Quan authored
'UVD' is a HW engine name for Vega20 and before ASICs. For newer ASICs, the similar engine is named as 'VCN'. Signed-off-by:
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