- 18 Jul, 2019 40 commits
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Tony Cheng authored
Signed-off-by:
Tony Cheng <tony.cheng@amd.com> Reviewed-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Fatemeh Darbehani authored
For some platforms, we need to know SMU version for driver/SMU compatibility. This change adds that field. Signed-off-by:
Fatemeh Darbehani <fatemeh.darbehani@amd.com> Reviewed-by:
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Jun Lei authored
[why] Existing support in DC for pstate only accounts for a single latency. This is sufficient when the variance of latency is small, or that pstate support isn't necessary for correct ASIC functionality. Newer ASICs violate both existing assumptions. PState support is mandatory of correct ASIC functionality, but not all latencies have to be supported. Existing code supports a "full p state" which allows memory clock to change, but is hard for DCN to support (as it requires very large buffers). New code will now fall back to a "dummy p state" support when "full p state" cannot be support. This easy p state support should always be allowed. [how] Define a new latency in socBB. Add fallback logic to support it. Note DML is also updated to ensure that fallback will always work. Signed-off-by:
Jun Lei <Jun.Lei@amd.com> Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Eric Yang authored
[Why] In DCN2x asic, the MPCC status register definition changed, and our logic for assert is incorrect. disabled is valid state, where we should see idle and not busy, where as in not disabled state, we should see not idle. [How] Change assert condition to be more sensible. Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Reviewed-by:
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Eric Yang authored
[Why] Previously assume eDP sink present if connector present. Do not need to enforce this restriction. Fix issue where driver attempt to read link setting even though no edp connected. {How] Only read link setting after reading connection status. Signed-off-by: -
Tai Man authored
[Why] The audios array defined in "struct resource_pool" is only 6 (MAX_PIPES) but the max number of audio devices (num_audio) is 7. In some projects, it will run out of audios array. [How] Incraese the audios array size to 7. Signed-off-by:
Tai Man <taiman.wong@amd.com> Reviewed-by:
Joshua Aberback <Joshua.Aberback@amd.com> Acked-by:
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Aric Cyr authored
Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
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Zhan Liu authored
[Why] For boards that support eDP but do not have a physical eDP display connected an ASSERT will be thrown. This is not a critical failure and shouldn't be treated as such. [How] Drop the assertion. Signed-off-by:
Zhan Liu <zhan.liu@amd.com> Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
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Nicholas Kazlauskas authored
[Why] In an effort to stop redundant calls to dce110_disable_audio_stream the audio->enabled flag was added to the audio resource struct. While this state probably shouldn't have been tracked on the audio struct itself it still works fine for some sequences. However, it does not work for cases where we're freeing the audio resource (such as hotplugs) or when dynamic audio is enabled. In these cases the pipe_ctx->stream_res.audio = NULL before we can set audio->enabled = false. The next time we acquire the audio resource such as on hotplug the audio will not be enabled for the stream since DC thinks it's still enabled. Audio state tracking should cover this sequence. [How] Set audio->enabled = false at the start as long as we have pipe_ctx->stream_res.audio. Signed-off-by:
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Julian Parkin authored
[Why] Code to enable DCN20 dynamic metadata feature is duplicated in two places and was added to DCE110 enable stream. [How] Create DCN20 specific enable stream function for clarity, and add a hardware sequencer function to program dynamic metadata to avoid the duplicate code. Signed-off-by:
Julian Parkin <julian.parkin@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
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Alvin Lee authored
[Why] In dm_helpers_parse_edid_caps, there is a corner case where no speakers can be allocated even though the audio mode count is greater than 0. Enabling audio when no speaker allocations exists can cause issues in the video stream. [How] Add a check to not enable audio unless one or more speaker allocations exist (since doing this can cause issues in the video stream). Signed-off-by:
Alvin Lee <alvin.lee2@amd.com> Reviewed-by:
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Julian Parkin authored
[Why] It is possible (but very unlikely) that constructing dc fails before current_state is created. We support 666 color depth in some scenarios, but this isn't handled in get_norm_pix_clk. It uses exactly the same pixel clock as the 888 case. [How] Check for non null current_state before destructing. Add case for 666 color depth to get_norm_pix_clk to avoid assertion. Signed-off-by:
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Jun Lei authored
[why] update_bounding_box calculates intermediate bb states based on clock relationship however, the last state doesn't need to maintain a minimum relationship, but should actually contain maximum of every clock. otherwise maximum clocks are not usable [how] once the calculated bb is built, override the last state with max values Signed-off-by:
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Dmytro Laktyushkin authored
Add dual plane dcc programming support for surfaces. Removes unions from plane size and dcc params as they serve no practical purpose only making our code more convoluted. This results in easy dual plane dcc and surface size programming. Temporary diags_dm code is used to handle the interface change without breaking functionality as a diags change needs to be applied after this one. Signed-off-by:
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Reza Amini authored
[WHY] Users want to not have filtering when scaling by integer multiples to native timing. [HOW] If timing is a multiple integer of view, we set number of taps to 1 (effectivly closest neighbour). Signed-off-by:
Reza Amini <Reza.Amini@amd.com> Reviewed-by:
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Dingchen Zhang authored
[Why] need to verify the impact of spatial dithering on 8bpc bypass mode. [How] added CRC sources and configure dihter option from dc stream. Signed-off-by:
Dingchen Zhang <dingchen.zhang@amd.com> Reviewed-by:
Hanghong Ma <Hanghong.Ma@amd.com> Acked-by:
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Dmytro Laktyushkin authored
This allows to set a minimum display and dpp clock on dcn2+ HW by adjusting clocks used for dml calculations. Signed-off-by:
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Charlene Liu authored
[Description] This is for HW negative stress testing use. force reset the dispclk and dppclk even the same clock already set in HW. Signed-off-by:
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Murton Liu authored
id_to_offset does not point to the same reg offset that offset_to_id checks for, causing unintended asserts Signed-off-by:
Murton Liu <murton.liu@amd.com> Reviewed-by:
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Charlene Liu authored
add dc_set_clock add dc_get_clock this is for testing and diagnostics to get/set DPPCLK and DISPCLK. Signed-off-by:
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Derek Lai authored
[Why] Driver will create 0, 1, and 2 ddc engines for RV2, but some platforms used 0, 1, and 3. [How] Still allocate 4 ddc engines for RV2. Signed-off-by:
Derek Lai <Derek.Lai@amd.com> Reviewed-by:
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Murton Liu authored
[Why] Implementation of stereo mux register is complete, but unused. Need to call functions to write relevant configs. [How] Add function to write stereo config for enable/disable case and call in stereo control interface. Signed-off-by:
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Aric Cyr authored
Signed-off-by:
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Ilya Bakoulin authored
[Why] Alpha could be improperly applied (only affecting half the frame) for some source pixel formats. [How] Change how alpha is enabled in MPC/DPP LB and change the bottom plane blend mode in MPC. Signed-off-by:
Ilya Bakoulin <Ilya.Bakoulin@amd.com> Reviewed-by:
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Ilya Bakoulin authored
For clarity, save the use_pitch_c logic to a bool Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Acked-by:
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Nevenko Stupar authored
Add this register for future use Signed-off-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Reviewed-by:
Vitaly Prosyak <vitaly.prosyak@amd.com> Acked-by:
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Qingqing Zhuo authored
[Why] bypass CM block and MPC ogam for debug or triage use. [How] create a new flag cm_bypass_mode, which will set both CM_CONTROL and MPCC_OGAM_MODE to bypass when set to 1. Signed-off-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Reviewed-by:
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Vitaly Prosyak authored
[Why & How] Number of 3DLUT's in MPC are not equal to number of pipes. Resource management is required. Activate on FPGA entire tm solution which includes the following :hdr multiplier, shaper, 3dlut. Signed-off-by:
Gary Kattan <Gary.Kattan@amd.com> Acked-by:
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Joshua Aberback authored
[Why] We want a debug option to disable timing sync for testing. [How] New dc debug option that must be false to call program_timing_sync Signed-off-by:
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Nikola Cornij authored
[why] As a fail-safe, in case 'set FEC_READY' DPCD write fails, a HW shadow register should be cleared and the internal FEC stat should be set to 'not ready'. This is to make sure HW settings will be consistent with FEC_READY state on the RX. Signed-off-by:
Nikola Cornij <nikola.cornij@amd.com> Reviewed-by:
Chris Park <Chris.Park@amd.com> Acked-by:
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Krunoslav Kovac authored
[Why&How] 1. Stack usage is pretty high as fixed31_32 struct is 8 bytes and we have functions with >30 vars on the stack. 2. Optimize gamma calculation by reducing number of calls to dc_fixpt_pow Our X points are divided into 32 regions wth 16 pts each. Each region is 2x the previous, meaning x[i] = 2*x[i-16] for i>=16. Using (2x)^gamma = 2^gamma * x^gamma, we can recursively compute powers of gamma, we just need first 16 pts to start it up. dc_fixpt_pow() is expensive, it computes x^y by doing exp(y*logx) Exp is done by Taylor series approximation, and log by Newton-like approximation that also uses exp internally. In short, it's significantly heavier than run-of-the-mill addition/subtraction/multiply. Signed-off-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Eric Yang authored
[Why] Seamless boot optimization removed proper front end power off sequence. In driver disable enable case, this causes driver to power gate hubp and dpp while there is still memory fetching going on, this can cause invalid memory requests to be generated which will hang data fabric. [How] Put back proper front end power off sequence Signed-off-by:
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Nikola Cornij authored
[why] Right now we FEC_READY is set only before the final link training, i.e. at mode set time. This means FEC_READY won't be set when doing link training as a response to HPD. It also fails UCD400 FEC test in DP compliance. [how] Move FEC_READY setup to link training. Signed-off-by:
Abdoulaye Berthe <Abdoulaye.Berthe@amd.com> Acked-by:
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Eric Bernstein authored
Use helper to determine if HDMI signal when processing avmute. Signed-off-by:
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Murton Liu authored
[Why] Logic & structures for generic regs does not exist in DC currently. [How] Implement register masks/shifts and relevant functions for generic mux, similar to existing HPD and DDC objects. V2: fix includes for kalloc/free (Alex) Signed-off-by:
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Alvin Lee authored
[why] In pipe split issue occurs when we program immediate flip while vsync flip is pending [how] Don't program immediate flip until flip is no longer pending Signed-off-by:
Jaehyun Chung <Jaehyun.Chung@amd.com> Acked-by:
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Aric Cyr authored
Signed-off-by:
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Fatemeh Darbehani authored
[Why] Some display's hsync width is lower than the minimum dcn20 is set to support right now. This will cause optc1_validate_timing to fail which eventually will result in wrong set mode. This was set to 8 as per HW team's request for no valid reason. [How] Changing min_h_sync_width to 4 will let us validate timing for preffered mode and light up the headset. This change was made to Vega 10 before for a similar issue. Signed-off-by:
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Alvin Lee authored
[why] We initialize pp_smu twice [how] Remove second initialization of pp_smu Signed-off-by:
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Su Sung Chung authored
[why] dcn20_clk_mgr_construct was not initializing pp_smu, and PME call gets filtered out by the null check [how] initialize pp_smu dcn20_clk_mgr_construct Signed-off-by:
Su Sung Chung <Su.Chung@amd.com> Reviewed-by:
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