- 27 May, 2014 4 commits
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Olof Johansson authored
Merge tag 'keystone-reset-driver' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into next/drivers Merge "Keystone Reset driver for 3.16" from Santosh Shilimkar: * tag 'keystone-reset-driver' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone: power: reset: keystone-reset: introduce keystone reset driver Documentation: dt: add bindings for keystone pll control controller Documentation: dt: add bindings for keystone reset driver Signed-off-by:
Olof Johansson <olof@lixom.net>
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Ivan Khoronzhuk authored
The keystone SoC can be rebooted in several ways. By external reset pin, by soft and by watchdogs. To allow keystone SoC reset if watchdog is triggered we have to enable it in reset mux configuration register regarding of watchdog configuration. Also we need to set soft/hard reset we are going to use. So add keystone reset driver to handle all this stuff. Reviewed-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Signed-off-by:
Santosh Shilimkar <santosh.shilimkar@ti.com>
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Ivan Khoronzhuk authored
The main pll controller used to drive theC66x CorePacs, the switch fabric, and a majority of the peripheral clocks (all but the ARM CorePacs, DDR3 and the NETCP modules) requires a PLL Controller to manage the various clock divisions, gating, and synchronization. Reviewed-by:
Mike Turquette <mturquette@linaro.org> Signed-off-by:
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Ivan Khoronzhuk authored
This node is intended to allow SoC reset in case of software reset or appropriate watchdogs. The Keystone SoCs can contain up to 4 watchdog timers to reset SoC. Each watchdog timer event input is connected to the Reset Mux block. The Reset Mux block can be configured to cause reset or not. Additionally soft or hard reset can be configured. Reviewed-by:
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- 26 May, 2014 4 commits
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Olof Johansson authored
Merge tag 'davinci-for-v3.16/edma' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/drivers Merge "DaVinci EDMA clean-up for v3.16" from Sekhar Nori: This series makes edma use configuration information available within the IP instead of reading it from platform data or DT. Some other useful clean-ups are included too. * tag 'davinci-for-v3.16/edma' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci: (34 commits) ARM: edma: Remove redundant/unused parameters from edma_soc_info ARM: davinci: Remove redundant/unused parameters for edma ARM: dts: am4372: Remove obsolete properties from edma node ARM: dts: am33xx: Remove obsolete properties from edma node dt/bindings: ti,edma: Remove redundant properties from documentation ARM: edma: Get IP configuration from HW (number of channels, tc, etc) ARM: edma: Save number of regions from pdata to struct edma ARM: edma: Remove num_cc member from struct edma ARM: edma: Remove queue_tc_mapping data from edma_soc_info ARM: davinci: Remove eDMA3 queue_tc_mapping data from edma_soc_info ARM: edma: Do not change TC -> Queue mapping, leave it to default. ARM: edma: Take the number of tc from edma_soc_info (pdata) ARM: edma: No need to clean the pdata in edma_of_parse_dt() ARM: edma: Clean up and simplify the code around irq request dmaengine: edma: update DMA memcpy to use new param element dmaengine: edma: Document variables used for residue accounting dmaengine: edma: Provide granular accounting dmaengine: edma: Make reading the position of active channels work dmaengine: edma: Store transfer data in edma_desc and edma_pset dmaengine: edma: Create private pset struct ... Signed-off-by:
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Olof Johansson authored
Merge tag 'davinci-fixes-for-v3.15-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/drivers The patch fixes EDMA crossbar mapping to actually make it work. The patch has been tagged for stable. * tag 'davinci-fixes-for-v3.15-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci: ARM: common: edma: Fix xbar mapping
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Olof Johansson authored
Merge tag 'omap-for-v3.16/l3-noc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/drivers Merge "ARM: omap l3-noc bus driver changes for v3.16 merge window, resend" from Tony Lindgren: Improvments to omap l3-noc bus driver for v3.16 merge window to add support for am347x and dra7. * tag 'omap-for-v3.16/l3-noc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (25 commits) bus: omap_l3_noc: Add AM4372 interconnect error data bus: omap_l3_noc: Add DRA7 interconnect error data bus: omap_l3_noc: introduce concept of submodule bus: omap_l3_noc: Add information about the context of operation bus: omap_l3_noc: add information about the type of operation bus: omap_l3_noc: ignore masked out unclearable targets bus: omap_l3_noc: improve readability by using helper for slave event parsing bus: omap_l3_noc: make error reporting and handling common bus: omap_l3_noc: fix masterid detection bus: omap_l3_noc: convert flagmux information into a structure bus: omap_l3_noc: use of_match_data to pick up SoC information bus: omap_l3_noc: Add support for discountinous flag mux input numbers bus: omap_l3_noc: convert target information into a structure bus: omap_l3_noc: move L3 master data structure out bus: omap_l3_noc: un-obfuscate l3_targ address computation bus: omap_l3_noc: switch over to relaxed variants of readl/writel bus: omap_l3_noc: populate l3->dev and use it bus: omap_l3_noc: remove iclk from omap_l3 struct bus: omap_l3_noc: rename functions and data to omap_l3 bus: omap_l3_noc: Fix copyright information ... Signed-off-by:
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Arnd Bergmann authored
The match tables must be zero-terminated, and Kbuild now helpfully fails to link the kernel if that isn't the case. Signed-off-by:
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- 23 May, 2014 8 commits
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Florian Fainelli authored
This patch documents the sysfs properties exposed by the Broadcom GISB bus arbiter hardware. Signed-off-by:
Florian Fainelli <f.fainelli@gmail.com> Signed-off-by:
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Florian Fainelli authored
This patch adds the Broadcom GISB arbiter Device Tree binding that is used on all Broadcom Set-top-box System-on-a-chip. Signed-off-by:
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Florian Fainelli authored
This patch adds support for the Broadcom GISB arbiter bus timeout/error handler. GISB is a proprietary bus used by Broadcom Set Top Box System-on-a-chip devices (BCM7xxx) which allows multiple masters and clients to be interfaced with each other. The bus arbiter offers support for generating two interrupts towards the host CPU, thus allowing us to "catch" clock gated masters, or masters being volontarily blocked for powersaving purposes, or do general system troubleshooting. We also register a hook with the ARM fault exception handling to allow printing a more informative message than "imprecise external abort at 0x00000000" for instance. Signed-off-by:
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https://github.com/mripard/linuxArnd Bergmann authored
Allwinner drivers changes for 3.16, take 2 Add reset driver for the A31 * tag 'sunxi-drivers-for-3.16-2' of https://github.com/mripard/linux: power: reset: Add Allwinner A31 reset code Signed-off-by:
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Arnd Bergmann authored
Merge tag 'qcom-drivers-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom into next/drivers Qualcomm ARM Based driver Updates for v3.16 * Introduce drivers/soc directory for misc SoC specific code * Add driver to configure GSBI device * tag 'qcom-drivers-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom: soc: qcom: Add GSBI driver soc: Introduce drivers/soc place-holder for SOC specific drivers Signed-off-by:
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Andy Gross authored
The GSBI (General Serial Bus Interface) driver controls the overarching configuration of the shared serial bus infrastructure on APQ8064, IPQ8064, and earlier QCOM processors. The GSBI supports UART, I2C, SPI, and UIM functionality in various combinations. Signed-off-by:
Andy Gross <agross@codeaurora.org> Signed-off-by:
Kumar Gala <galak@codeaurora.org>
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Santosh Shilimkar authored
Based on earlier thread "https://lkml.org/lkml/2013/10/7/662" and discussion at Kernel Summit'2013, it was agreed to create 'driver/soc' for drivers which are quite SOC specific. Further discussion on the subject is in response to the earlier version of the patch is here: http://lwn.net/Articles/588942/ Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Kumar Gala <galak@codeaurora.org> Cc: Paul Walmsley <paul@pwsan.com> Cc: Olof Johansson <olof@lixom.net> Cc: Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Sandeep Nair <sandeep_n@ti.com> Signed-off-by:
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Maxime Ripard authored
That code used to be in the machine code, but it's more fit here with other restart hooks. That will allow to cleanup the machine directory, while waiting for a proper watchdog driver for the A31. Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by:
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- 22 May, 2014 15 commits
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Peter Ujfalusi authored
The following parameters are no longer needed by the edma driver since the information can be obtained from the IP's CCCFG register: n_channel, n_region, n_slot and n_tc. Remove the n_cc as well since in this context it has no meaning. We have separate edma_soc_info struct/eDMA3_CC instance so this member does not make any sense (and the driver no longer uses it). Signed-off-by:
Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by:
Sekhar Nori <nsekhar@ti.com>
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Peter Ujfalusi authored
The following parameters are no longer needed by the edma driver since the information can be obtained from the IP's CCCFG register: n_channel, n_region, n_slot and n_tc. Remove the initialization of n_cc as well since in this context it has no meaning. We have separate edma_soc_info struct/eDMA3_CC instance so this member does not make any sense (and the driver no longer uses it). Signed-off-by:
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Peter Ujfalusi authored
dma-channels, ti,edma-regions and ti,edma-slots no longer needed in DT since the the same information is available in the IP's CCCFG register. Signed-off-by:
Tony Lindgren <tony@atomide.com> Signed-off-by:
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Peter Ujfalusi authored
dma-channels, ti,edma-regions and ti,edma-slots no longer needed in DT since the the same information is available in the IP's CCCFG register. Signed-off-by:
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Peter Ujfalusi authored
From CCCFG register of eDMA3 we can get all the needed information for the driver about the IP: Number of channels: NUM_DMACH Number of regions: NUM_REGN Number of slots (PaRAM sets): NUM_PAENTRY Number of TC/EQ: NUM_EVQUE The ti,edma-regions; ti,edma-slots and dma-channels in DT are redundant since the very same information can be obtained from the HW. The mentioned properties are deprecated. Signed-off-by:
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Peter Ujfalusi authored
From CCCFG register of eDMA3 we can get all the needed information for the driver about the IP: Number of channels: NUM_DMACH Number of regions: NUM_REGN Number of slots (PaRAM sets): NUM_PAENTRY Number of TC/EQ: NUM_EVQUE In case when booted with DT or the queue_priority_mapping is not provided set up a default priority map. Signed-off-by:
Joel Fernandes <joelf@ti.com> Signed-off-by:
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Peter Ujfalusi authored
To be consistent in the code that we take parameters from edma_cc[j] struct and not randomly from info[j] as well. Signed-off-by:
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Peter Ujfalusi authored
The struct edma is allocated per CC bases so the member num_cc does not make any sense. One CC is one CC, it does not have sub CCs. Signed-off-by:
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Peter Ujfalusi authored
It is no longer in use by the driver or board files. Signed-off-by:
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Olof Johansson authored
Merge tag 'samsung-drivers' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers Merge "Samsung driver update for 3.16" from Kukjin Kim: exynos_mct update for v3.16 - register sched_clock callback to use clocksource mct-frc * tag 'samsung-drivers' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: clocksource: exynos_mct: register sched_clock callback Signed-off-by:
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Peter Ujfalusi authored
It is ignored by the edma driver since we are just setting back the default mapping of TC -> Queue. Signed-off-by:
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Peter Ujfalusi authored
There is no need to change the default TC -> Queue mapping. By default the mapping is: TC0 -> Q0, TC1 -> Q1, etc. Changing this has no benefits at all and all the board files are just setting the same mapping back to the HW. Signed-off-by:
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Peter Ujfalusi authored
Instead of saving the for loop length, take the num_tc value from the pdata. In case of DT boot set the n_tc to 3 as it is hardwired in edma_of_parse_dt() This is a temporary state since upcoming patch(es) will change how we are dealing with these parameters. Signed-off-by:
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Peter Ujfalusi authored
The pdata has been just allocated with devm_kzalloc() in edma_setup_info_from_dt() and passed to this function. Signed-off-by:
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Peter Ujfalusi authored
Get the two interrupt line number at the same time by merging the two instance of if(node){}else{} places. replace the &pdev->dev with the already existing dev which makes it possible to collapse lines with devm_request_irq() Signed-off-by:
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- 21 May, 2014 1 commit
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https://github.com/mripard/linuxOlof Johansson authored
Merge "Allwinner drivers changes for 3.16" from Maxime Ripard: Reset drivers for the A31, that have been merged with reset maintainer's Acked-by. * 'sunxi/drivers-for-3.16' of https://github.com/mripard/linux: reset: sunxi: allow MFD subdevices probe reset: sunxi: document sunxi's reset controllers bindings Signed-off-by:
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- 20 May, 2014 1 commit
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git://git.infradead.org/linux-mvebuOlof Johansson authored
Merge "ARM: mvebu: driver changes for v3.16" from Jason Cooper: mvebu driver changes for v3.16 - mvebu-devbus - changes need to add support for the orion5x platform * tag 'mvebu-drivers-3.16' of git://git.infradead.org/linux-mvebu: memory: mvebu-devbus: add a devbus, keep-config property memory: mvebu-devbus: add Orion5x support memory: mvebu-devbus: split functions memory: mvebu-devbus: use _SHIFT suffixes instead of _BIT memory: mvebu-devbus: use ARMADA_ prefix in defines ARM: orion5x: fix target ID for crypto SRAM window memory: mvebu-devbus: fix the conversion of the bus width Signed-off-by:
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- 15 May, 2014 2 commits
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Boris BREZILLON authored
The current implementation uses sunxi_reset_init function for both early init and platform device probe. The sunxi_reset_init function uses DT to retrieve device resources, which will be an issue if reset controllers are registered from an MFD device that define resources from mfd_cell definition. Moreover, we can make of devm functions when we're in the probe context. Signed-off-by:
Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by:
Philipp Zabel <p.zabel@pengutronix.de>
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Boris BREZILLON authored
Add DT bindings documentation for sunxi's reset controllers. Signed-off-by:
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- 05 May, 2014 5 commits
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Olof Johansson authored
Merge tag 'socfpga-driver-update-for-3.16' of git://git.rocketboards.org/linux-socfpga-next into next/drivers Merge "drivers: Add reset driver for SOCFPGA" from Dinh Nguyen: Add a reset driver for the SOCFPGA platform. * tag 'socfpga-driver-update-for-3.16' of git://git.rocketboards.org/linux-socfpga-next: reset: add driver for socfpga Signed-off-by:
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Afzal Mohammed authored
Add AM4372 information to handle L3 error. AM4372 has two clk domains 100f and 200s. Provide flagmux and data associated with it. NOTE: Timeout doesn't have STDERRLOG_MAIN register. And per hardware team, L3 timeout error cannot be cleared the normal way (by setting bit 31 in STDERRLOG_MAIN), instead it may be required to do system reset. L3 error handler can't help in such scenarios. Hence indicate timeout target offset as L3_TARGET_NOT_SUPPORTED as done for undocumented bits. Signed-off-by:
Dave Gerlach <d-gerlach@ti.com> Signed-off-by:
Afzal Mohammed <afzal@ti.com> Signed-off-by:
Nishanth Menon <nm@ti.com> Acked-by:
Darren Etheridge <detheridge@ti.com> Tested-by:
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Rajendra Nayak authored
DRA7 is distinctly different from OMAP4 in terms of masters and clock domain organization. There two main clock domains which is divided as follows: <0x44000000 0x1000000> is clk1 and clk2 is the sub clock domain <0x45000000 0x1000> is clk3 Add all the data needed to handle L3 error handling on DRA7 devices and mark clk2 as subdomain and provide a compatible flag for functionality. Other than the data difference the hardware blocks involved are essentially the same. Signed-off-by:Rajendra Nayak <rnayak@ti.com> [nm@ti.com: bugfixes and generic improvements, documentation] Signed-off-by:
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Nishanth Menon authored
While OMAP4 and OMAP5 had 3 separate clock domains, DRA7 has only 2 and the first one then is internally divided into 2 sub clock domains. To better represent this in the driver, we use the concept of submodule. The address defintions in the devicetree is as per the high level clock domain(module) base, the sub clockdomain/subdomain which shares the same register space of a clockdomain is marked in the SoC data as L3_BASE_IS_SUBMODULE. L3_BASE_IS_SUBMODULE is used as an indication that it's base address is the same as the parent module and offsets are considered from the same base address as they are usually intermingled. Other than the base address, the submodule is same as a module as it is functionally so. Signed-off-by:
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Nishanth Menon authored
L3 error may be triggered using Debug interface (example JTAG) or due to other errors, for example an opcode fetch (due to function pointer or stack corruption) or a data access (due to some other failure). NOC registers contain additional information to help aid debug information. With this, we can enhance the error information to more detailed form: " L3 Custom Error: MASTER MPU TARGET L4PER2 (Read): Data Access in User mode during Functional access " Signed-off-by:
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