- 18 May, 2020 1 commit
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Tudor Ambarus authored
The sama5d2 SoC has two dedicated I2C IPs that are enabled on sama5d2_xplained. Add alias for the i2c devices to not rely on probe order for the i2c device numbering. Signed-off-by:
Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200518114802.253660-1-tudor.ambarus@microchip.comSigned-off-by:
Alexandre Belloni <alexandre.belloni@bootlin.com>
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- 15 May, 2020 17 commits
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Codrin Ciubotariu authored
The SCL gpio pin used by I2C bus for recovery needs to be configured as open drain. Fixes: 455fec93 ("ARM: dts: at91: sama5d2: add i2c gpio pinctrl") Fixes: a4bd8da8 ("ARM: dts: at91: sama5d3: add i2c gpio pinctrl") Fixes: 8fb82f05 ("ARM: dts: at91: sama5d4: add i2c gpio pinctrl") Signed-off-by:
Codrin Ciubotariu <codrin.ciubotariu@microchip.com> Link: https://lore.kernel.org/r/20200515140001.287932-1-codrin.ciubotariu@microchip.comSigned-off-by:
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Tudor Ambarus authored
Users can choose which flexcom function to use. Describe the I2C Flexcom0 function. Add alias for the i2c2 node in order to not rely on probe order for the i2c device numbering. The sama5d2 SoC has two dedicated i2c buses and five flexcoms that can function as i2c. The i2c0 and i2c1 aliases are kept for the dedicated i2c buses, the i2c flexcom functions can be numbered in order starting from i2c2. Signed-off-by:
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Tudor Ambarus authored
Indicate which i2c alias is for which connector on the board. Specify that serial0 is for DBGU. This eases tester's life. Signed-off-by:
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Tudor Ambarus authored
The aliases should be defined in the board dts rather than in the SoC dtsi. Don't rely on the aliases defined in the SoC dtsi and define the alias for the Serial DBGU in the board dts file. sama5d2 boards use the "serial0" alias for the Serial DBGU, do the same for sama5d2_xplained. Signed-off-by:
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Tudor Ambarus authored
Describe all the flexcom functions for all the flexcom nodes. Signed-off-by:
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Tudor Ambarus authored
Device aliases are board-specific, if needed one should define them in board dts rather than in the SoC dtsi. If an alias from the SoC dtsi is addressed by a driver that does not use any of the of_alias*() methods, we can drop it. This is the case for the i2s aliases, drop them. tcb aliases point to nodes that are not enabled in any of the sama5d2 based platforms. atmel_tclib.c is scheduled to go away, any board using that alias is already broken, so get rid of the tcb aliases too. Signed-off-by:
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Tudor Ambarus authored
Spare boards of duplicating the DMA bindings. Describe the flx0 DMA bindings in the SoC dtsi. Users that don't want to use DMA for their flexcom functions have to overwrite the flexcom DMA bindings in their board device tree. Signed-off-by:
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Tudor Ambarus authored
Spare boards of duplicating the DMA bindings. Describe the flx1 DMA bindings in the SoC dtsi. Users that don't want to use DMA for their flexcom functions have to overwrite the flexcom DMA bindings in their board device tree. Signed-off-by:
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Tudor Ambarus authored
Spare boards of duplicating the DMA bindings. Describe the flx3 DMA bindings in the SoC dtsi. Users that don't want to use DMA for their flexcom functions have to overwrite the flexcom DMA bindings in their board device tree. Signed-off-by:
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Tudor Ambarus authored
Spare boards of duplicating the DMA bindings. Describe the flx4 DMA bindings in the SoC dtsi. Users that don't want to use DMA for their flexcom functions have to overwrite the flexcom DMA bindings in their board device tree. Signed-off-by:
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Tudor Ambarus authored
The UART submodule in Flexcom has 32-byte Transmit and Receive FIFOs. Tested uart7 on sama5d2-icp, which has both DMA and FIFO enabled. Signed-off-by:
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Tudor Ambarus authored
The Flexcom IP is part of the sama5d2 SoC. Move the flx0 node together with its function definitions in sama5d2.dtsi. Boards will just fill the pins and enable the desired functions. There is a single functional change in this patch. With the move of the flx0 uart5 definition in the SoC dtsi, the uart5 from at91-sama5d27_wlsom1_ek.dts inherits the following optional property: atmel,fifo-size = <32>; This particular change was tested by Codrin. Signed-off-by:
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Tudor Ambarus authored
The Flexcom IP is part of the sama5d2 SoC. Move the flx0 node together with its function definitions in sama5d2.dtsi. Boards will just fill the pins and enable the desired functions. Signed-off-by:
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Tudor Ambarus authored
The Flexcom IP is part of the sama5d2 SoC. Move the flx2 node together with its function definitions in sama5d2.dtsi. Boards will just fill the pins and enable the desired functions. Signed-off-by:
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Tudor Ambarus authored
The Flexcom IP is part of the sama5d2 SoC. Move the flx3 node together with its function definitions in sama5d2.dtsi. Boards will just fill the pins and enable the desired functions. Signed-off-by:
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Tudor Ambarus authored
The Flexcom IP is part of the sama5d2 SoC. Move the flx0 node together with its function definitions in sama5d2.dtsi. Boards will just fill the pins and enable the desired functions. Signed-off-by:
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Tudor Ambarus authored
The sama5d2 SoC has the following IPs: [uart0, uart4], {spi0, spi1}, {i2c0, i2c1}. Label the flexcom functions in order: flx0: uart5, spi2, i2c2 flx1: uart6, spi3, i2c3 flx2: uart7, spi4, i2c4 flx3: uart8, spi5, i2c5 flx4: uart9, spi6, i2c6 Some boards respected this scheme, others not. Fix the ones that didn't. Signed-off-by:
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- 14 Apr, 2020 1 commit
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Tudor Ambarus authored
wlsom1 has an ATECC608A-TNGTLS Secure Element connected on the i2c0 bus. Add alias for the i2c device to not rely on probe order for the i2c device numbering. Signed-off-by:
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- 13 Apr, 2020 16 commits
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Cristian Birsan authored
This is the addition of the new SAMA5D2 Industrial Connectivity Platform(ICP). Signed-off-by:
Cristian Birsan <cristian.birsan@microchip.com> Link: https://lore.kernel.org/r/20200410164320.7658-3-cristian.birsan@microchip.comSigned-off-by:
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Codrin Ciubotariu authored
Document device tree binding for SAMA5D2 Industrial Connectivity Platform(ICP). Signed-off-by:
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Ludovic Desroches authored
There is an EEPROM on at91-sama5d27_som1 connected to i2c0. i2c0 node has to be moved from at91-sama5d27_som1_ek to at91-sama5d27_som1. Enable the i2c EEPROM found on at91-sama5d27_som1. Add an alias for the i2c node. Signed-off-by:
Ludovic Desroches <ludovic.desroches@microchip.com> Tested-by:
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Cyrille Pitchen authored
This patch enables the QSPI0 controller, configures its pin muxing and declares a jedec,spi-nor memory. sama5d2 Xplained RevB and RevC use the Macronix MX25L25673G flash memory which advertises a maximum frequency of 80MHz for Quad IO Fast Read. Set the spi-max-frequency to 80MHz knowing that actually the QSPI drver will set the SPI bus clock to 166MHz / 3 = 55.3MHz. Signed-off-by:
Cyrille Pitchen <cyrille.pitchen@microchip.com> Tested-by:
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Tudor Ambarus authored
sdmmc1 is not populated by default on sam9x60ek, but there are cases where it is populated with wilc3000. Add the node, but keep it disabled. Signed-off-by:
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Claudiu Beznea authored
Add SoM1 flash mapping, identical with the other SPI NOR flash mappings found on the other at91 boards. Signed-off-by:
Claudiu Beznea <claudiu.beznea@microchip.com> Tested-by:
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Tudor Ambarus authored
Both the QSPI controller and the sst26vf064b flash support quad mode, enable it. Signed-off-by:
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Ludovic Desroches authored
Add aliases for i2c devices to not rely on probe order for i2c device numbering. Signed-off-by:
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Ludovic Desroches authored
Enable i2c0 controller. Signed-off-by:
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Ludovic Desroches authored
Add the push button PB_USER as wakeup source Signed-off-by:
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Ludovic Desroches authored
The gpio property for the vbus pin doesn't match the pinctrl and is not correct. Signed-off-by:
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Ludovic Desroches authored
Remove non-removable and mmc-ddr-1_8v properties from the sdmmc0 node which come probably from an unchecked copy/paste. Signed-off-by:
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Alexandre Belloni authored
Switch at91rm9200 boards to the new PMC clock bindings. Link: https://lore.kernel.org/r/20200324124154.368335-1-alexandre.belloni@bootlin.comSigned-off-by:
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Alexandre Belloni authored
Switch at91sam9g45 boards to the new PMC clock bindings. Link: https://lore.kernel.org/r/20200117210619.17768-1-alexandre.belloni@bootlin.comSigned-off-by:
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Alexandre Belloni authored
Switch at91sam9n12 boards to the new PMC clock bindings. Link: https://lore.kernel.org/r/20200116173510.427403-1-alexandre.belloni@bootlin.comSigned-off-by:
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Alexandre Belloni authored
Switch sama5d3 boards to the new PMC clock bindings. This prevents the wb50n to use the out of spec rate for USART1. Link: https://lore.kernel.org/r/20200110222744.1261464-1-alexandre.belloni@bootlin.comSigned-off-by:
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- 12 Apr, 2020 5 commits
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Linus Torvalds authored
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Linus Torvalds authored
This sorts the actual field names too, potentially causing even more chaos and confusion at merge time if you have edited the MAINTAINERS file. But the end result is a more consistent layout, and hopefully it's a one-time pain minimized by doing this just before the -rc1 release. This was entirely scripted: ./scripts/parse-maintainers.pl --input=MAINTAINERS --output=MAINTAINERS --order Requested-by:
Joe Perches <joe@perches.com> Signed-off-by:
Linus Torvalds <torvalds@linux-foundation.org>
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Linus Torvalds authored
They are all supposed to be sorted, but people who add new entries don't always know the alphabet. Plus sometimes the entry names get edited, and people don't then re-order the entry. Let's see how painful this will be for merging purposes (the MAINTAINERS file is often edited in various different trees), but Joe claims there's relatively few patches in -next that touch this, and doing it just before -rc1 is likely the best time. Fingers crossed. This was scripted with /scripts/parse-maintainers.pl --input=MAINTAINERS --output=MAINTAINERS but then I also ended up manually upper-casing a few entry names that stood out when looking at the end result. Requested-by:
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git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds authored
Pull x86 fixes from Thomas Gleixner: "A set of three patches to fix the fallout of the newly added split lock detection feature. It addressed the case where a KVM guest triggers a split lock #AC and KVM reinjects it into the guest which is not prepared to handle it. Add proper sanity checks which prevent the unconditional injection into the guest and handles the #AC on the host side in the same way as user space detections are handled. Depending on the detection mode it either warns and disables detection for the task or kills the task if the mode is set to fatal" * tag 'x86-urgent-2020-04-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: KVM: VMX: Extend VMXs #AC interceptor to handle split lock #AC in guest KVM: x86: Emulate split-lock access as a write in emulator x86/split_lock: Provide handle_guest_split_lock()
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git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds authored
Pull time(keeping) updates from Thomas Gleixner: - Fix the time_for_children symlink in /proc/$PID/ so it properly reflects that it part of the 'time' namespace - Add the missing userns limit for the allowed number of time namespaces, which was half defined but the actual array member was not added. This went unnoticed as the array has an exessive empty member at the end but introduced a user visible regression as the output was corrupted. - Prevent further silent ucount corruption by adding a BUILD_BUG_ON() to catch half updated data. * tag 'timers-urgent-2020-04-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: ucount: Make sure ucounts in /proc/sys/user don't regress again time/namespace: Add max_time_namespaces ucount time/namespace: Fix time_for_children symlink
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