1. 24 Jan, 2018 10 commits
    • Davide Caratti's avatar
      net/sched: act_csum: don't use spinlock in the fast path · 9c5f69bb
      Davide Caratti authored
      use RCU instead of spin_{,unlock}_bh() to protect concurrent read/write on
      act_csum configuration, to reduce the effects of contention in the data
      path when multiple readers are present.
      Signed-off-by: default avatarDavide Caratti <dcaratti@redhat.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      9c5f69bb
    • Davide Caratti's avatar
      net/sched: act_csum: use per-core statistics · f6052cf2
      Davide Caratti authored
      use per-CPU counters, like other TC actions do, instead of maintaining one
      set of stats across all cores. This allows updating act_csum stats without
      the need of protecting them using spin_{,un}lock_bh() invocations.
      Signed-off-by: default avatarDavide Caratti <dcaratti@redhat.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      f6052cf2
    • Roopa Prabhu's avatar
      net: link_watch: mark bonding link events urgent · b76f4189
      Roopa Prabhu authored
      It takes 1sec for bond link down notification to hit user-space
      when all slaves of the bond go down. 1sec is too long for
      protocol daemons in user-space relying on bond notification
      to recover (eg: multichassis lag implementations in user-space).
      Since the link event code already marks team device port link events
       as urgent, this patch moves the code to cover all lag ports and master.
      Signed-off-by: default avatarRoopa Prabhu <roopa@cumulusnetworks.com>
      Acked-by: default avatarJiri Pirko <jiri@mellanox.com>
      Reviewed-by: default avatarNikolay Aleksandrov <nikolay@cumulusnetworks.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      b76f4189
    • David S. Miller's avatar
      Merge branch '10GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/next-queue · 0542e13b
      David S. Miller authored
      Jeff Kirsher says:
      
      ====================
      10GbE Intel Wired LAN Driver Updates 2018-01-23
      
      This series contains updates to ixgbe only.
      
      Shannon Nelson provides an implementation of the ipsec hardware offload
      feature for the ixgbe driver for these devices: x540, x550, 82599.
      
      The ixgbe NICs support ipsec offload for 1024 Rx and 1024 Tx Security
      Associations (SAs), using up to 128 inbound IP addresses, and using the
      rfc4106(gcm(aes)) encryption.  This code does not yet support checksum
      offload, or TSO in conjunction with the ipsec offload - those will be
      added in the future.
      
      This code shows improvements in both packet throughput and CPU utilization.
      For example, here are some quicky numbers that show the magnitude of the
      performance gain on a single run of "iperf -c <dest>" with the ipsec
      offload on both ends of a point-to-point connection:
      
      	9.4 Gbps - normal case
      	7.6 Gbps - ipsec with offload
      	343 Mbps - ipsec no offload
      ====================
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      0542e13b
    • David S. Miller's avatar
      Merge branch 'GEHC-Bx50-Switch-Support' · c89b517d
      David S. Miller authored
      Sebastian Reichel says:
      
      ====================
      GEHC Bx50 Switch Support
      
      This adds support for the internal switch found in GE Healthcare
      B450v3, B650v3 and B850v3. All devices use a GPIO bitbanged MDIO
      bus to communicate with the switch and a PCIe based network card
      for exchanging network data. The cpu network data link requires,
      that the switch's internal phy interface is enabled, so support
      for that is added by the first patch in this series.
      
      The patch series is based on v4.15-rc8.
      
      Changes since PATCHv4:
       * Introduce dsa_port_link_(un)register_of and mark the fixed
         variant static.
       * Update patch description to describe the phy<->phy connection
         from i210 to the Marvell switch
      Changes since PATCHv3:
       * Enable the phy in dsa_port_setup() instead of abusing the
         fixed link setup function
      Changes since PATCHv2:
       * Add phy nodes to switch in bx50.dtsi and reference them
         from switch ports
       * Enable cpu-port's phy based on 'phy-handle' instead of 'phy-mode'
      Changes since PATCHv1:
       * Use 'marvell,mv88e6085' instead of introducing compatible
         string for mv88e6240.
       * Fix indention of DT nodes
       * Only enable 'cpu' phy, if explicitly set to "internal".
      ====================
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      c89b517d
    • Sebastian Reichel's avatar
      ARM: dts: imx6q-b450v3: Add switch port configuration · 658d063d
      Sebastian Reichel authored
      This adds support for the Marvell switch and names the network
      ports according to the labels, that can be found next to the
      connectors. The switch is connected to the host system using a
      PCI based network card.
      
      The PCI bus configuration has been written using the following
      information:
      
      root@b450v3# lspci -tv
      -[0000:00]---00.0-[01]----00.0  Intel Corporation I210 Gigabit Network Connection
      root@b450v3# lspci -nn
      00:00.0 PCI bridge [0604]: Synopsys, Inc. Device [16c3:abcd] (rev 01)
      01:00.0 Ethernet controller [0200]: Intel Corporation I210 Gigabit Network Connection [8086:1533] (rev 03)
      Signed-off-by: default avatarSebastian Reichel <sebastian.reichel@collabora.co.uk>
      Reviewed-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      658d063d
    • Sebastian Reichel's avatar
      ARM: dts: imx6q-b650v3: Add switch port configuration · b2ea7f83
      Sebastian Reichel authored
      This adds support for the Marvell switch and names the network
      ports according to the labels, that can be found next to the
      connectors. The switch is connected to the host system using a
      PCI based network card.
      
      The PCI bus configuration has been written using the following
      information:
      
      root@b650v3# lspci -tv
      -[0000:00]---00.0-[01]----00.0  Intel Corporation I210 Gigabit Network Connection
      root@b650v3# lspci -nn
      00:00.0 PCI bridge [0604]: Synopsys, Inc. Device [16c3:abcd] (rev 01)
      01:00.0 Ethernet controller [0200]: Intel Corporation I210 Gigabit Network Connection [8086:1533] (rev 03)
      Signed-off-by: default avatarSebastian Reichel <sebastian.reichel@collabora.co.uk>
      Reviewed-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      b2ea7f83
    • Sebastian Reichel's avatar
      ARM: dts: imx6q-b850v3: Add switch port configuration · e6b22e41
      Sebastian Reichel authored
      This adds support for the Marvell switch and names the network
      ports according to the labels, that can be found next to the
      connectors ("ID", "IX", "ePort 1", "ePort 2"). The switch is
      connected to the host system using a PCI based network card.
      
      The PCI bus configuration has been written using the following
      information:
      
      root@b850v3# lspci -tv
      -[0000:00]---00.0-[01]----00.0-[02-05]--+-01.0-[03]----00.0  Intel Corporation I210 Gigabit Network Connection
                                              +-02.0-[04]----00.0  Intel Corporation I210 Gigabit Network Connection
                                              \-03.0-[05]--
      root@b850v3# lspci -nn
      00:00.0 PCI bridge [0604]: Synopsys, Inc. Device [16c3:abcd] (rev 01)
      01:00.0 PCI bridge [0604]: PLX Technology, Inc. PEX 8605 PCI Express 4-port Gen2 Switch [10b5:8605] (rev ab)
      02:01.0 PCI bridge [0604]: PLX Technology, Inc. PEX 8605 PCI Express 4-port Gen2 Switch [10b5:8605] (rev ab)
      02:02.0 PCI bridge [0604]: PLX Technology, Inc. PEX 8605 PCI Express 4-port Gen2 Switch [10b5:8605] (rev ab)
      02:03.0 PCI bridge [0604]: PLX Technology, Inc. PEX 8605 PCI Express 4-port Gen2 Switch [10b5:8605] (rev ab)
      03:00.0 Ethernet controller [0200]: Intel Corporation I210 Gigabit Network Connection [8086:1533] (rev 03)
      04:00.0 Ethernet controller [0200]: Intel Corporation I210 Gigabit Network Connection [8086:1533] (rev 03)
      Signed-off-by: default avatarSebastian Reichel <sebastian.reichel@collabora.co.uk>
      Reviewed-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      e6b22e41
    • Sebastian Reichel's avatar
      ARM: dts: imx6q-bx50v3: Add internal switch · e26dead4
      Sebastian Reichel authored
      B850v3, B650v3 and B450v3 all have a GPIO bit banged MDIO bus to
      communicate with a Marvell switch. On all devices the switch is
      connected to a PCI based network card, which needs to be referenced
      by DT, so this also adds the common PCI root node.
      Signed-off-by: default avatarSebastian Reichel <sebastian.reichel@collabora.co.uk>
      Reviewed-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      e26dead4
    • Sebastian Reichel's avatar
      net: dsa: Support internal phy on 'cpu' port · 33615367
      Sebastian Reichel authored
      This adds support for enabling the internal PHY for a 'cpu' port.
      It has been tested on GE B850v3,  B650v3 and B450v3, which have a
      built-in MV88E6240 switch hardwired to a PCIe based network card.
      On these machines the internal PHY of the i210 network card and
      the Marvell switch are connected to each other and must be enabled
      for properly using the switch. While the i210 PHY will be enabled
      when the network interface is enabled, the switch's port is not
      exposed as network interface. Additionally the mv88e6xxx driver
      resets the chip during probe, so the PHY is disabled without this
      patch.
      Signed-off-by: default avatarSebastian Reichel <sebastian.reichel@collabora.co.uk>
      Reviewed-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      33615367
  2. 23 Jan, 2018 25 commits
  3. 22 Jan, 2018 5 commits