- 01 Nov, 2013 5 commits
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Paulo Zanoni authored
Even though we only check for unclaimed registers while we're writing registers, if we read a bad register we'll still trigger a CPU error interrupt, and we'll print an "Unclaimed register" DRM_ERROR due to that. To avoid this error, just avoid touching power domains that are not enabled. Use kzalloc so we're sure all the disabled domains will be zeroed on the error state file. We already print the information that is enough to discover if the power well is enabled on the error state file, so this should not be a problem. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=69747Signed-off-by:
Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Daniel Vetter authored
Now that DP port CRCs are stable, we can use it for generic CRC tests. Yay, the auto CRC source should now work everywhere! Reviewed-by:
Damien Lespiau <damien.lespiau@intel.com> Signed-off-by:
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Daniel Vetter authored
They've moved the DC balance reset bit around. Again I don't think we need it, but better safe than sorry and maybe HDMI port CRC will prove useful for checking infoframes or hdmi audio. v2: Apply the suggestions from Damien's review. Reviewed-by:
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Daniel Vetter authored
We need to reset the DP scrambler on every vsync to get stable CRCs. And since we can't use the normal pipe CRC on DP ports on g4x we really need them to be able to test modesetting issues on (e)DP outputs. Note that the DC balance reset is for SDVO port CRCs so we don't strictly need it. But better safe than sorry (and it's a nice template in case we ever want to grab port CRCs for e.g. audio checking). v2: Apply the suggestions from Damien's review. Reviewed-by:
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Daniel Vetter authored
On gmch platforms the normal pipe source CRC registers don't work for DP and TV encoders. And on newer platforms the single pipe CRC has been replaced by a set of CRC at different stages in the platform. Now most of our userspace tests don't care one bit about the exact CRC, they simply want something that reflects any changes on the screen. Hence add a new auto target for platform agnostic tests to use. v2: Pass back the adjusted source so that it can be shown in debugfs. v3: I seem to be unable to get a stable CRC for DP ports. So let's just disable them for now when using the auto mode. Note that testcases need to be restructured so that they can dynamically skip connectors. They also first need to set up the desired mode configuration, since otherwise the auto mode won't do the right thing. v4: Don't leak the modeset mutex on error paths. v5: Spelling fix for the i9xx auto_source function. Cc: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by:
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- 31 Oct, 2013 5 commits
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Paulo Zanoni authored
That explains why I was seeing 2 consecutive "Turning eDP VDD off" messages. Regression introduced by: commit bf13e81b Author: Jani Nikula <jani.nikula@intel.com> Date: Fri Sep 6 07:40:05 2013 +0300 drm/i915: add support for per-pipe power sequencing on vlv Signed-off-by:Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Imre Deak authored
In commit 6efdf354 Author: Imre Deak <imre.deak@intel.com> Date: Wed Oct 16 17:25:52 2013 +0300 the check for i915_disable_power_well flag was removed by overlook, so add it back now. Reported-by:
Paulo Zanoni <paulo.zanoni@intel.com> Signed-off-by:
Imre Deak <imre.deak@intel.com> Reviewed-by:
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Chon Ming Lee authored
Incorrect definition DPIO_TX3_SWING_CTL4. From Ville's review: "Based on the specs, the typo meant that HDMI B ended up using "incorrect" de-emphasis for the TMDS data lanes." Signed-off-by:
Chon Ming Lee <chon.ming.lee@intel.com> Reviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> [danvet: Add comment from Ville's review about the impact.] Signed-off-by:
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Paulo Zanoni authored
Now we only print messages when we actually enable VDD and when we actually disable VDD. The changes in the last commit triggered a big number of messages while the driver was being initialized, and I thought we were toggling things on/off too many times, but that was not really true: we were just being too verbose. Signed-off-by:
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Paulo Zanoni authored
If the eDP output is disabled, then we try to use /dev/i2c-X file to do i2c transations, we get a WARN from intel_dp_check_edp() saying we're trying to do AUX communication with the panel off. So this commit reorganizes the code so we enable the VDD at intel_dp_i2c_aux_ch() instead of just the callers inside i915.ko. This fixes the i2c subtest from the pc8 test of intel-gpu-tools on machines that have eDP panels. Signed-off-by:
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- 30 Oct, 2013 4 commits
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Daniel Vetter authored
- Use a for_each_loop and add the corresponding #defines. - Drop the _ILK postfix on the existing DE_PIPE_VBLANK macro for consistency with everything else. - Also use macros (and add the missing one for plane flips) for the ivb display interrupt handler. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Daniel Vetter authored
Request by Ville in his review of the CRC stuff. This converts everything but ilk_display_irq_handler since that needs a bit more than a simple search&replace to look nice. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Chris Wilson authored
The bbstate contains useful bits of debugging information such as whether the batch is being read from GTT or PPGTT, or whether it is allowed to execute privileged instructions. v2: Only record BB_STATE for gen4+ Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Daniel Vetter authored
Otherwise QA will report this as a real hang when running igt ZZ_missed_irq. v2: Actually test the right stuff and really shut up the DRM_ERROR output ... Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=70747Tested-by:
lu hua <huax.lu@intel.com> Acked-by:
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- 29 Oct, 2013 1 commit
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Imre Deak authored
Similarly rename the other related functions in the power domain interface. Higher level driver code calling these functions knows only about power domains, not the underlying power wells which may be different on different platforms. Also these functions really init/cleanup/resume power domains and only through that all related power wells, so rename them accordingly. Note that I left i915_{request,release}_power_well as is, since that really changes the state only of a single power well (and is HSW specific). It should also get a better name once we make it more generic by controlling things through a new audio power domain. v4: - use intel prefix instead of i915 everywhere (Paulo) - use a $prefix_$block_$action format (Daniel) Signed-off-by:
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- 28 Oct, 2013 1 commit
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Ville Syrjälä authored
We store cursor_x/y as int16_t internally, but the user provided coordinates are int32_t. Clamp the coordinates so that they don't overflow the int16_t. Since the cursor is only 64x64 in size, the clamping can't cause any visual changes. Signed-off-by:
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- 27 Oct, 2013 6 commits
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Imre Deak authored
The only real need for this field was in i915_{request,release}_power_well, but there we can get at it by a container_of magic. Also since in the future we'll have multiple power wells each with its own power_well struct it makes sense to remove the field from there where it'd be just redundancy. Suggested-by: -
Imre Deak authored
Currently we make sure that all power domains are enabled during driver init and turn off unneded ones only after the first modeset. Similarly during suspend we enable all power domains, which will remain on through the following resume until the first modeset. This logic is supported by intel_set_power_well() in the power domain framework. It would be nice to simplify the API, so that we only have get/put functions and make it more explicit on the higher level how this "power well on during init" logic works. This will make it also easier if in the future we want to shorten the time the power wells are on. For this add a new device private flag tracking whether we have the power wells on because of init/suspend and use only intel_display_power_get()/put(). As nothing else uses intel_set_power_well() we can remove it. This also fixes commit 6efdf354 Author: Imre Deak <imre.deak@intel.com> Date: Wed Oct 16 17:25:52 2013 +0300 drm/i915: enable only the needed power domains during modeset where removing intel_set_power_well() resulted in not releasing the reference on the power well that was taken during init and thus leaving the power well on all the time. Regression reported by Paulo. v2: - move the init_power_on flag to the power_domains struct (Daniel) v3: - add note about this being a regression fix too (Paulo) Signed-off-by:
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Imre Deak authored
In the future we'll need to support multiple power wells, so prepare for that here. Create a new power domains struct which contains all power domain/well specific fields. Since we'll have one lock protecting all power wells, move power_well->lock to the new struct too. No functional change. Signed-off-by:
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Ben Widawsky authored
Production HSW does not need it. I confirmed this with Art. Signed-off-by:
Ben Widawsky <ben@bwidawsk.net> Reviewed-by:
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Ben Widawsky authored
Production IVB does not need it. I confirmed this with Art. Signed-off-by:
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Ben Widawsky authored
All our registers which are written through the MCHBAR are defined descriptively as an offset to the MCHBAR. We had 3 outliers here. Convert these as well so all registers which are offsets are MCHBAR can be easily identified/found within the code. With this, convert DCLK to also follow this format. Signed-off-by:
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- 21 Oct, 2013 18 commits
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Damien Lespiau authored
Daniel pointed out that it was hard to get anything lockless to work correctly, so don't even try for this non critical piece of code and just use a spin lock. v2: Make intel_pipe_crc->opened a bool v3: Use assert_spin_locked() instead of a comment (Daniel Vetter) v4: Use spin_lock_irq() in the debugfs functions (they can only be called from process context), Use spin_lock() in the pipe_crc_update() function that can only be called from an interrupt handler, Use wait_event_interruptible_lock_irq() when waiting for data in the cicular buffer to ensure proper locking around the condition we are waiting for. (Daniel Vetter) Suggested-by: -
Daniel Vetter authored
Adding stuff to the bottom of struct drm_i915_driver_private is nowadays considered uncool. Cc: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by:
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Imre Deak authored
So far the modeset code enabled all power domains if it needed any. It wasn't a problem since HW generations so far only had one always-on power well and one dynamic power well that can be enabled/disabled. For domains powered by always-on power wells (panel fitter on pipe A and the eDP transcoder) we didn't do anything, for all other domains we just enabled the single dynamic power well. Future HW generations will change this, as they add multiple dynamic power wells. Support for these will be added later, this patch prepares for those by making sure we only enable the required domains. Note that after this change on HSW we'll enable all power domains even if it was the domain for the panel fitter on pipe A or the eDP transcoder. This isn't a problem since the power domain framework already checks if the domain is on an always-on power well and doesn't do anything in this case. Signed-off-by:
Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by:
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Imre Deak authored
We'll need the same functionality for other HW generations. The support for these will be added by upcoming patches. Signed-off-by:
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Imre Deak authored
There is no hard need for this to be a spin lock, as we don't take these locks in irq context from anywhere. An upcoming patch will add calls to punit read/write functions from within regions protected by this lock and those functions need a mutex in turn. As a solution for that convert the spin lock to be a mutex. Signed-off-by:
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Imre Deak authored
It is just cleaner this way and makes it easier to add support for other HW generations with always-on power wells powering a different set of domains. Signed-off-by:
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Imre Deak authored
Upcoming patches will add tracking for a set of power domains via a bitmask; to make things simple there remove the current gap in the enum values. Signed-off-by:
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Daniel Vetter authored
- Give them an _irq_handler postfix, like all the other irq stuff. - Shuffle the DEBUG_FS=n dummy functions around a bit. This is prep work to extract all the crc debug stuff into intel_display_testing.c Reviewed-by:
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Daniel Vetter authored
v2: Actually enable it. Reviewed-by:
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Daniel Vetter authored
Really simple, and we don't even have working frame numbers. v2: Actually enable it ... v3: Review from Ville: - Unconditionally enable the border in the CRC checksum for consistency with gen3+. - Handle the "none" source to be able to disable the CRC machinery again. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Daniel Vetter authored
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Daniel Vetter authored
On pre-gen5 and vlv we can't use the pipe source when TV-out or a DP port is connected to the pipe. Hence we need to expose new CRC sources. Also simplify the existing pipe source platform code a bit by rejecting all unhandled sources by default. Reviewed-by:
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Daniel Vetter authored
The PIPE_B #define was missing the display mmio offset. Use the _PIPE_INC macro instead, it's simpler. Reviewed-by:
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Daniel Vetter authored
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Daniel Vetter authored
And throw in a tiny for_each_pipe refactoring for gen2. Reviewed-by:
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Daniel Vetter authored
A bit a mess, since with DP/TV outputs we can't use the pipe CRC. Also, no plane CRCs, so we need to update the basic testcases. Reviewed-by:
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Daniel Vetter authored
Should work down to gen2. The #defines for the interrupt sources are already there in PIPESTAT and are the same on all gmch platforms for gen2 up to vlv. Reviewed-by:
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Chris Wilson authored
The current output looks like: Num Pipes: 2 Pipe [0]: SRC: 027f01df Plane [0]: CNTR: d9000000 STRIDE: 00001400 SIZE: 031f04ff POS: 00000000 ADDR: 00020000 Cursor [0]: CNTR: 00000000 POS: 00000000 BASE: 00000000 Pipe [1]: SRC: 04ff031f Plane [1]: CNTR: 01000000 STRIDE: 00000000 SIZE: 018f02cf POS: 00000000 ADDR: 00000000 Cursor [1]: CNTR: 00000000 POS: 00000000 BASE: 00000000 CPU transcoder: A CONF: 00000000 HTOTAL: 031f027f HBLANK: 03170287 HSYNC: 02ef028f VTOTAL: 020c01df VBLANK: 020401e7 VSYNC: 01eb01e9 CPU transcoder: B CONF: 80000000 HTOTAL: 059f04ff HBLANK: 059f04ff HSYNC: 054f052f VTOTAL: 0336031f VBLANK: 0336031f VSYNC: 03280322 which lacks the important visual clue to demarque the transcoder blocks from the last cursor. Signed-off-by:
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