1. 10 Nov, 2016 35 commits
  2. 01 Nov, 2016 3 commits
  3. 31 Oct, 2016 2 commits
    • Greg Kroah-Hartman's avatar
      Linux 4.4.29 · acd21d84
      Greg Kroah-Hartman authored
      acd21d84
    • Robert Jarzmik's avatar
      ARM: pxa: pxa_cplds: fix interrupt handling · 590a3eda
      Robert Jarzmik authored
      commit 9ba63e3c upstream.
      
      Since its initial commit, the driver is buggy for multiple interrupts
      handling. The translation from the former lubbock.c file was not
      complete, and might stall all interrupt handling when multiple
      interrupts occur.
      
      This is especially true when inside the interrupt handler and if a new
      interrupt comes and is not handled, leaving the output line still held,
      and not creating a transition as the GPIO block behind would expect to
      trigger another cplds_irq_handler() call.
      
      For the record, the hardware is working as follows.
      
      The interrupt mechanism relies on :
       - one status register
       - one mask register
      
      Let's suppose the input irq lines are called :
       - i_sa1111
       - i_lan91x
       - i_mmc_cd
      Let's suppose the status register for each irq line is called :
       - status_sa1111
       - status_lan91x
       - status_mmc_cd
      Let's suppose the interrupt mask for each irq line is called :
       - irqen_sa1111
       - irqen_lan91x
       - irqen_mmc_cd
      Let's suppose the output irq line, connected to GPIO0 is called :
       - o_gpio0
      
      The behavior is as follows :
       - o_gpio0 = not((status_sa1111 & irqen_sa1111) |
      		 (status_lan91x & irqen_lan91x) |
      		 (status_mmc_cd & irqen_mmc_cd))
         => this is a N-to-1 NOR gate and multiple AND gates
       - irqen_* is exactly as programmed by a write to the FPGA
       - status_* behavior is governed by a bi-stable D flip-flop
         => on next FPGA clock :
           - if i_xxx is high, status_xxx becomes 1
           - if i_xxx is low, status_xxx remains as it is
           - if software sets status_xxx to 0, the D flip-flop is reset
             => status_xxx becomes 0
             => on next FPGA clock cycle, if i_xxx is high, status_xxx becomes
      	  1 again
      
      Fixes: fc9e38c0 ("ARM: pxa: lubbock: use new pxa_cplds driver")
      Reported-by: default avatarRussell King <rmk+kernel@armlinux.org.uk>
      Signed-off-by: default avatarRobert Jarzmik <robert.jarzmik@free.fr>
      Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      590a3eda