- 27 Jul, 2020 34 commits
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Mauro Rossi authored
[Why] hw_factory.c requires changes for DCE6 support [How] DCE6 targets added replicating and adapting existing DCE8 implementation. (v2) changes due to following commit: 91db9311 ("drm/amd/display: refactor gpio to allocate hw_container in constructor") Reviewed-by:Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Mauro Rossi <issor.oruam@gmail.com> Signed-off-by:
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Mauro Rossi authored
[Why] command_table_helper.c requires changes for DCE6 support [How] DCE6 targets added replicating and adapting the existing DCE8 implementation. Reviewed-by:
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Mauro Rossi authored
[Why] resource_parse_asic_id() and dc_create_resource_pool() are missing SI/DCE6 cases [How] SI/DCE6 cases support added using existing DCE8 implementation as a reference (v2) updated due to following kernel 5.2 commit: d9673c92 ("drm/amd/display: Pass init_data into DCN resource creation") Reviewed-by: -
Mauro Rossi authored
[Why] DCE6 chipsets have a lot in common with DCE8, let's start from this [How] DCE6 targets are added replicating existing DCE8 implementation. NOTE: dce_8_0_{d,sh_mask}.h headers used instead of dce_6_0_{d,sh_mask}.h initial build prototype due to missing DCE6 macros/registers/masks DCE6 specific macros/registers/masks will be added with later commits (v2b) removed dce_version cases in dc/dce/dce_clock_source.c and updated dce60 due to following kernel 5.0 commits: 24f7dd7e ("drm/amd/display: move pplib/smu notification to dccg block") 9566b675 ("drm/amd/display: remove safe_to_lower flag from dc, use 2 functions instead") 4244381c ("drm/amd/display: clean up base dccg struct") 4c5e8b54 ("drm/amd/display: split dccg clock manager into asic folders") 84e7fc0 ("drm/amd/display: rename dccg to clk_mgr") 77f6916a ("drm/amd/display: Remove duplicate header") 9f7ddbea ("drm/amd/display: fix optimize_bandwidth func pointer for dce80") 4ece61a2 ("drm/amd/display: set clocks to 0 on suspend on dce80") (v3b) updated dce60 due to following kernel 5.1 commits: 380604e2 ("drm/amd/display: Use 100 Hz precision for pipe pixel clocks") 32e61361 ("drm/amd/display: Fix 64-bit division for 32-bit builds") 1877ccf6 ("drm/amd/display: Change from aux_engine to dce_aux") c69dffab ("drm/amd/display: fix eDP fast bootup for pre-raven asic") (v4b) updated dce60 due to following kernel 5.2 commits: e5c41970 ("drm/amd/display: Add plane capabilities to dc_caps") 813d20dc ("drm/amd/display: Fix multi-thread writing to 1 state") ea36ad34 ("drm/amd/display: expand plane caps to include fp16 and scaling capability") afcd526b ("drm/amd/display: Add fast_validate parameter") (v5b) updated dce60 due to following kernel 5.3 commits: e7e10c46 ("drm/amd/display: stop external access to internal optc sync params") 78cc70b1 ("drm/amd/display: Engine-specific encoder allocation") dc88b4a6 ("drm/amd/display: make clk mgr soc specific") 4fc4dca8 ("drm/amd: drop use of drmp.h in os_types.h") (v6b) updated dce60 due to following kernel 5.4 commits: 54a9bcb0 ("drm/amd/display: Fix a typo - dce_aduio_mask --> dce_audio_mask") 9adc8050 ("drm/amd/display: make firmware info only load once during dc_bios create") (v7b) updated dce60 due to following kernel 5.5 commits: cabe144b ("drm/amd/display: memory leak") 8276dd87 ("drm/amd/display: update register field access mechanism") f6040a43 ("drm/amd/display: configurable aux timeout support") bf7f5ac3 ("drm/amd/display: map TRANSMITTER_UNIPHY_x to LINK_REGS_x") (v8b) updated dce60 due to following kernel 5.6 commits: d9e32672 ("drm/amd/display: cleanup of construct and destruct funcs") f42ea55b ("drm/amd/display: add separate of private hwss functions") (v9b) updated dce60 due to following kernel 5.8 commits: bba8289 ("drm/amd/display: code clean up in dce80_hw_sequencer.c") 904fb6e0 ("drm/amd/display: move panel power seq to new panel struct") d4caa72e ("drm/amd/display: change from panel to panel cntl") (v10) Fix up PLL handling for DCE6: DCE6.0 supports 2 PLLs. DCE6.1 supports 3 PLLs. (Alex) Reviewed-by: -
Mauro Rossi authored
[Why] Asic info for SI parts need to be preliminarly added [How] Asics info retrieved from si_id.h in https://github.com/GPUOpen-Tools/CodeXL Tree path: ./CodeXL/Components/ShaderAnalyzer/AMDTBackEnd/Include/Common/asic_reg/si_id.h Reviewed-by:
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Alex Deucher authored
To help with the DC port. v2: add missing masks, add additional registers v3: more updates v4: fix accidently dropped changes v5: add missing nb pstate mask v6: add vblank, vline masks v7: add SCL_HORZ_FILTER_INIT regs Signed-off-by: -
Dan Carpenter authored
These tables have _COUNT number of elements so the comparisons should be >= instead of > to prevent reading one element beyond the end of the array. Fixes: 8264ee69 ("drm/amd/powerplay: drop unused code") Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
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Christophe JAILLET authored
The wrappers in include/linux/pci-dma-compat.h should go away. The patch has been generated with the coccinelle script below and has been hand modified to replace GFP_ with a correct flag. It has been compile tested. When memory is allocated in 'radeon_gart_table_ram_alloc()' GFP_KERNEL can be used because its callers already use this flag. Both 'r100_pci_gart_init()' (r100.c) and 'rs400_gart_init()' (rs400.c) call 'radeon_gart_init()'. This function uses 'vmalloc'. @@ @@ - PCI_DMA_BIDIRECTIONAL + DMA_BIDIRECTIONAL @@ @@ - PCI_DMA_TODEVICE + DMA_TO_DEVICE @@ @@ - PCI_DMA_FROMDEVICE + DMA_FROM_DEVICE @@ @@ - PCI_DMA_NONE + DMA_NONE @@ expression e1, e2, e3; @@ - pci_alloc_consistent(e1, e2, e3) + dma_alloc_coherent(&e1->dev, e2, e3, GFP_) @@ expression e1, e2, e3; @@ - pci_zalloc_consistent(e1, e2, e3) + dma_alloc_coherent(&e1->dev, e2, e3, GFP_) @@ expression e1, e2, e3, e4; @@ - pci_free_consistent(e1, e2, e3, e4) + dma_free_coherent(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_map_single(e1, e2, e3, e4) + dma_map_single(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_unmap_single(e1, e2, e3, e4) + dma_unmap_single(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4, e5; @@ - pci_map_page(e1, e2, e3, e4, e5) + dma_map_page(&e1->dev, e2, e3, e4, e5) @@ expression e1, e2, e3, e4; @@ - pci_unmap_page(e1, e2, e3, e4) + dma_unmap_page(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_map_sg(e1, e2, e3, e4) + dma_map_sg(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_unmap_sg(e1, e2, e3, e4) + dma_unmap_sg(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_dma_sync_single_for_cpu(e1, e2, e3, e4) + dma_sync_single_for_cpu(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_dma_sync_single_for_device(e1, e2, e3, e4) + dma_sync_single_for_device(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_dma_sync_sg_for_cpu(e1, e2, e3, e4) + dma_sync_sg_for_cpu(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_dma_sync_sg_for_device(e1, e2, e3, e4) + dma_sync_sg_for_device(&e1->dev, e2, e3, e4) @@ expression e1, e2; @@ - pci_dma_mapping_error(e1, e2) + dma_mapping_error(&e1->dev, e2) @@ expression e1, e2; @@ - pci_set_dma_mask(e1, e2) + dma_set_mask(&e1->dev, e2) @@ expression e1, e2; @@ - pci_set_consistent_dma_mask(e1, e2) + dma_set_coherent_mask(&e1->dev, e2) Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by:
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Christophe JAILLET authored
Avoid a memset after a call to 'dma_alloc_coherent()'. This is useless since commit 518a2f19 ("dma-mapping: zero memory returned from dma_alloc_*") Reviewed-by:
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Bhawanpreet Lakha authored
Use DCN21 functions instead of DCE110 Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by:
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Bhawanpreet Lakha authored
[Why] Currently navy_flounder is using sienna_cichlid_dmcub.bin. [How] Create a seperate define so navy_flounder will use its own firmware. Signed-off-by:
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Martin Tsai authored
[Why] Some monitors could suffer symbol unlock but cannot send HPD IRQ to notic source device to handle link loss. This makes monitor stuck in abnormal status and causes black screen. [How] According to the suggestion from scalar vendor, to check lane status again after link training done. That can improve the comaptibility from current production monitors. Signed-off-by:
Martin Tsai <martin.tsai@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
Eryk Brol <eryk.brol@amd.com> Signed-off-by:
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Alvin Lee authored
[Why] In dcn3_update_clocks there are situations where dppclk is not lowered (i.e. stays the same), but DTO still needs to be increased before we program pipe frontend (i.e. in prepare_bandwidth). If we don't program the new DTO value before we program the pipe, we will underflow as soon as the pipe lock is released until the next call to dcn3_update_clocks where the DTO is updated. [How] Remove dppclk check before programming new DTO value. Signed-off-by:
Alvin Lee <alvin.lee2@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Eryk Brol authored
[why] Fix naming and return bits rather than bytes per pixel for naming consistency. Because registers return Bytes per pixel, but DSC Config structure is expecting bits per pixel as input. So when returning the value convert from bytes into bits. Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Reviewed-by:
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Eryk Brol authored
[Why] Struct dcn_dsc_state is used for reading current state and parameters of DSC on a pipe, the target rate parameter uses bytes per pixel even though its reading BITS_PER_PIXEL register. [How] Changing it to Bits Per Pixel for consistency. Signed-off-by:
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Dmytro Laktyushkin authored
[Why] This change replaces older looping code in favor of these functions. [How] There are built in functions for extracting global sync params during mode validation now. Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
Eric Bernstein <Eric.Bernstein@amd.com> Acked-by:
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Kevin Wang authored
1. allow asic to handle sensor type by itself. 2. if not, use smu common sensor to handle it. Signed-off-by:
Kevin Wang <kevin1.wang@amd.com> Reviewed-by:
Kenneth Feng <kenneth.feng@amd.com> Signed-off-by:
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John Clements authored
added support for umc 8.7 error reporting and query Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
John Clements <john.clements@amd.com> Signed-off-by:
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Likun Gao authored
Update sienna_cichlid driver if header and related files. Support new smu metrics for pre & postDS frequency. Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
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John Clements authored
the change introduces IP headers for unified memory controller (umc) Reviewed-by:
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Evan Quan authored
The current outputs of amdgpu_pm_info debugfs come with clock gating status and followed by current clock/power information. However the clock gating status retrieving may pull GFX out of CG status. That will make the succeeding clock/power information retrieving inaccurate. To overcome this and be with minimum impact, the outputs are updated to show current clock/power information first. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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James Zhu authored
This reverts commit 058c07201ec7d373fc6a0a570b38a8a9d62c29fb. Chip NAVY_FLOUNDER uses vcn3.0, but it has only one VCN instance. Signed-off-by:
James Zhu <James.Zhu@amd.com> Signed-off-by:
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Jay Cornwall authored
s_barrier triggers a debug exception when issued with PRIV=1, DEBUG_EN=1. This causes spurious notifications to rocm-gdb. Clear MODE before issuing s_barrier and restore MODE afterwards in the context restore handler. Signed-off-by:
Jay Cornwall <jay.cornwall@amd.com> Tested-by:
Laurent Morichetti <laurent.morichetti@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Changfeng authored
Take back patch:drop unnecessary message support check Because the gpu reset fail problem on renoir can be fixed by: drm/amd/powerplay: skip invalid msg when smu set mp1 state It needs to remove SWSMU_CODE_LAYER_L1 in smu_cmn.h to guard a clear code layer. Signed-off-by:
changfeng <Changfeng.Zhu@amd.com> Reviewed-by:
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Mukul Joshi authored
Add support for reporting thermal throttling events through SMI. Also, add a counter to count the number of throttling interrupts observed and report the count in the SMI event message. Signed-off-by:
Mukul Joshi <mukul.joshi@amd.com> Reviewed-by:
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Dennis Li authored
when GPU hang, driver has multi-paths to enter amdgpu_device_gpu_recover, the atomic adev->in_gpu_reset and hive->in_reset are used to avoid re-entering GPU recovery. During GPU reset and resume, it is unsafe that other threads access GPU, which maybe cause GPU reset failed. Therefore the new rw_semaphore adev->reset_sem is introduced, which protect GPU from being accessed by external threads during recovery. v2: 1. add rwlock for some ioctls, debugfs and file-close function. 2. change to use dqm->is_resetting and dqm_lock for protection in kfd driver. 3. remove try_lock and change adev->in_gpu_reset as atomic, to avoid re-enter GPU recovery for the same GPU hang. v3: 1. change back to use adev->reset_sem to protect kfd callback functions, because dqm_lock couldn't protect all codes, for example: free_mqd must be called outside of dqm_lock; [ 1230.176199] Hardware name: Supermicro SYS-7049GP-TRT/X11DPG-QT, BIOS 3.1 05/23/2019 [ 1230.177221] Call Trace: [ 1230.178249] dump_stack+0x98/0xd5 [ 1230.179443] amdgpu_virt_kiq_reg_write_reg_wait+0x181/0x190 [amdgpu] [ 1230.180673] gmc_v9_0_flush_gpu_tlb+0xcc/0x310 [amdgpu] [ 1230.181882] amdgpu_gart_unbind+0xa9/0xe0 [amdgpu] [ 1230.183098] amdgpu_ttm_backend_unbind+0x46/0x180 [amdgpu] [ 1230.184239] ? ttm_bo_put+0x171/0x5f0 [ttm] [ 1230.185394] ttm_tt_unbind+0x21/0x40 [ttm] [ 1230.186558] ttm_tt_destroy.part.12+0x12/0x60 [ttm] [ 1230.187707] ttm_tt_destroy+0x13/0x20 [ttm] [ 1230.188832] ttm_bo_cleanup_memtype_use+0x36/0x80 [ttm] [ 1230.189979] ttm_bo_put+0x1be/0x5f0 [ttm] [ 1230.191230] amdgpu_bo_unref+0x1e/0x30 [amdgpu] [ 1230.192522] amdgpu_amdkfd_free_gtt_mem+0xaf/0x140 [amdgpu] [ 1230.193833] free_mqd+0x25/0x40 [amdgpu] [ 1230.195143] destroy_queue_cpsch+0x1a7/0x270 [amdgpu] [ 1230.196475] pqm_destroy_queue+0x105/0x260 [amdgpu] [ 1230.197819] kfd_ioctl_destroy_queue+0x37/0x70 [amdgpu] [ 1230.199154] kfd_ioctl+0x277/0x500 [amdgpu] [ 1230.200458] ? kfd_ioctl_get_clock_counters+0x60/0x60 [amdgpu] [ 1230.201656] ? tomoyo_file_ioctl+0x19/0x20 [ 1230.202831] ksys_ioctl+0x98/0xb0 [ 1230.204004] __x64_sys_ioctl+0x1a/0x20 [ 1230.205174] do_syscall_64+0x5f/0x250 [ 1230.206339] entry_SYSCALL_64_after_hwframe+0x49/0xbe 2. remove try_lock and introduce atomic hive->in_reset, to avoid re-enter GPU recovery. v4: 1. remove an unnecessary whitespace change in kfd_chardev.c 2. remove comment codes in amdgpu_device.c 3. add more detailed comment in commit message 4. define a wrap function amdgpu_in_reset v5: 1. Fix some style issues. Reviewed-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Suggested-by:
Lijo Lazar <Lijo.Lazar@amd.com> Suggested-by:
Luben Tukov <luben.tuikov@amd.com> Signed-off-by:
Dennis Li <Dennis.Li@amd.com> Signed-off-by:
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Boyuan Zhang authored
Signed-off-by:
Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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Colin Ian King authored
The variable result is being initialized with a value that is never read and it is being updated later with a new value. The initialization is redundant and can be removed. Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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James Zhu authored
vcn ip block is already selected based on ASIC type during set_ip_blocks. Signed-off-by:
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James Zhu authored
jpeg ip block is already selected based on ASIC type during set_ip_blocks. Signed-off-by:
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Laurent Morichetti authored
Add some padding before the MODE register in the HWREGs block to preserve the same layout as gfx9. This simplifies implementation of a user-mode debugger. Signed-off-by:
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Tom St Denis authored
Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
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James Zhu authored
vcn ip block is already selected based on ASIC type during set_ip_blocks Signed-off-by:
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James Zhu authored
jpeg ip block is already selected based on ASIC type during set_ip_blocks. Signed-off-by:
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- 23 Jul, 2020 6 commits
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Alex Deucher authored
We expose the actual memory controller clock rate in Linux, not the effective memory clock of the DRAMs. To translate it, it follows the following formula: Clock conversion (Mhz): HBM: effective_memory_clock = memory_controller_clock * 1 G5: effective_memory_clock = memory_controller_clock * 1 G6: effective_memory_clock = memory_controller_clock * 2 DRAM data rate (MT/s): HBM: effective_memory_clock * 2 = data_rate G5: effective_memory_clock * 4 = data_rate G6: effective_memory_clock * 8 = data_rate Bandwidth (MB/s): data_rate * vram_bit_width / 8 = memory_bandwidth Some examples: G5 on RX460: memory_controller_clock = 1750 Mhz effective_memory_clock = 1750 Mhz * 1 = 1750 Mhz data rate = 1750 * 4 = 7000 MT/s memory_bandwidth = 7000 * 128 bits / 8 = 112000 MB/s G6 on RX5600: memory_controller_clock = 900 Mhz effective_memory_clock = 900 Mhz * 2 = 1800 Mhz data rate = 1800 * 8 = 14400 MT/s memory_bandwidth = 14400 * 192 bits / 8 = 345600 MB/s Acked-by:
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Li Heng authored
Fix below warnings reported by coccicheck: ./drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c:557:2-7: WARNING: NULL check before some freeing functions is not needed. Fixes: 4d55b0dd ("drm/amd/display: Add DCN3 CLK_MGR") Signed-off-by:
Li Heng <liheng40@huawei.com> Signed-off-by:
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John Clements authored
certain umc macros are common across umc versions Reviewed-by:
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Likun Gao authored
Update golden setting for sienna_cichlid. Signed-off-by:
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Likun Gao authored
Set valid_in_vf to false for the message not support in vf mode on sienna cichlid. Signed-off-by:
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Likun Gao authored
Mapping Mode1Reset message for sienna_cichlid. Signed-off-by:
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