- 14 Jan, 2019 40 commits
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Hawking Zhang authored
get_fw_type and prep_cmd_buf should be common interface instead of IP specific ones Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Hawking Zhang authored
GFX_FW_TYPE_RLC_RESTORE_LIST_CNTL was renamed to GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL in latest psp_gfx_if drop Signed-off-by:
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Gustavo A. R. Silva authored
Fix boolean expressions by using logical AND operator '&&' instead of bitwise operator '&'. This issue was detected with the help of Coccinelle. Fixes: 9a4b7d4c ("drm/amdgpu: Add vm context module param") Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by:
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Emily Deng authored
When init fail, send rel init, req_fini and rel_fini to host for the finishing routine. Signed-off-by:
Emily Deng <Emily.Deng@amd.com> Reviewed-by:
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Gustavo A. R. Silva authored
Fix boolean expression by using logical AND operator '&&' instead of bitwise operator '&'. This issue was detected with the help of Coccinelle. Fixes: 6d04ee9d ("drm/amd/display: Restructuring and cleaning up DML") Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Christian König authored
Note if this is a retry fault or not and cleanup the message a bit. Signed-off-by:
Christian König <christian.koenig@amd.com> Acked-by:
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wentalou authored
distinguish ip_reinit_early_sriov and ip_reinit_late_sriov by different log RE-INIT-early and RE-INIT-late Signed-off-by:
Wentao Lou <Wentao.Lou@amd.com> Reviewed-by:
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Nicholas Kazlauskas authored
[Why] Hardware support for Delta Color Compression (DCC) decompression is available in DC for GFX9 but there's no way for userspace to enable the feature. Enabling the feature can provide improved GFX performance and power savings in many situations. [How] The GFX9 DCC parameters are passed to amdgpu_dm from AMDGPU via the amdgpu_bo tiling_flags. The plane capability is queried and the parameters are set accordingly. The DCC address is given via a 256 byte aligned offset on the framebuffer address. The DCC address is updated whenever the buffer address changes. Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by:
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Christian König authored
To distinct on which IH ring an IV was found. Signed-off-by:
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Christian König authored
When an ring buffer overflow happens the appropriate bit is set in the WPTR register which is also written back to memory. But clearing the bit in the WPTR doesn't trigger another memory writeback. So what can happen is that we end up processing the buffer overflow over and over again because the bit is never cleared. Resulting in a random system lockup because of an infinite loop in an interrupt handler. This is 100% reproducible on Vega10, but it's most likely an issue we have in the driver over all generations all the way back to radeon. v2: rebase Signed-off-by:
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Christian König authored
Calculate all the addresses and pointers in amdgpu_ih.c Signed-off-by:
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Christian König authored
Let's start to support multiple rings. v2: decode IV is needed as well Signed-off-by:
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Prike Liang authored
As the PG was setted by each IP block durinng IP early init thus remove the unused phm_enable_clock_power_gatings related funcs. Signed-off-by:
Prike Liang <Prike.Liang@amd.com> Reviewed-by:
Kenneth Feng <kenneth.feng@amd.com> Signed-off-by:
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Shirish S authored
Initializing structures with { } is known to be problematic since it doesn't necessararily initialize all bytes, in case of padding, causing random failures when structures are memcmp(). This patch fixes the structure initialisation related compiler error by memset(). V2: rectified missing piece in coding Signed-off-by:Shirish S <shirish.s@amd.com> Reviewed-by:
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Ken Chalmers authored
[Why] 32-bit builds break when doing 64-bit division directly. [How] Use the div_u64() function instead to perform the division. Fixes: https://lists.freedesktop.org/archives/dri-devel/2018-December/201008.htmlSigned-off-by:
Ken Chalmers <ken.chalmers@amd.com> Reviewed-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
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Shirish S authored
Initializing structures with { } is known to be problematic since it doesn't necessararily initialize all bytes, in case of padding, causing random failures when structures are memcmp(). This patch fixes the structure initialisation related compiler error by memset. Signed-off-by: -
Ken Chalmers authored
[Why] For more informative debugging. [How] Add timing generator and PLL ids to output, to make it clear which pixel clock is being set. Signed-off-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Brajeswar Ghosh authored
Remove reg_helper.h which is included more than once Signed-off-by:
Brajeswar Ghosh <brajeswar.linux@gmail.com> Signed-off-by:
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Brajeswar Ghosh authored
Remove custom_float.h which is included more than once Signed-off-by:
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Brajeswar Ghosh authored
Remove custom_float.h which is included more than once Acked-by:
Souptick Joarder <jrdr.linux@gmail.com> Signed-off-by:
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Colin Ian King authored
There are several variables that are defined and never used and hence can be removed. Remove them. Cleans up clang -Wunused-const-variable warnings: warning: ‘dvi_hdmi_dongle_signature_str’ defined but not used warning: ‘dce11_one_lpt_channel_max_resolution’ defined but not used warning: ‘ddc_hw_status_addr’ defined but not used Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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David Francis authored
[Why] The function dc_commit_updates_for_stream had a parameter called plane_states. It was never used. It was getting in the way of some cleanup work [How] Remove it Signed-off-by:
David Francis <David.Francis@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
This will allow us to program dscclk to required value Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
Eric Bernstein <Eric.Bernstein@amd.com> Acked-by:
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Fatemeh Darbehani authored
[Why] PPLib has impelemented the new pp_smu interface [How] Use the new functions if available instead of the old interface 'set_display_requirement' and 'dcn1_pplib_apply_display_requirements'. Signed-off-by:
Fatemeh Darbehani <fatemeh.darbehani@amd.com> Reviewed-by:
Su Chung <Su.Chung@amd.com> Signed-off-by:
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Steven Chiu authored
Signed-off-by:
Steven Chiu <steven.chiu@amd.com> Reviewed-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
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Leo Li authored
[Why] When XGMI is enabled, we need to adjust the dprefclk according to the WAFL link's spread spectrum info. This is for VG20 (DCE121) only. [How] dce_clk_mgr already stores SS info, currently being used by audio clock. Therefore, patch the clk_mgr's SS info with the xGMI SS info, if xGMI is enabled. For display clock, adjust it during dce12_update_clocks() before calling set_clock(). Since we rely on a mmhub register to reliably determine if xGMI is enabled, the patching step needs to happen after resource_construct() has initialized the hardware sequencer. Signed-off-by:
Hersen Wu <hersenxs.wu@amd.com> Acked-by:
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Leo Li authored
[Why] This fixes an regression introduced by: drm/amd/display: add stream ID and otg instance in dc_stream_state During driver initialization, a null pointer deref is raised. This is caused by searching for a stream status in the dc->current_state before the dc_state swap happens at the end of dc_commit_state_no_check(). Since the swap has not happened, the dc_state to be swapped in should be searched, and not dc->current_state. [How] Add a function that searches for the stream status within the given dc_state, instead of dc->current_state. Use that before the state swap happens in dc_commit_state_no_check(). Also remove duplicate occurrences of this function in amdgpu_dm.c. Signed-off-by: -
Leo Li authored
[Why] context->bw.dce.dispclk_khz is being cached into unpatched_clock, then restored at end of function call. This is needlessly complex [How] Instead, use a local patched_clock variable. Leave context->bw.dce.dispclk_khz alone. No functional change is intended. Signed-off-by:
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Eric Bernstein authored
[Why] There are different reasons for Validation failure error during atomic_check [How] Add better logging of the reason for validation failure Signed-off-by:
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Ken Chalmers authored
[Why] Users would like more accurate pixel clocks, especially for fractional "TV" frame rates like 59.94 Hz. [How] Store and communicate pixel clocks with 100 Hz accuracy from dc_crtc_timing through to BIOS command table setpixelclock call. Signed-off-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
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SivapiriyanKumarasamy authored
[WHY] There is an extra null check for fs_params in the build_freesync_hdr function detected by Smatch. [HOW] 1) Remove the extra null check since it is checked in the caller. Signed-off-by:
SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
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Leo Li authored
[Why] It's not being used anywhere. [How] Remove it. Signed-off-by:
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Steven Chiu authored
Signed-off-by:
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David Francis authored
[Why] ABM enablement testing can be automated if a way of reading target and current hardware backlight is available [How] Expand debugfs interface with two new entries. Hook directly into dc interface. Units are as a fraction of 0x1000 = 100% Use the built-in amdgpu function for creating read-only debugfs files Signed-off-by:
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Jun Lei authored
[why] stream ID allows DMs to avoid memory address comparisons to compare stream equality. otg_instance allows DC to more rigorously define when otg_instance can change. specifically, it is now defined to be only mutable when dc_stream_state changes. This is better than a "get status" function which prevents efficient caching of otherwise very stable information. [how] stream ID follows similar pattern to sink ID, which is already implemented otg_instance is an output which occurs on all dc_stream modification functions Signed-off-by:
Jun Lei <Jun.Lei@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
DV have made updates to DCN dml which we need to pull in Signed-off-by:
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David Francis authored
[Why] Backlight is conceptually a property of links, not streams. All backlight programming is done on links, but there is a stream property bl_pwm_level that is used to restore backlight on dpms on and s3 resume. This is unnecessary, as backlight is already restored by hardware with no driver intervention. [How] Remove bl_pwm_level, and the stream argument to set_backlight Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Imad Syed authored
They're not being used, so remove them. Signed-off-by:
Imad Syed <imad.syed@amd.com> Reviewed-by:
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Jun Lei authored
[why] dc_stream_state containing a pointer to sink is poor design. Sink describes the display, and the specifications or capabilities it has. That information is irrelevant for dc_stream_state, which describes hardware state, and is generally used for hardware programming. It could further be argued that dc_sink itself is just a convenience dc provides, and DC should be perfectly capable of programming hardware without any dc_sinks (for example, emulated sinks). [how] Phase 1: Deprecate use of dc_sink pointer in dc_stream. Most references are trivial to remove, but some call sites are risky (such as is_timing_changed) with no obvious logical replacement. These will be removed in follow up change. Add dc_link pointer to dc_stream. This is the typical reason DC really needed sink pointer, and most call sites are replaced with this. DMs also need minor updates, as all 3 DMs leverage stream->sink for some functionality. this is replaced instead by a pointer to private data inside dc_stream_state, which is used by DMs as a quality of life improvment for some key functionality. it allows DMs to set pointers have to their own objects which associate OS objects to dc_stream_states (such as DisplayTarget and amdgpu_dm_connector). Without the private pointer, DMs would be forced to perform a lookup for callbacks. Signed-off-by:
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Hugo Hu authored
[Why] So that we can adjust fclk for debugging purposes. [How] Add option to force adjust fclk request to pplib. Signed-off-by:
Hugo Hu <hugo.hu@amd.com> Reviewed-by:
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