- 17 Jan, 2019 4 commits
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Alban Bedel authored
The custom setup/cleanup routines included in the ath79 driver only take care of setting the initial CS state. However that is already handled by the bitbang code, so this code can be removed. Signed-off-by:
Alban Bedel <albeu@free.fr> Signed-off-by:
Mark Brown <broonie@kernel.org>
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Alban Bedel authored
To allow building this driver in compile test we need to remove all dependency on headers from arch/mips/include. To allow this we explicitly define all the registers locally instead of using ar71xx_regs.h and we move the platform data struct definition to include/linux/platform_data/spi-ath79.h. Signed-off-by:
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Alban Bedel authored
First of all this callback was slightly misused to setup the clock polarity at the beginning of a transfer. Beside being at the wrong place, it is also useless as only SPI mode 1 is supported. Instead just make sure the base value used for IOC is suitable to start a transfer by clearing the clock and data bits during the controller setup. This also remove the last direct usage of the GPIO API, so we can remove the direct dependency on GPIOLIB. Signed-off-by:
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Alban Bedel authored
spi_setup() already call spi_set_cs() right after calling the controller setup method, so there is no need for the bitbang driver to do that. Because of this the chipselect() callback was confusingly still called when CS is GPIO based. Signed-off-by:
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- 14 Jan, 2019 3 commits
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Charles Keepax authored
Currently the driver calls pm_runtime_put_autosuspend but without ever having done a pm_runtime_get, this causes the reference count in the pm runtime core to become -1. The bad reference count causes the core to sometimes suspend whilst an active SPI transfer is in progress. arizona spi0.1: SPI transfer timed out spi_master spi0: failed to transfer one message from queue The correct proceedure is to do all the initialisation that requires the hardware to be powered up before enabling the PM runtime, then enable the PM runtime having called pm_runtime_set_active to inform it that the hardware is currently powered up. The core will then power it down at it's leisure and no explicit pm_runtime_put is required. Fixes: d36ccd9f ("spi: cadence: Runtime pm adaptation") Signed-off-by:
Charles Keepax <ckeepax@opensource.cirrus.com> Signed-off-by:
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Stephen Boyd authored
We don't need this forward declaration. Move the function to where it needed so we can drop it and shave some lines of code. CC: Girish Mahadevan <girishm@codeaurora.org> CC: Dilip Kota <dkota@codeaurora.org> CC: Alok Chauhan <alokc@codeaurora.org> Cc: Douglas Anderson <dianders@chromium.org> Signed-off-by:
Stephen Boyd <swboyd@chromium.org> Signed-off-by:
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Stephen Boyd authored
We only use this completion when we're doing something that isn't a message transfer. For example, changing CS or aborting/canceling a command. All of those situations properly reinitialize the completion before sending the GENI the special command to change CS or cancel, etc. Given that, let's remove the initialization here. Cc: Girish Mahadevan <girishm@codeaurora.org> Cc: Dilip Kota <dkota@codeaurora.org> Cc: Alok Chauhan <alokc@codeaurora.org> Cc: Douglas Anderson <dianders@chromium.org> Signed-off-by:
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- 10 Jan, 2019 2 commits
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Linus Walleij authored
The previous commit left a variable unused, my bad. Clean it up. Cc: Stephen Rothwell <sfr@canb.auug.org.au> Cc: David Lechner <david@lechnology.com> Reported-by:
Stephen Rothwell <sfr@canb.auug.org.au> Fixes: 101a68e7 ("spi: davinci: Convert to use CS GPIO descriptors") Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
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Anders Roxell authored
When CONFIG_SPI_DESIGNWARE are enabled we see the unused variable warning in dw_spi_setup. ../drivers/spi/spi-dw.c: In function ‘dw_spi_setup’: ../drivers/spi/spi-dw.c:400:6: warning: unused variable ‘ret’ [-Wunused-variable] int ret; ^~~ Remove the unused varable. Fixes: 9400c41e ("spi: dw: Convert to use CS GPIO descriptors") Reported-by:Anders Roxell <anders.roxell@linaro.org> Signed-off-by:
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- 09 Jan, 2019 8 commits
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Martin Sperl authored
When spi_sync is running alone with no other spi devices connected to the bus the worker thread is woken during spi_finalize_current_message to run the teardown code every time. This is totally unnecessary in the case that there is no message queued. On a multi-core system this results in one wakeup of the thread for each spi_message processed via spi_sync where in most cases the teardown does not happen as the hw is already in use. This patch now delays the teardown by 1 second by using a separate kthread_delayed_work for the teardown. This avoids waking the kthread too often. For spi_sync transfers in a tight loop (say 40k messages/s) this avoids the penalty of waking the worker thread 40k times/s. On a rasperry pi 3 with 4 cores the results in 32% of a single core only to find out that there is nothing in the queue and it can go back to sleep. With this patch applied the spi-worker is woken exactly once: after the load finishes and the spi bus is idle for 1 second. I believe I have also seen situations where during a spi_sync loop the worker thread (triggered by the last message finished) is slightly faster and _wins_ the race to process the message, so we are actually running the kthread and letting it do some work... This is also no longer observed with this patch applied as. Tested with a new CAN controller driver for the mcp2517fd which uses spi_sync for interrupt handling and spi_async for scheduling of can frames for transmission (in a different thread) Some statistics when receiving 100000 CAN frames with the mcp25xxfd driver on a Raspberry pi 3: without the patch: ------------------ root@raspcm3:~# for x in $(pgrep spi0) $(pgrep irq/94-mcp25xxf) ; do awk '{printf "%-20s %6i\n", $2,$15}' /proc/$x/stat; done (spi0) 5 (irq/94-mcp25xxf) 0 root@raspcm3:~# vmstat 1 procs -----------memory---------- ---swap-- -----io---- -system-- ------cpu----- r b swpd free buff cache si so bi bo in cs us sy id wa st 1 0 0 821960 13592 50848 0 0 80 2 1986 105 1 2 97 0 0 0 0 0 821968 13592 50876 0 0 0 0 8046 30 0 0 100 0 0 0 0 0 821936 13592 50876 0 0 0 0 8032 24 0 0 100 0 0 0 0 0 821936 13592 50876 0 0 0 0 8035 30 0 0 100 0 0 0 0 0 821936 13592 50876 0 0 0 0 8033 22 0 0 100 0 0 2 0 0 821936 13592 50876 0 0 0 0 11598 7129 0 3 97 0 0 1 0 0 821872 13592 50876 0 0 0 0 37741 59003 0 31 69 0 0 2 0 0 821840 13592 50876 0 0 0 0 37762 59078 0 29 71 0 0 2 0 0 821776 13592 50876 0 0 0 0 37593 58792 0 28 72 0 0 1 0 0 821744 13592 50876 0 0 0 0 37642 58881 0 30 70 0 0 2 0 0 821680 13592 50876 0 0 0 0 37490 58602 0 27 73 0 0 1 0 0 821648 13592 50876 0 0 0 0 37412 58418 0 29 71 0 0 1 0 0 821584 13592 50876 0 0 0 0 37337 58288 0 27 73 0 0 1 0 0 821552 13592 50876 0 0 0 0 37584 58774 0 27 73 0 0 0 0 0 821520 13592 50876 0 0 0 0 18363 20566 0 9 91 0 0 0 0 0 821520 13592 50876 0 0 0 0 8037 32 0 0 100 0 0 0 0 0 821520 13592 50876 0 0 0 0 8031 23 0 0 100 0 0 0 0 0 821520 13592 50876 0 0 0 0 8034 26 0 0 100 0 0 0 0 0 821520 13592 50876 0 0 0 0 8033 24 0 0 100 0 0 ^C root@raspcm3:~# for x in $(pgrep spi0) $(pgrep irq/94-mcp25xxf) ; do awk '{printf "%-20s %6i\n", $2,$15}' /proc/$x/stat; done (spi0) 228 (irq/94-mcp25xxf) 794 root@raspcm3:~# cat /proc/interrupts CPU0 CPU1 CPU2 CPU3 17: 34 0 0 0 ARMCTRL-level 1 Edge 3f00b880.mailbox 27: 1 0 0 0 ARMCTRL-level 35 Edge timer 33: 1416870 0 0 0 ARMCTRL-level 41 Edge 3f980000.usb, dwc2_hsotg:usb1 34: 1 0 0 0 ARMCTRL-level 42 Edge vc4 35: 0 0 0 0 ARMCTRL-level 43 Edge 3f004000.txp 40: 1753 0 0 0 ARMCTRL-level 48 Edge DMA IRQ 42: 11 0 0 0 ARMCTRL-level 50 Edge DMA IRQ 44: 11 0 0 0 ARMCTRL-level 52 Edge DMA IRQ 45: 0 0 0 0 ARMCTRL-level 53 Edge DMA IRQ 66: 0 0 0 0 ARMCTRL-level 74 Edge vc4 crtc 69: 0 0 0 0 ARMCTRL-level 77 Edge vc4 crtc 70: 0 0 0 0 ARMCTRL-level 78 Edge vc4 crtc 77: 20 0 0 0 ARMCTRL-level 85 Edge 3f205000.i2c, 3f804000.i2c, 3f805000.i2c 78: 6346 0 0 0 ARMCTRL-level 86 Edge 3f204000.spi 80: 205 0 0 0 ARMCTRL-level 88 Edge mmc0 81: 493 0 0 0 ARMCTRL-level 89 Edge uart-pl011 89: 0 0 0 0 bcm2836-timer 0 Edge arch_timer 90: 4291 3821 2180 1649 bcm2836-timer 1 Edge arch_timer 94: 14289 0 0 0 pinctrl-bcm2835 16 Level mcp25xxfd IPI0: 0 0 0 0 CPU wakeup interrupts IPI1: 0 0 0 0 Timer broadcast interrupts IPI2: 3645 242371 7919 1328 Rescheduling interrupts IPI3: 112 543 273 194 Function call interrupts IPI4: 0 0 0 0 CPU stop interrupts IPI5: 1 0 0 0 IRQ work interrupts IPI6: 0 0 0 0 completion interrupts Err: 0 top shows 93% for the mcp25xxfd interrupt handler, 31% for spi0. with the patch: --------------- root@raspcm3:~# for x in $(pgrep spi0) $(pgrep irq/94-mcp25xxf) ; do awk '{printf "%-20s %6i\n", $2,$15}' /proc/$x/stat; done (spi0) 0 (irq/94-mcp25xxf) 0 root@raspcm3:~# vmstat 1 procs -----------memory---------- ---swap-- -----io---- -system-- ------cpu----- 0 0 0 804768 13584 62628 0 0 0 0 8038 24 0 0 100 0 0 0 0 0 804768 13584 62628 0 0 0 0 8042 25 0 0 100 0 0 1 0 0 804704 13584 62628 0 0 0 0 9603 2967 0 20 80 0 0 1 0 0 804672 13584 62628 0 0 0 0 9828 3380 0 24 76 0 0 1 0 0 804608 13584 62628 0 0 0 0 9823 3375 0 23 77 0 0 1 0 0 804608 13584 62628 0 0 0 12 9829 3394 0 23 77 0 0 1 0 0 804544 13584 62628 0 0 0 0 9816 3362 0 22 78 0 0 1 0 0 804512 13584 62628 0 0 0 0 9817 3367 0 23 77 0 0 1 0 0 804448 13584 62628 0 0 0 0 9822 3370 0 22 78 0 0 1 0 0 804416 13584 62628 0 0 0 0 9815 3367 0 23 77 0 0 0 0 0 804352 13584 62628 0 0 0 84 9222 2250 0 14 86 0 0 0 0 0 804352 13592 62620 0 0 0 24 8131 209 0 0 93 7 0 0 0 0 804320 13592 62628 0 0 0 0 8041 27 0 0 100 0 0 0 0 0 804352 13592 62628 0 0 0 0 8040 26 0 0 100 0 0 root@raspcm3:~# for x in $(pgrep spi0) $(pgrep irq/94-mcp25xxf) ; do awk '{printf "%-20s %6i\n", $2,$15}' /proc/$x/stat; done (spi0) 0 (irq/94-mcp25xxf) 767 root@raspcm3:~# cat /proc/interrupts CPU0 CPU1 CPU2 CPU3 17: 29 0 0 0 ARMCTRL-level 1 Edge 3f00b880.mailbox 27: 1 0 0 0 ARMCTRL-level 35 Edge timer 33: 1024412 0 0 0 ARMCTRL-level 41 Edge 3f980000.usb, dwc2_hsotg:usb1 34: 1 0 0 0 ARMCTRL-level 42 Edge vc4 35: 0 0 0 0 ARMCTRL-level 43 Edge 3f004000.txp 40: 1773 0 0 0 ARMCTRL-level 48 Edge DMA IRQ 42: 11 0 0 0 ARMCTRL-level 50 Edge DMA IRQ 44: 11 0 0 0 ARMCTRL-level 52 Edge DMA IRQ 45: 0 0 0 0 ARMCTRL-level 53 Edge DMA IRQ 66: 0 0 0 0 ARMCTRL-level 74 Edge vc4 crtc 69: 0 0 0 0 ARMCTRL-level 77 Edge vc4 crtc 70: 0 0 0 0 ARMCTRL-level 78 Edge vc4 crtc 77: 20 0 0 0 ARMCTRL-level 85 Edge 3f205000.i2c, 3f804000.i2c, 3f805000.i2c 78: 6417 0 0 0 ARMCTRL-level 86 Edge 3f204000.spi 80: 237 0 0 0 ARMCTRL-level 88 Edge mmc0 81: 489 0 0 0 ARMCTRL-level 89 Edge uart-pl011 89: 0 0 0 0 bcm2836-timer 0 Edge arch_timer 90: 4048 3704 2383 1892 bcm2836-timer 1 Edge arch_timer 94: 14287 0 0 0 pinctrl-bcm2835 16 Level mcp25xxfd IPI0: 0 0 0 0 CPU wakeup interrupts IPI1: 0 0 0 0 Timer broadcast interrupts IPI2: 2361 2948 7890 1616 Rescheduling interrupts IPI3: 65 617 301 166 Function call interrupts IPI4: 0 0 0 0 CPU stop interrupts IPI5: 1 0 0 0 IRQ work interrupts IPI6: 0 0 0 0 completion interrupts Err: 0 top shows 91% for the mcp25xxfd interrupt handler, 0% for spi0 So we see that spi0 is no longer getting scheduled wasting CPU cycles There are a lot less context switches and corresponding Rescheduling interrupts All of these show that this improves efficiency of the system and reduces CPU utilization. Signed-off-by:Martin Sperl <kernel@martin.sperl.org> Signed-off-by:
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Linus Walleij authored
This converts the DesignWare (dw) SPI master driver to use GPIO descriptors for chip select handling. This driver has a duplicate DT parser in addition to the one in the core, sets up the line as non-asserted and relies on the core to drive the GPIOs. It is a pretty straight-forward conversion. Cc: Talel Shenhar <talel@amazon.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Alexandre Belloni <alexandre.belloni@bootlin.com> Cc: Linuxarm <linuxarm@huawei.com> Tested-by:
Jay Fang <f.fangjian@huawei.com> Reviewed-by:
Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by:
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Linus Walleij authored
This converts the DaVinci SPI master driver to use GPIO descriptors for chip select handling. DaVinci parses the device tree a second time for the chip select GPIOs (no relying on the parsing already happening in the SPI core) and handles inversion semantics locally. We simply drop the extra parsing and set up and move the CS handling to the core and gpiolib. The fact that the driver is actively driving the GPIO in the davinci_spi_chipselect() callback is confusing since the host does not set SPI_MASTER_GPIO_SS so this should not ever get called when using GPIO CS. I put in a comment about this. This driver also supports instantiation from board files, but these are all using native chip selects so no problem with GPIO lines here. Cc: David Lechner <david@lechnology.com> Cc: Bartosz Golaszewski <bgolaszewski@baylibre.com> Cc: Linuxarm <linuxarm@huawei.com> Signed-off-by:
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Linus Walleij authored
This converts the CLPS711x SPI master driver to use GPIO descriptors for chip select handling. The CLPS711x driver was merely requesting the GPIO and setting the CS line non-asserted so this was a pretty straight-forward conversion. The setup callback goes away. Cc: Alexander Shiyan <shc_work@mail.ru> Cc: Linuxarm <linuxarm@huawei.com> Signed-off-by:
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Linus Walleij authored
This converts the Cadence SPI master driver to use GPIO descriptors for chip select handling. The Cadence driver was allocating a state container just to hold the requested GPIO line and contained lots of polarity inversion code. As this is all handled by gpiolib and a simple devm_* request in the core, and as the driver is fully device tree only, most of this code chunk goes away in favour of central handling. The setup/cleanup callbacks goes away. This driver does NOT drive the CS line by setting the value of the GPIO so it relies on the SPI core to do this, which should work just fine with the descriptors. Cc: Wei Yongjun <weiyongjun1@huawei.com> Cc: Janek Kotas <jank@cadence.com> Cc: Linuxarm <linuxarm@huawei.com> Signed-off-by:
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Linus Walleij authored
This converts the Atmel SPI master driver to use GPIO descriptors for chip select handling. The Atmel driver has duplicate code to look up and initialize CS GPIOs from the device tree, so this is removed. It further has code to retrieve a CS GPIO from .controller_data but this seems to be completely unused in the kernel (legacy codepath?) so I deleted this support. It keeps track of polarity when switching the CS, but this is not needed anymore since we moved this over to the gpiolib. The local handling of the "npcs_pin" (I guess this might mean "negative polarity chip select pin") is preserved, but I strongly suspect this can be switched over to handling by the core and using the SPI_MASTER_GPIO_SS flag on the master to assure that the additional CS handling in the driver is also done. Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Nicolas Ferre <nicolas.ferre@microchip.com> Cc: Radu Pirea <radu.pirea@microchip.com> Cc: Linuxarm <linuxarm@huawei.com> Signed-off-by:
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Linus Walleij authored
This converts the ATH79 SPI master driver to use GPIO descriptors for chip select handling. The ATH79 driver was requesting the GPIO and driving it from the bitbang .chipselect callback. Do not request it anymore as the SPI core will request it, remove the line inversion semantics for the GPIO case (handled by gpiolib) and let the SPI core deal with requesting the GPIO line from the device tree node of the controller. This driver can be instantiated from a board file (no device tree) but the board files only use native CS (no GPIO lines) so we should be fine just letting the SPI core grab the GPIO from the device. The fact that the driver is actively driving the GPIO in the ath79_spi_chipselect() callback is confusing since the host does not set SPI_MASTER_GPIO_SS so this should not ever get called when using GPIO CS. I put in a comment about this. Cc: Felix Fietkau <nbd@nbd.name> Cc: Alban Bedel <albeu@free.fr> Cc: Linuxarm <linuxarm@huawei.com> Signed-off-by:
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Linus Walleij authored
This augments the SPI core to optionally use GPIO descriptors for chip select on a per-master-driver opt-in basis. Drivers using this will rely on the SPI core to look up GPIO descriptors associated with the device, such as when using device tree or board files with GPIO descriptor tables. When getting descriptors from the device tree, this will in turn activate the code in gpiolib that was added in commit 6953c57a ("gpio: of: Handle SPI chipselect legacy bindings") which means that these descriptors are aware of the active low semantics that is the default for SPI CS GPIO lines and we can assume that all of these are "active high" and thus assign SPI_CS_HIGH to all CS lines on the DT path. The previously used gpio_set_value() would call down into gpiod_set_raw_value() and ignore the polarity inversion semantics. It seems like many drivers go to great lengths to set up the CS GPIO line as non-asserted, respecting SPI_CS_HIGH. We pull this out of the SPI drivers and into the core, and by simply requesting the line as GPIOD_OUT_LOW when retrieveing it from the device and relying on the gpiolib to handle any inversion semantics. This way a lot of code can be simplified and removed in each converted driver. The end goal after dealing with each driver in turn, is to delete the non-descriptor path (of_spi_register_master() for example) and let the core deal with only descriptors. The different SPI drivers have complex interactions with the core so we cannot simply change them all over, we need to use a stepwise, bisectable approach so that each driver can be converted and fixed in isolation. This patch has the intended side effect of adding support for ACPI GPIOs as it starts relying on gpiod_get_*() to get the GPIO handle associated with the device. Cc: Linuxarm <linuxarm@huawei.com> Acked-by:
Jonathan Cameron <jonathan.cameron@huawei.com> Tested-by:
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- 07 Jan, 2019 23 commits
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Uwe Kleine-König authored
It highly improves usability when the buffer contents are inspecable via tracing. Signed-off-by:
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by:
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Uwe Kleine-König authored
bus_num, chip_select and len are already ints, so there is no gain in casting them to int. xfer is a pointer to a struct spi_transfer. Casting that to struct spi_message * is wrong but as only the pointer value is used for the %p format specifier no harm is done. Signed-off-by:
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Cezary Gapinski authored
Add description that STM32F4 can be used in compatible property. Master Inter-Data Idleness optional property cannot be used in STM32F4. Signed-off-by:
Cezary Gapinski <cezary.gapinski@gmail.com> Signed-off-by:
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Cezary Gapinski authored
Add routines, registers & bitfield definition. Also baud rate divisor definitions for STM32F4 SPI. This version supports full-duplex, simplex TX and half-duplex TX communication with 8 or 16-bit per word. DMA capability is optionally supported for transfer longer than 16 bytes. For transfer less than 16 bytes frames can be send in discontinuous mode. Signed-off-by:
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Cezary Gapinski authored
Prepare support for STM32F4 spi variant by introducing compatible configuration data. Move STM32H7 specific stuff to compatible data structure: - registers & bit fields - routines to control driver - baud rate divisor definitions - fifo availability - split IRQ functions to parts to be called when the IRQ occurs and for threaded interrupt what helps to provide less discontinuous mode for drivers without FIFO. Signed-off-by:
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Cezary Gapinski authored
Add transfer_one_dma_start function to be more generic for other stm32 SPI family drivers. Signed-off-by:
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Cezary Gapinski authored
Split stm32_spi_transfer_one_setup function into smaller chunks to be more generic for other stm32 SPI family drivers. Signed-off-by:
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Cezary Gapinski authored
Interrupt function is used as a thread so rename it to express meaning directly by more clear function name. Signed-off-by:
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Cezary Gapinski authored
Rename STM32 SPI registers to be related to STM32H7 SPI driver and not STM32 generally. Signed-off-by:
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Cezary Gapinski authored
This driver does not support SPI LOOP mode by configuration in registers. Signed-off-by:
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Cezary Gapinski authored
Driver supports SPI mode 0 to 3 not only the mode 3. Use SPI_CPOL and SPI_CPHA indicates that these bits can be changed to obtain modes 0 - 3. Signed-off-by:
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Cezary Gapinski authored
Fix typo from STMicroelectonics to STMicroelectronics. Signed-off-by:
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Cezary Gapinski authored
When SPI driver is configured to work only with TX or RX DMA channel then dmaengine functions can dereferene NULL pointer. Running full-duplex mode when when only RX or TX DMA channel is available can cause overrun condition or incorrect writing to transmit buffer so disable this types of DMA configuration and go back to interrupt mode. Signed-off-by:
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Cezary Gapinski authored
Patch fixes sparse warning: Using plain integer as NULL pointer. Replaces second argument of function devm_clk_get from 0 to NULL. Signed-off-by:
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Cezary Gapinski authored
Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by:
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shaftarger authored
spi::mode is defined by framework for several SPI capabilities, such as polarity, phase, bit-endian, wire number. Directly use this variable for setting controller's polarity and phase causes other bit in register being set. Since SPI framework has its definition, SPI_CPOL and SPI_CPHA offset may be changed by framwork change. Instead of just mask off the relevant bits, fetch required bit in spi::mode and set to register. Signed-off-by:
shaftarger <shol@livemail.tw> Signed-off-by:
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Angelo Dureghello authored
Add some cpu families that are actually using the fsl-dspi module in the related Kconfig description. Signed-off-by:
Angelo Dureghello <angelo@sysam.it> Signed-off-by:
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Frieder Schrempf authored
The driver was ported to the SPI framework so it can be used as a generic SPI memory driver and not only for SPI NOR. Reflect this transition in the MAINTAINERS file. Signed-off-by:
Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by:
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Frieder Schrempf authored
There's a new driver using the SPI memory interface of the SPI framework at spi/spi-fsl-qspi.c, which can be used together with m25p80.c to replace the functionality of this SPI NOR driver. The new driver is already in use and this code is not compiled anymore, so let's remove it. Signed-off-by:
Han Xu <han.xu@nxp.com> Tested-by:
Boris Brezillon <bbrezillon@kernel.org> Signed-off-by:
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Frieder Schrempf authored
Adjust the documentation of the new SPI memory interface based driver to reflect the new drivers settings. The "old" driver was using the "fsl,qspi-has-second-chip" property to select one of two dual chip setups (two chips on one bus or two chips on separate buses). And it used the order in which the subnodes are defined in the dt to select the CS, the chip is connected to. Both methods are wrong and in fact the "reg" property should be used to determine which bus and CS a chip is connected to. This also enables us to use different setups than just single chip, or symmetric dual chip. So the porting of the driver from the MTD to the SPI framework actually enforces the use of the "reg" properties and makes "fsl,qspi-has-second-chip" superfluous. As all boards that have "fsl,qspi-has-second-chip" set, also have correct "reg" properties, the removal of this property shouldn't lead to any incompatibilities. The only compatibility issues I can see are with imx6sx-sdb.dts and imx6sx-sdb-reva.dts, which have their reg properties set incorrectly (see explanation here: [2]), all other boards should stay compatible. Also the "big-endian" flag was removed, as this setting is now selected by the driver, depending on which SoC is in use. [2] https://patchwork.ozlabs.org/patch/922817/#1925445Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Frieder Schrempf authored
Move the documentation of the old SPI NOR driver to the place of the new SPI memory interface based driver. Signed-off-by:
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Frieder Schrempf authored
This driver is derived from the SPI NOR driver at mtd/spi-nor/fsl-quadspi.c. It uses the new SPI memory interface of the SPI framework to issue flash memory operations to up to four connected flash chips (2 buses with 2 CS each). The controller does not support generic SPI messages. This patch also disables the build of the "old" driver and reuses its Kconfig option CONFIG_SPI_FSL_QUADSPI to replace it. Signed-off-by:
Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Tested-by:
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Linus Torvalds authored
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