- 07 Jul, 2016 40 commits
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Tom St Denis authored
To make the code more legible various numerical constants have been changed to their #define'ed MASKs. Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Alex Xie authored
Initialize the variable in a straight-forward way instead of hiding the initialization inside the loop. This can also reduce one function call. Signed-off-by:
Alex Xie <AlexBin.Xie@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Alex Xie authored
Use == instead of != in the if statement to make code easier understood Signed-off-by:
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Alex Xie authored
Add comment to describe some variables otherwise. Signed-off-by:
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Chunming Zhou authored
Re-enable bus mastering after GPU reset. We disable it at the top of these functions, so balance them by re-enabling it. Signed-off-by:
Chunming Zhou <David1.Zhou@amd.com> eviewed-by:
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Chunming Zhou authored
So we know whether or not the reset succeeded. Signed-off-by:
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Christian König authored
vm_flush() now comes directly after vm_grab_id(). Acked-by:
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Christian König authored
Just wait for any fence to become available, instead of waiting for the last entry of the LRU. Acked-by:
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Christian König authored
This fixes a fairness problem with the GPU scheduler. VM having lot of jobs could previously starve VM with less jobs. Acked-by:
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Christian König authored
Prefer to use a VMIDs which are idle on the ring we want to submit to. This also removes bubbling idle VMIDs up on the LRU, which is actually not beneficial. Acked-by:
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Christian König authored
Check if the sync object is idle depending on the ring a submission works with. Acked-by:
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Christian König authored
Stop hiding bugs, instead print a proper error when the scheduler doesn't handle all dependencies. Acked-by:
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Christian König authored
Make it two events, one for the job being scheduled and one when it is finished. Acked-by:
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Christian König authored
It's not obvious what it should do. Acked-by:
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Tom St Denis authored
Signed-off-by:
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Tom St Denis authored
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Tom St Denis authored
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Tom St Denis authored
Enable all relevant CG flags for Stoney parts. Signed-off-by:
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Tom St Denis authored
According to the bringup code ST/CZ share the RLC ENTER/EXIT logic. Tested on my ST board. Signed-off-by:
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Nicolai Hähnle authored
They allow disabling clock and power gating from the kernel command line, which hopefully helps with diagnosing problems in the field. Reviewed-by:
Nicolai Hähnle <Nicolai.Haehnle@amd.com> Signed-off-by:
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Tom St Denis authored
Add tracepoints to the MMIO read/write so we can log MMIO traffic. Signed-off-by:
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yanyang1 authored
The non-powerplay code handles this directly. Do it in cgs for powerplay. Signed-off-by:
yanyang1 <Young.Yang@amd.com> Reviewed-by: Rex Zhu Rex.Zhu@amd.com Signed-off-by:
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Alex Deucher authored
Was missing the calls to fini. Signed-off-by: -
Alex Deucher authored
Until Dave's patch to support the new hybrid gfx ACPI method goes upstream, we can fallback to the old ATPX method which seems to still work. Signed-off-by: -
Alex Deucher authored
Until Dave's patch to support the new hybrid gfx ACPI method goes upstream, we can fallback to the old ATPX method which seems to still work. Signed-off-by: -
Chunming Zhou authored
so that we could actually reset the GPU when it hangs. Signed-off-by:
Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by:
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Monk Liu authored
debugfs file added but not released after driver unloaded Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
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Tom St Denis authored
If a user tries to read a non-multiple of 4 bytes it would have read until the end of the ring potentially crashing the user task. Signed-off-by:
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Tom St Denis authored
They now emit ring data in binary which will be read/written by the userspace tool umr shortly. Signed-off-by:
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Alex Deucher authored
The ATPX power control method does this for you. Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Acked-by:
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Alex Deucher authored
The platform d3 cold is used to power down the dGPU. Reviewed-by:
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Alex Deucher authored
hybrid graphics in this case refers to systems which use the new platform d3 cold ACPI methods as opposed to ATPX for dGPU power control. Reviewed-by:
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Alex Deucher authored
The ATPX power control method does this for you. Reviewed-by:
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Alex Deucher authored
The platform d3 cold is used to power down the dGPU. Reviewed-by:
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Alex Deucher authored
hybrid graphics in this case refers to systems which use the new platform d3 cold ACPI methods as opposed to ATPX for dGPU power control. Reviewed-by:
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Alex Deucher authored
Now that we handle this correctly, there is no need to force it. Reviewed-by:
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Alex Deucher authored
On PX systems without dGPU power control, use PCI_D3hot. Reviewed-by:
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Alex Deucher authored
The runtime pm sequence is different depending on whether or not the platform supports ATPX dGPU power control. Reviewed-by:
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Alex Deucher authored
ATPX dGPU power control requires a 200ms delay between power off and on. This should fix dGPU failures on resume from power off. Reviewed-by:
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Alex Deucher authored
The presence of the power control method should be determined via the presence of the method in function 0. However, some sbioses only set the appropriate bits in function 1 so use then to override a missing power control function. Reviewed-by:
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