- 24 Sep, 2010 40 commits
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Ben Skeggs authored
Signed-off-by:Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
The rest of the connector code assumes we can kfree() the EDID pointer. This causes things to blow up with the ACPI EDID pointer we get passed. Signed-off-by: -
Ben Skeggs authored
The most important part of this change is that we now instruct PFIFO to drop all pending fetches, rather than attempting to skip a single dword and hope that things would magically sort themselves out - they usually don't, and we end up with PFIFO being completely hung. This commit also adds somewhat more useful logging when these exceptions occur. Signed-off-by: -
Ben Skeggs authored
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Francisco Jerez authored
More Apple brain damage, it fixes the modesetting failure on an eMac G4 (fdo bug 29810). Reported-by:
Zoltan Varnagy <doi@freemail.hu> Signed-off-by:
Francisco Jerez <currojerez@riseup.net> Signed-off-by:
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Francisco Jerez authored
Instead of emptying the caches to avoid a race with the PFIFO puller, go straight ahead and try to recover from it when it happens. Also, kill pfifo->cache_flush and tile->lock, we don't need them anymore. Signed-off-by:
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Francisco Jerez authored
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Francisco Jerez authored
This makes sure that RAMHT is cleared correctly on start up. Signed-off-by:
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Francisco Jerez authored
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Francisco Jerez authored
FW seems to be broken on nv18, it causes random lockups and breaks suspend/resume even with the blob. Signed-off-by:
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Francisco Jerez authored
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Francisco Jerez authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Marcin Kościelnicki authored
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Marcin Kościelnicki <koriakin@0x04.net> Signed-off-by:
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Ben Skeggs authored
This doesn't actually happen now, but there's a test case for an earlier kernel where a GPU error is signalled on one of nv50's fake channels, and the ramht lookup by the IRQ handler triggered an oops. This adds a check for RAMHT's existance on a channel before looking up an object handle. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
Will be used at a later point when we plug in an alternative VRAM memory manager for GeForce 8+ boards. Based on pscnv code to do the same. Signed-off-by:
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Francisco Jerez authored
They don't seem to do anything useful, and we really want to program CRE_LCD if we aren't lucky enough to find the right CRTC binding already set. Signed-off-by:
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Francisco Jerez authored
On some boards the residual current DAC outputs can draw when they're disconnected can be high enough to give a false load detection positive (I've only seen it in the S-video luma output of some cards, but just to be sure). The output line capacitance is limited and sampling twice should fix it reliably. Signed-off-by:
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
Hopefully this one will be better able to cope with moving tiled buffers around without getting them all scrambled as a result. Signed-off-by: -
Francisco Jerez authored
nv2x CRTC FIFOs are as large as in nv3x (4kB it seems), and the FIFO control registers have the same layout: we can make them share the same implementation. Previously we were using the nv1x code, but the calculated FIFO watermarks are usually too low for nv2x and they cause horrible scanout artifacts. They've gone unnoticed until now because we've been leaving one of the bandwidth regs uninitialized (CRE 47, which contains the most significant bits of FFLWM), so everything seemed to work fine except in some cases after a cold boot, depending on the memory bandwidth and pixel clocks used. Signed-off-by:
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