Skip to content

O
ORS Hardware
Commit 71169733 authored by Jean-Marc Ouvrard's avatar Jean-Marc Ouvrard Committed by Thomas Gambier
Browse files
Options

Gerber corection stackup file and bug capa in altium

parent ccf62b08
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 285894 additions and 322034 deletions
hardOrsTypeB/ORS_TypeB_8Layers.OutJob
View file @ 71169733
......@@ -21,7 +21,7 @@ TargetOutputMedium=Gerbers
VariantName=[No Variations]
VariantScope=0
CurrentConfigurationName=
TargetPrinter=Brother MFC-660CN
TargetPrinter=Microsoft Print to PDF
PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=0
OutputMedium1=Print Job
OutputMedium1_Type=Printer
......@@ -80,7 +80,7 @@ OutputEnabled2_OutputMedium8=0
OutputEnabled2_OutputMedium9=0
OutputDefault2=0
Configuration2_Name1=OutputConfigurationParameter1
Configuration2_Item1=AddToAllLayerClasses.Set= |AddToAllPlots.Set=SerializeLayerHash.Version~2,ClassName~TLayerToBoolean,16908301~1|CentrePlots=False|DrillDrawingSymbol=GraphicsSymbol|DrillDrawingSymbolSize=500000|EmbeddedApertures=True|FilmBorderSize=10000000|FilmXSize=200000000|FilmYSize=160000000|FlashAllFills=False|FlashPadShapes=True|G54OnApertureChange=False|GenerateDRCRulesFile=True|GenerateReliefShapes=True|GerberUnit=Metric|IncludeUnconnectedMidLayerPads=False|LayerClassesMirror.Set= |LayerClassesPlot.Set= |LeadingAndTrailingZeroesMode=SuppressLeadingZeroes|MaxApertureSize=2500000|MinusApertureTolerance=39|Mirror.Set=SerializeLayerHash.Version~2,ClassName~TLayerToBoolean|MirrorDrillDrawingPlots=False|MirrorDrillGuidePlots=False|NoRegularPolygons=True|NumberOfDecimals=3|OptimizeChangeLocationCommands=True|OriginPosition=Absolute|Panelize=False|Plot.Set=SerializeLayerHash.Version~2,ClassName~TLayerToBoolean,16973830~1,16973832~1,16973834~1,16777217~1,16777218~1,16777219~1,16777220~1,16777221~1,16777222~1,16777223~1,16842751~1,16973835~1,16973833~1,16973831~1,16908289~1,16908290~1,16908291~1,16908295~1,16908301~1|PlotPositivePlaneLayers=False|PlotUsedDrillDrawingLayerPairs=False|PlotUsedDrillGuideLayerPairs=False|PlusApertureTolerance=39|Record=GerberView|SoftwareArcs=True|Sorted=False
Configuration2_Item1=AddToAllLayerClasses.Set= |AddToAllPlots.Set=SerializeLayerHash.Version~2,ClassName~TLayerToBoolean,16908301~1|CentrePlots=False|DrillDrawingSymbol=GraphicsSymbol|DrillDrawingSymbolSize=500000|EmbeddedApertures=True|FilmBorderSize=10000000|FilmXSize=200000000|FilmYSize=160000000|FlashAllFills=False|FlashPadShapes=True|G54OnApertureChange=False|GenerateDRCRulesFile=True|GenerateReliefShapes=True|GerberUnit=Metric|IncludeUnconnectedMidLayerPads=False|LayerClassesMirror.Set= |LayerClassesPlot.Set= |LeadingAndTrailingZeroesMode=SuppressLeadingZeroes|MaxApertureSize=2500000|MinusApertureTolerance=0|Mirror.Set=SerializeLayerHash.Version~2,ClassName~TLayerToBoolean|MirrorDrillDrawingPlots=False|MirrorDrillGuidePlots=False|NoRegularPolygons=True|NumberOfDecimals=4|OptimizeChangeLocationCommands=True|OriginPosition=Absolute|Panelize=False|Plot.Set=SerializeLayerHash.Version~2,ClassName~TLayerToBoolean,16973830~1,16973832~1,16973834~1,16777217~1,16777218~1,16777219~1,16777220~1,16777221~1,16777222~1,16777223~1,16842751~1,16973835~1,16973833~1,16973831~1,16908289~1,16908290~1,16908291~1,16908295~1,16908301~1|PlotPositivePlaneLayers=False|PlotUsedDrillDrawingLayerPairs=False|PlotUsedDrillGuideLayerPairs=False|PlusApertureTolerance=0|Record=GerberView|SoftwareArcs=False|Sorted=False
OutputType3=ODB
OutputName3=ODB++ Files
OutputCategory3=Fabrication
......
hardOrsTypeB/OrsTypeB.PrjPcb
View file @ 71169733
......@@ -28,7 +28,7 @@ PowerPortNamesTakePriority=0
PushECOToAnnotationFile=1
DItemRevisionGUID=
ReportSuppressedErrorsInMessages=0
OutputPath=Project Outputs for OrsTypeB
OutputPath=
LogFolderPath=
ManagedProjectGUID=
......@@ -1086,7 +1086,7 @@ GlobalBookmarks=0
PrintQuality=-3
[Generic_EDE]
OutputDir=Project Outputs for OrsTypeB
OutputDir=
[OutputGroup1]
Name=Netlist Outputs
......@@ -1123,101 +1123,6 @@ OutputName6=VHDL File
OutputDocumentPath6=
OutputVariantName6=
OutputDefault6=0
OutputType7=CadnetixNetlist
OutputName7=Cadnetix Netlist
OutputDocumentPath7=
OutputVariantName7=
OutputDefault7=0
OutputType8=CalayNetlist
OutputName8=Calay Netlist
OutputDocumentPath8=
OutputVariantName8=
OutputDefault8=0
OutputType9=EDIF
OutputName9=EDIF for PCB
OutputDocumentPath9=
OutputVariantName9=
OutputDefault9=0
OutputType10=EESofNetlist
OutputName10=EESof Netlist
OutputDocumentPath10=
OutputVariantName10=
OutputDefault10=0
OutputType11=IntergraphNetlist
OutputName11=Intergraph Netlist
OutputDocumentPath11=
OutputVariantName11=
OutputDefault11=0
OutputType12=MentorBoardStationNetlist
OutputName12=Mentor BoardStation Netlist
OutputDocumentPath12=
OutputVariantName12=
OutputDefault12=0
OutputType13=MultiWire
OutputName13=MultiWire
OutputDocumentPath13=
OutputVariantName13=
OutputDefault13=0
OutputType14=OrCadPCB2Netlist
OutputName14=Orcad/PCB2 Netlist
OutputDocumentPath14=
OutputVariantName14=
OutputDefault14=0
OutputType15=PADSNetlist
OutputName15=PADS ASCII Netlist
OutputDocumentPath15=
OutputVariantName15=
OutputDefault15=0
OutputType16=Pcad
OutputName16=Pcad for PCB
OutputDocumentPath16=
OutputVariantName16=
OutputDefault16=0
OutputType17=PCADnltNetlist
OutputName17=PCADnlt Netlist
OutputDocumentPath17=
OutputVariantName17=
OutputDefault17=0
OutputType18=Protel2Netlist
OutputName18=Protel2 Netlist
OutputDocumentPath18=
OutputVariantName18=
OutputDefault18=0
OutputType19=ProtelNetlist
OutputName19=Protel
OutputDocumentPath19=
OutputVariantName19=
OutputDefault19=0
OutputType20=RacalNetlist
OutputName20=Racal Netlist
OutputDocumentPath20=
OutputVariantName20=
OutputDefault20=0
OutputType21=RINFNetlist
OutputName21=RINF Netlist
OutputDocumentPath21=
OutputVariantName21=
OutputDefault21=0
OutputType22=SciCardsNetlist
OutputName22=SciCards Netlist
OutputDocumentPath22=
OutputVariantName22=
OutputDefault22=0
OutputType23=TangoNetlist
OutputName23=Tango Netlist
OutputDocumentPath23=
OutputVariantName23=
OutputDefault23=0
OutputType24=TelesisNetlist
OutputName24=Telesis Netlist
OutputDocumentPath24=
OutputVariantName24=
OutputDefault24=0
OutputType25=WireListNetlist
OutputName25=WireList Netlist
OutputDocumentPath25=
OutputVariantName25=
OutputDefault25=0
[OutputGroup2]
Name=Simulator Outputs
......
hardOrsTypeB/Project Outputs for OrsTypeB/Design Rule Check - OrsTypeB.drc
View file @ 71169733
Protel Design System Design Rule Check
PCB File : V:\Work\Projets\RapidSpaceLocal\ors-hardware\hardOrsTypeB\OrsTypeB.PcbDoc
Date : 18/04/2023
Time : 17:21:03
Date : 25/04/2023
Time : 20:53:04
Processing Rule : Clearance Constraint (Gap=0.15mm) (InNetClass('DiffPairNetClass100Ohms_1_2')),(InPolygon)
Processing Rule : Clearance Constraint (Gap=0.5mm) (InNetClass('50OhmsL8tol4')),(InPolygon)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.15mm) (InNetClass('50OhmsL8toL5')),(InPolygon)
Processing Rule : Clearance Constraint (Gap=0.21mm) (InPolygon),(All)
Rule Violations :0
Processing Rule : Matched Net Lengths(Tolerance=0.3mm) (InNetClass('POENetClass1'))
Processing Rule : Clearance Constraint (Gap=0.2mm) (InNamedPolygon('TOP-GND') OR InNamedPolygon('GND-BOTTOM_PWR1')),(All)
Rule Violations :0
Processing Rule : Matched Net Lengths(Tolerance=0.5mm) (InNetClass('POENetClass2'))
Processing Rule : Clearance Constraint (Gap=0.12mm) (All),(IsVia)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.1mm) (All),(All)
Processing Rule : Clearance Constraint (Gap=0.2mm) (InNamedPolygon('L4-+12V-2')OR InNamedPolygon('L4-+12V')OR InNamedPolygon('BOTTOM+12V')OR InNamedPolygon('BOTTOM+12V-1')OR InNamedPolygon('L6_NoNet2') OR InNamedPolygon('L6_NoNet')),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.2mm) (InNetClass('50OhmsL1toL2')),(InPolygon)
Processing Rule : Clearance Constraint (Gap=0.35mm) (InNetClass('HighIsolation')),(All)
Rule Violations :0
Processing Rule : Net Antennae (Tolerance=0mm) (Disabled)(All)
Processing Rule : Clearance Constraint (Gap=0.5mm) (InNamedPolygon('L5_NoNet') OR InNamedPolygon('L6_NoNet') OR InNamedPolygon('L4_NoNet') OR InNamedPolygon('L7_NoNet')OR InNamedPolygon('L3_NoNet')),(All)
Rule Violations :0
Processing Rule : Silk to Silk (Clearance=0.2mm) (Disabled)(All),(All)
Processing Rule : Clearance Constraint (Gap=0.1mm) (InNetClass('DiffPairNetClass')),(All)
Rule Violations :0
Processing Rule : Silk To Solder Mask (Clearance=0.2mm) (Disabled)(IsPad),(All)
Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0
Processing Rule : Minimum Solder Mask Sliver (Gap=0.05mm) (All),(All)
Processing Rule : Un-Routed Net Constraint ( (All) )
Rule Violations :0
Processing Rule : Hole To Hole Clearance (Gap=0.25mm) (All),(All)
Processing Rule : Power Plane Connect Rule(Direct Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
Rule Violations :0
Processing Rule : Hole Size Constraint (Min=0.02mm) (Max=3.5mm) (All)
Processing Rule : Width Constraint (Min=0.1mm) (Max=10mm) (Preferred=0.254mm) (All)
Rule Violations :0
Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
Rule Violations :0
Processing Rule : Width Constraint (Min=0.1mm) (Max=10mm) (Preferred=0.254mm) (All)
Processing Rule : Hole Size Constraint (Min=0.02mm) (Max=3.5mm) (All)
Rule Violations :0
Processing Rule : Power Plane Connect Rule(Direct Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
Processing Rule : Hole To Hole Clearance (Gap=0.25mm) (All),(All)
Rule Violations :0
Processing Rule : Un-Routed Net Constraint ( (All) )
Processing Rule : Minimum Solder Mask Sliver (Gap=0.05mm) (All),(All)
Rule Violations :0
Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Processing Rule : Silk To Solder Mask (Clearance=0.2mm) (Disabled)(IsPad),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.1mm) (InNetClass('DiffPairNetClass')),(All)
Processing Rule : Silk to Silk (Clearance=0.2mm) (Disabled)(All),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.5mm) (InNamedPolygon('L5_NoNet') OR InNamedPolygon('L6_NoNet') OR InNamedPolygon('L4_NoNet') OR InNamedPolygon('L7_NoNet')OR InNamedPolygon('L3_NoNet')),(All)
Processing Rule : Net Antennae (Tolerance=0mm) (Disabled)(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.35mm) (InNetClass('HighIsolation')),(All)
Processing Rule : Clearance Constraint (Gap=0.2mm) (InNetClass('50OhmsL1toL2')),(InPolygon)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.2mm) (InNamedPolygon('L4-+12V-2')OR InNamedPolygon('L4-+12V')OR InNamedPolygon('BOTTOM+12V')OR InNamedPolygon('BOTTOM+12V-1')OR InNamedPolygon('L6_NoNet2') OR InNamedPolygon('L6_NoNet')),(All)
Processing Rule : Clearance Constraint (Gap=0.1mm) (All),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.12mm) (All),(IsVia)
Processing Rule : Matched Net Lengths(Tolerance=0.5mm) (InNetClass('POENetClass2'))
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.2mm) (InNamedPolygon('TOP-GND') OR InNamedPolygon('GND-BOTTOM_PWR1')),(All)
Processing Rule : Matched Net Lengths(Tolerance=0.3mm) (InNetClass('POENetClass1'))
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.21mm) (InPolygon),(All)
Processing Rule : Clearance Constraint (Gap=0.15mm) (InNetClass('50OhmsL8toL5')),(InPolygon)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.5mm) (InNetClass('50OhmsL8tol4')),(InPolygon)
Processing Rule : Clearance Constraint (Gap=0.15mm) (InNetClass('DiffPairNetClass100Ohms_1_2')),(InPolygon)
Rule Violations :0
Violations Detected : 0
Time Elapsed : 00:02:07
\ No newline at end of file
Time Elapsed : 00:02:00
\ No newline at end of file
hardOrsTypeB/Project Outputs for OrsTypeB/Gerber/Gerber Files-macro.APR_LIB
View file @ 71169733
This source diff could not be displayed because it is too large. You can view the blob instead.
hardOrsTypeB/Project Outputs for OrsTypeB/Gerber/Gerber Files.EXTREP
View file @ 71169733
------------------------------------------------------------------------------------------
Gerber File Extension Report For: Gerber Files.GBR 18/04/2023 17:26:15
Gerber File Extension Report For: Gerber Files.GBR 25/04/2023 20:55:57
------------------------------------------------------------------------------------------
......
hardOrsTypeB/Project Outputs for OrsTypeB/Gerber/Gerber Files.GM13
View file @ 71169733
This source diff could not be displayed because it is too large. You can view the blob instead.
hardOrsTypeB/Project Outputs for OrsTypeB/Gerber/Gerber Files.GTO
View file @ 71169733
This source diff could not be displayed because it is too large. You can view the blob instead.
hardOrsTypeB/Project Outputs for OrsTypeB/Gerber/Gerber Files.RUL
View file @ 71169733
DRC Rules Export File for PCB: V:\Work\Projets\RapidSpaceLocal\ors-hardware\hardOrsTypeB\OrsTypeB.PcbDoc
RuleKind=Clearance|RuleName=100OhmsL8toL1_2|Scope=Board|Minimum=5.91
RuleKind=Clearance|RuleName=50OhmsL8toL5|Scope=Board|Minimum=5.91
RuleKind=Clearance|RuleName=Clearance|Scope=Board|Minimum=3.94
RuleKind=Clearance|RuleName=50OhmsL1toL2|Scope=Board|Minimum=7.87
RuleKind=SolderMaskExpansion|RuleName=SolderMaskExpansion|Scope=Board|Minimum=1.97
RuleKind=Width|RuleName=Width|Scope=Board|Minimum=3.94
RuleKind=ShortCircuit|RuleName=ShortCircuit|Scope=Board|Allowed=0
RuleKind=Clearance|RuleName=DiffPairNetClass|Scope=Board|Minimum=3.94
RuleKind=Clearance|RuleName=PolyGon PourClearance_NoNet|Scope=Board|Minimum=19.69
RuleKind=Clearance|RuleName=HighIsolation|Scope=Board|Minimum=13.78
RuleKind=Clearance|RuleName=PolyGon Pour Clearance_12V|Scope=Board|Minimum=7.87
RuleKind=Clearance|RuleName=Clearance-Via_1|Scope=Board|Minimum=4.72
RuleKind=Clearance|RuleName=PolyGon Clearance_GND|Scope=Board|Minimum=7.87
RuleKind=Clearance|RuleName=PolyGon Clearance_ALL|Scope=Board|Minimum=8.27
RuleKind=Clearance|RuleName=50OhmsL8toL4_1|Scope=Board|Minimum=19.69
RuleKind=Clearance|RuleName=PolyGon Clearance_ALL|Scope=Board|Minimum=8.27
RuleKind=Clearance|RuleName=PolyGon Clearance_GND|Scope=Board|Minimum=7.87
RuleKind=Clearance|RuleName=Clearance-Via_1|Scope=Board|Minimum=4.72
RuleKind=Clearance|RuleName=PolyGon Pour Clearance_12V|Scope=Board|Minimum=7.87
RuleKind=Clearance|RuleName=HighIsolation|Scope=Board|Minimum=13.78
RuleKind=Clearance|RuleName=PolyGon PourClearance_NoNet|Scope=Board|Minimum=19.69
RuleKind=Clearance|RuleName=DiffPairNetClass|Scope=Board|Minimum=3.94
RuleKind=ShortCircuit|RuleName=ShortCircuit|Scope=Board|Allowed=0
RuleKind=Width|RuleName=Width|Scope=Board|Minimum=3.94
RuleKind=SolderMaskExpansion|RuleName=SolderMaskExpansion|Scope=Board|Minimum=1.97
RuleKind=Clearance|RuleName=50OhmsL1toL2|Scope=Board|Minimum=7.87
RuleKind=Clearance|RuleName=Clearance|Scope=Board|Minimum=3.94
RuleKind=Clearance|RuleName=50OhmsL8toL5|Scope=Board|Minimum=5.91
RuleKind=Clearance|RuleName=100OhmsL8toL1_2|Scope=Board|Minimum=5.91
hardOrsTypeB/Project Outputs for OrsTypeB/NC Drill/NC Drill Files.DRR
View file @ 71169733
---------------------------------------------------------------------------
NCDrill File Report For: OrsTypeB.PcbDoc 18/04/2023 17:26:28
NCDrill File Report For: OrsTypeB.PcbDoc 25/04/2023 20:56:07
---------------------------------------------------------------------------
Layer Pair : TOP to BOTTOM
......@@ -8,14 +8,14 @@ ASCII Non-Plated RoundHoles File : NC Drill Files-NonPlated.TXT
Tool Hole Size Hole Type Hole Count Plated Tool Travel
---------------------------------------------------------------------------
T1 0.2mm (7.874mil) Round 2500 4616.68 mm (181.76 Inch)
T2 0.25mm (9.842mil) Round 1811 4649.14 mm (183.04 Inch)
T3 0.3mm (11.811mil) Round 223 984.41 mm (38.76 Inch)
T4 0.5mm (19.685mil) Round 34 306.23 mm (12.06 Inch)
T1 0.2mm (7.874mil) Round 2500 4628.21 mm (182.21 Inch)
T2 0.25mm (9.842mil) Round 1811 4521.41 mm (178.01 Inch)
T3 0.3mm (11.811mil) Round 223 918.74 mm (36.17 Inch)
T4 0.5mm (19.685mil) Round 34 313.99 mm (12.36 Inch)
T5 2.6mm (102.362mil) Round 17 650.39 mm (25.61 Inch)
T6 3.25mm (127.953mil) Round 4 35.10 mm (1.38 Inch)
T7 1mm (39.37mil) Round 8 NPTH 301.02 mm (11.85 Inch)
---------------------------------------------------------------------------
Totals 4597 11542.97 mm (454.45 Inch)
Totals 4597 11368.86 mm (447.59 Inch)
Total Processing Time (hh:mm:ss) : 00:00:02
hardOrsTypeB/Project Outputs for OrsTypeB/Pick Place/Pick Place for OrsTypeB(TDDN77_3800-4000).txt
View file @ 71169733
Designator Footprint Mid X Mid Y Ref X Ref Y Pad X Pad Y TB Rotation Comment
C247 0402 -103.8014mm 79.3101mm -103.8014mm 79.3101mm -104.1549mm 79.6636mm T 315.00 CAP_SM1nF
C243 0402 -86.01mm 79.12mm -86.01mm 79.12mm -85.6565mm 79.4736mm T 225.00 CAP_SM1nF
C259 0402 -104.4057mm 76.3599mm -104.4057mm 76.3599mm -104.7593mm 76.0063mm T 45.00 CAP_SM0.4pF
C258 0402 -107.123mm 82.5535mm -107.123mm 82.5535mm -107.606mm 82.4241mm T 15.00 CAP_SM0.2pF
......@@ -324,7 +325,7 @@ R98 0402 -112.5mm 118mm -112.5mm 118
C184 0402 -92.5mm 115.75mm -92.5mm 115.75mm -92mm 115.75mm T 180.00 CAP_SM10uF
C90 0402 -96.2mm 112.8mm -96.2mm 112.8mm -96.2mm 113.3mm T 270.00 CAP_SM100nF
C97 0402 -101.9mm 116.9mm -101.9mm 116.9mm -101.9mm 117.4mm T 270.00 CAP_SM100nF
Q6 PP1212D-8_1 -74.8075mm 147.5mm -74.75mm 147.5mm -73.315mm 146.525mm T 90.00 MOSFET_SMSi7232DN
Q6 PP1212D-8_1 -74.8075mm 147.5mm -74.75mm 147.5mm -73.315mm 146.525mm T 90.00 MOSFET_SMDual NMOSFET
C253 0402 -82.4536mm 77.2036mm -82.4536mm 77.2036mm -82.1mm 76.85mm T 135.00 CAP_SM5.6pF
C263 0402 -89mm 80.45mm -89mm 80.45mm -89mm 79.95mm T 90.00 CAP_SM100pF
C265 0402 -96.4839mm 78.309mm -96.4839mm 78.309mm -96.1304mm 77.9554mm T 135.00 CAP_SM100pF
......@@ -441,7 +442,6 @@ R46 0201 -85.2mm 139.25mm -85.2mm 139.25
R45 0201 -85.2mm 136.75mm -85.2mm 136.75mm -85.5mm 136.75mm B 360.00 RES_SM-10K
R17 0201 -70.3mm 88.85mm -70.3mm 88.85mm -70.6mm 88.85mm T 360.00 RES_SM-50
C86 0201 -71.8mm 88.85mm -71.8mm 88.85mm -71.5mm 88.85mm T 180.00 CAP_SM1nF
C247 0402 -103.75mm 79.25mm -103.75mm 79.25mm -104.1451mm 79.6451mm T 315.00 CAP_SM1nF
C102 0201 -86.75mm 90.5mm -86.75mm 90.5mm -86.45mm 90.5mm T 180.00 CAP_SM18pF
C104 0201 -88.75mm 90.5mm -88.75mm 90.5mm -89.05mm 90.5mm T 360.00 CAP_SM18pF
C105 0201 -80.7mm 93.875mm -80.7mm 93.875mm -80.7mm 93.575mm T 90.00 CAP_SM18pF
......
hardOrsTypeB/Project Outputs for OrsTypeB/Pick Place/Pick Place for OrsTypeB(TDDN79_4600-5000).txt
View file @ 71169733
Designator Footprint Mid X Mid Y Ref X Ref Y Pad X Pad Y TB Rotation Comment
C247 0402 -103.8014mm 79.3101mm -103.8014mm 79.3101mm -104.1549mm 79.6636mm T 315.00 CAP_SM1nF
C243 0402 -86.01mm 79.12mm -86.01mm 79.12mm -85.6565mm 79.4736mm T 225.00 CAP_SM1nF
C259 0402 -104.4057mm 76.3599mm -104.4057mm 76.3599mm -104.7593mm 76.0063mm T 45.00 CAP_SM0.4pF
C258 0402 -107.123mm 82.5535mm -107.123mm 82.5535mm -107.606mm 82.4241mm T 15.00 CAP_SM0.2pF
......@@ -324,7 +325,7 @@ R98 0402 -112.5mm 118mm -112.5mm 118
C184 0402 -92.5mm 115.75mm -92.5mm 115.75mm -92mm 115.75mm T 180.00 CAP_SM10uF
C90 0402 -96.2mm 112.8mm -96.2mm 112.8mm -96.2mm 113.3mm T 270.00 CAP_SM100nF
C97 0402 -101.9mm 116.9mm -101.9mm 116.9mm -101.9mm 117.4mm T 270.00 CAP_SM100nF
Q6 PP1212D-8_1 -74.8075mm 147.5mm -74.75mm 147.5mm -73.315mm 146.525mm T 90.00 MOSFET_SMSi7232DN
Q6 PP1212D-8_1 -74.8075mm 147.5mm -74.75mm 147.5mm -73.315mm 146.525mm T 90.00 MOSFET_SMDual NMOSFET
C253 0402 -82.4536mm 77.2036mm -82.4536mm 77.2036mm -82.1mm 76.85mm T 135.00 CAP_SM5.6pF
C263 0402 -89mm 80.45mm -89mm 80.45mm -89mm 79.95mm T 90.00 CAP_SM100pF
C265 0402 -96.4839mm 78.309mm -96.4839mm 78.309mm -96.1304mm 77.9554mm T 135.00 CAP_SM100pF
......@@ -441,7 +442,6 @@ R46 0201 -85.2mm 139.25mm -85.2mm 139.25
R45 0201 -85.2mm 136.75mm -85.2mm 136.75mm -85.5mm 136.75mm B 360.00 RES_SM-10K
R17 0201 -70.3mm 88.85mm -70.3mm 88.85mm -70.6mm 88.85mm T 360.00 RES_SM-50
C86 0201 -71.8mm 88.85mm -71.8mm 88.85mm -71.5mm 88.85mm T 180.00 CAP_SM1nF
C247 0402 -103.75mm 79.25mm -103.75mm 79.25mm -104.1451mm 79.6451mm T 315.00 CAP_SM1nF
C102 0201 -86.75mm 90.5mm -86.75mm 90.5mm -86.45mm 90.5mm T 180.00 CAP_SM18pF
C104 0201 -88.75mm 90.5mm -88.75mm 90.5mm -89.05mm 90.5mm T 360.00 CAP_SM18pF
C105 0201 -80.7mm 93.875mm -80.7mm 93.875mm -80.7mm 93.575mm T 90.00 CAP_SM18pF
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7