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ORS Hardware
Commit fe3a9293 authored by Jean-Marc Ouvrard's avatar Jean-Marc Ouvrard Committed by Thomas Gambier
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Add new project "OrsTypeB" that will be used for higher frequencies

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README.md
View file @ fe3a9293
......@@ -29,20 +29,17 @@ In order to do a full functional product, you will need all those components:
## Files
* `hardOrs`: Altium sources files and project files for main radio PCB
* `Project Outputs for Ors`: directory containing all the output of Altium
* `Assembly`: the PDF showing the places of the components (top and bottom)
* `BOM`: the BOM (in ODS format) for each version of the board
* `Gerber`: Gerber files for all the layers
* `MecaSoleBottomCase`: SolidWorks files for the sole case (the aluminium case is adjusted to the PCB)
* `NC Drill`: text file for drilling
* `Pick Place`: text files for pick and place
* `Schematic Print`: PDF version of the schematic
* `Exported_Ors.Net`: netlist file
* `MiniPCIexpressCard`: Altium sources files and project files for miniPCIe adaptator PCB
* `Project Outputs for MiniPciExpressCard`: directory containing all the output of Altium (same organisation as above)
* `splitter30dB`: Altium sources files and project files for 30dB directional splitter/coupler PCB
* `Project Outputs for splitter30dB`: directory containing all the output of Altium (same organisation as above)
* `hardOrs`: *ALTIUM PROJECT*, main radio PCB supporting following bands:
* B28
* 2580 MHz - 2620 MHz, B38
* 1880 MHz - 1920 MHz, B39
* 3400 MHz - 3600 MHz, B42
* 3600 MHz - 3800 MHz, B43
* `hardOrsTypeB`: *ALTIUM PROJECT*, main radio PCB supporting following bands:
* 3800 MHz - 4000 MHz, part of N77
* 4600 MHz - 5000 MHz, part of N79
* `MiniPCIexpressCard`: *ALTIUM PROJECT*, miniPCIe adaptator PCB
* `splitter30dB`: *ALTIUM PROJECT*, 30dB directional splitter/coupler PCB
* `AltiumLib`: Lib files and important files for Altium
* `*.PcbLib`: contains footprint for components
* `*.SchLib`: contains schematic for components
......@@ -50,6 +47,21 @@ In order to do a full functional product, you will need all those components:
* `Stack8Layers.ods`: description of the PCB stack with impedance information
* `tools`: directory containing useful tools
Please note that all directories containing an *ALTIUM PROJECT* is organised like this:
* TOP directory:
* `*.schlib`, `*.PcbDoc`, `*.PrjPcb*`, `*.OutJob`: Altium source files
* `Exported*.Net`: exported netlist (not mandatory)
* `Project Outputs for*`:directory containing all the output of Altium
* `Assembly`: the PDF showing the places of the components (top and bottom)
* `BOM`: the BOM (in ODS format) for each variation of the board
* `Gerber`: Gerber files for all the layers
* `MecaSoleBottomCase`: SolidWorks files for the sole case (the aluminium case is adjusted to the PCB)
* `NC Drill`: text file for drilling
* `Pick Place`: text files for pick and place
* `Schematic Print`: the PDF of the schematic for each variation of the board
## FAQ
* *Why do you use Altium (proprietary software) for Open Hardware project?*
......
hardOrsTypeB/Exported OrsTypeB.Net 0 → 100644
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hardOrsTypeB/ORS_TypeB_8Layers.OutJob 0 → 100644
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hardOrsTypeB/OrsTypeB.PrjPcb 0 → 100644
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This source diff could not be displayed because it is too large. You can view the blob instead.
hardOrsTypeB/OrsTypeB.PrjPcbStructure 0 → 100644
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Record=TopLevelDocument|FileName=OrsTypeB_Top.SchDoc
Record=SheetSymbol|Record=SheetSymbol|SourceDocument=OrsTypeB_Pwr_0.SchDoc|Designator= |SchDesignator= |FileName=OrsTypeB_Pwr_2.SchDoc|SymbolType=Normal|RawFileName=OrsTypeB_Pwr_2.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|Record=SheetSymbol|SourceDocument=OrsTypeB_Pwr_0.SchDoc|Designator= |SchDesignator= |FileName=OrsTypeB_Pwr_1.SchDoc|SymbolType=Normal|RawFileName=OrsTypeB_Pwr_1.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|Record=SheetSymbol|SourceDocument=OrsTypeB_Pwr_0.SchDoc|Designator=b|SchDesignator=b|FileName=OrsTypeB_Pwr_1.SchDoc|SymbolType=Normal|RawFileName=OrsTypeB_Pwr_1.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|Record=SheetSymbol|SourceDocument=OrsTypeB_Pwr_0.SchDoc|Designator=b2|SchDesignator=b2|FileName=OrsTypeB_Pwr_2.SchDoc|SymbolType=Normal|RawFileName=OrsTypeB_Pwr_2.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|Record=SheetSymbol|SourceDocument=OrsTypeB_Top.SchDoc|Designator= |SchDesignator= |FileName=OrsTypeB_Supply_0.SchDoc|SymbolType=Normal|RawFileName=OrsTypeB_Supply_0.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|Record=SheetSymbol|SourceDocument=OrsTypeB_Top.SchDoc|Designator= |SchDesignator= |FileName=OrsTypeB_Prog.SchDoc|SymbolType=Normal|RawFileName=OrsTypeB_Prog.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|Record=SheetSymbol|SourceDocument=OrsTypeB_Top.SchDoc|Designator=root|SchDesignator=root|FileName=OrsTypeB_0.SchDoc; OrsTypeB_1.SchDoc; OrsTypeB_2.SchDoc; OrsTypeB_3.SchDoc; OrsTypeB_4.SchDoc; OrsTypeB_5.SchDoc; OrsTypeB_6.SchDoc; OrsTypeB_7.SchDoc; OrsTypeB_8.SchDoc; OrsTypeB_9.SchDoc;|SymbolType=Normal|RawFileName=OrsTypeB_0.SchDoc; OrsTypeB_1.SchDoc; OrsTypeB_2.SchDoc; OrsTypeB_3.SchDoc; OrsTypeB_4.SchDoc; OrsTypeB_5.SchDoc; OrsTypeB_6.SchDoc; OrsTypeB_7.SchDoc; OrsTypeB_8.SchDoc; OrsTypeB_9.SchDoc;|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|Record=SheetSymbol|SourceDocument=OrsTypeB_Top.SchDoc|Designator=RxTxPower|SchDesignator=RxTxPower|FileName=OrsTypeB_Pwr_0.SchDoc|SymbolType=Normal|RawFileName=OrsTypeB_Pwr_0.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|Record=SheetSymbol|SourceDocument=OrsTypeB_Top.SchDoc|Designator=U_LowPwrLTE1|SchDesignator=U_LowPwrLTE1|FileName=OrsTypeB_Supply_1.SchDoc|SymbolType=Normal|RawFileName=OrsTypeB_Supply_1.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
hardOrsTypeB/Project Logs for OrsTypeB/OrsTypeB PCB ECO 17-03-2023 11-44-05.LOG 0 → 100644
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Removed Pin From Net: NetName=GND Pin=C47x-2
Removed Pin From Net: NetName=GND Pin=C47xb-2
Change Component Comment : Designator=C47x Old Comment=CAP_SM5.6pF New Comment=CAP_SM0.4pF
Change Component Comment : Designator=C47xb Old Comment=CAP_SM5.6pF New Comment=CAP_SM0.4pF
Change Component Comment : Designator=C46x Old Comment=CAP_SM10pF New Comment=CAP_SM0.2pF
Change Component Comment : Designator=C46xb Old Comment=CAP_SM10pF New Comment=CAP_SM0.2pF
Added Pin To Net: NetName=NetC44x_2 Pin=C46x-2
Added Pin To Net: NetName=NetC44xb_2 Pin=C46xb-2
Added Pin To Net: NetName=NetC45x_2 Pin=C47x-2
Added Pin To Net: NetName=GND Pin=C47xb-1
Added Pin To Net: NetName=NetC45xb_2 Pin=C47xb-2
Added Member To Class: ClassName=OrsTypeB_Pwr_1 Member=Component C44x CAP_SM10pF
Added Member To Class: ClassName=b Member=Component C46xb (C46x) CAP_SM0.2pF
Added Member To Class: ClassName=b Member=Component C47xb (C47x) CAP_SM0.4pF
Added Member To Class: ClassName=OrsTypeB_Pwr_1 Member=Component C47x CAP_SM0.4pF
hardOrsTypeB/Project Logs for OrsTypeB/OrsTypeB PCB ECO 17-03-2023 12-13-58.LOG 0 → 100644
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Change Component Comment : Designator=C257 Old Comment=CAP_SM5.6pF New Comment=CAP_SM0.2pF
Change Component Comment : Designator=C256 Old Comment=CAP_SM5.6pF New Comment=CAP_SM0.4pF
Change Component Comment : Designator=C258 Old Comment=CAP_SM5.6pF New Comment=CAP_SM0.4pF
Change Component Comment : Designator=C259 Old Comment=CAP_SM5.6pF New Comment=CAP_SM0.4pF
Added Pin To Net: NetName=GND Pin=C256-1
Added Pin To Net: NetName=NetC249_1 Pin=C256-2
Added Pin To Net: NetName=GND Pin=C257-1
Added Pin To Net: NetName=NetC253_1 Pin=C257-2
Added Pin To Net: NetName=GND Pin=C258-1
Added Pin To Net: NetName=NetC251_2 Pin=C258-2
Added Pin To Net: NetName=GND Pin=C259-1
Added Pin To Net: NetName=NetC255_1 Pin=C259-2
Added Member To Class: ClassName=root Member=Component C256 CAP_SM0.4pF
Added Member To Class: ClassName=root Member=Component C257 CAP_SM0.2pF
Added Member To Class: ClassName=root Member=Component C258 CAP_SM0.4pF
Added Member To Class: ClassName=root Member=Component C259 CAP_SM0.4pF
hardOrsTypeB/Project Logs for OrsTypeB/OrsTypeB PCB ECO 17-03-2023 15-23-41.LOG 0 → 100644
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Removed Pin From Net: NetName=NetC251_2 Pin=C258-2
Change Component Comment : Designator=C257 Old Comment=CAP_SM0.2pF New Comment=CAP_SM0.4pF
Change Component Comment : Designator=C256 Old Comment=CAP_SM0.4pF New Comment=CAP_SM0.2pF
Change Component Comment : Designator=C258 Old Comment=CAP_SM0.4pF New Comment=CAP_SM0.2pF
Added Pin To Net: NetName=NetC251_1 Pin=C258-2
hardOrsTypeB/Project Logs for OrsTypeB/OrsTypeB PCB ECO 17-03-2023 16-30-12.LOG 0 → 100644
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Change Component Description : Designator=Z1 Old Description=FilterCeramic 2.3GHz-2.4GHz New Description=Band Pass Filter
Change Component Description : Designator=Z1b Old Description=FilterCeramic 2.3GHz-2.4GHz New Description=Band Pass Filter
hardOrsTypeB/Project Outputs for OrsTypeB/BOM/macroLibreOffice.bas 0 → 100644
View file @ fe3a9293
sub FormatBomRapidSpace
rem ----------------------------------------------------------------------
rem define variables
dim document as object
dim dispatcher as object
rem ----------------------------------------------------------------------
rem get access to the document
document = ThisComponent.CurrentController.Frame
dispatcher = createUnoService("com.sun.star.frame.DispatchHelper")
rem ajuste la largeur de la colonne x au contenu des cellules en 1/10mm:
ThisComponent.Sheets(0).Columns(0).Width = 10000 rem Designator list
ThisComponent.Sheets(0).Columns(1).Width = 3700 rem FootPrint
ThisComponent.Sheets(0).Columns(2).Width = 4500 rem Manufacturer
ThisComponent.Sheets(0).Columns(3).Width = 5000 rem Type
ThisComponent.Sheets(0).Columns(4).Width = 3800 rem Value
ThisComponent.Sheets(0).Columns(5).Width = 1800 rem Qte
ThisComponent.Sheets(0).Columns(6).Width = 7000 rem Infos
rem ----------------------------------------------------------------------
dispatcher.executeDispatch(document, ".uno:SelectAll", "", 0, Array())
rem ----------------------------------------------------------------------
dim args2(2) as new com.sun.star.beans.PropertyValue
args2(0).Name = "FontHeight.Height"
args2(0).Value = 10
args2(1).Name = "FontHeight.Prop"
args2(1).Value = 100
args2(2).Name = "FontHeight.Diff"
args2(2).Value = 0
dispatcher.executeDispatch(document, ".uno:FontHeight", "", 0, args2())
rem ----------------------------------------------------------------------
dim args3(0) as new com.sun.star.beans.PropertyValue
args3(0).Name = "WrapText"
args3(0).Value = true
dispatcher.executeDispatch(document, ".uno:WrapText", "", 0, args3())
rem ---Figer les Volets----------------------------------------------------------
dim args1(0) as new com.sun.star.beans.PropertyValue
args1(0).Name = "ToPoint"
args1(0).Value = "$B$2"
dispatcher.executeDispatch(document, ".uno:GoToCell", "", 0, args1())
dispatcher.executeDispatch(document, ".uno:FreezePanes", "", 0, Array())
rem ----------------------------------------------------------------------
dim args6(0) as new com.sun.star.beans.PropertyValue
args6(0).Name = "ToPoint"
args6(0).Value = "$A$2"
dispatcher.executeDispatch(document, ".uno:GoToCell", "", 0, args6())
rem ----------------------------------------------------------------------
dim args5(0) as new com.sun.star.beans.PropertyValue
Dim oCurrentSelection As Variant
Dim oRows As Variant, oCols As Variant
args5(0).Name = "Sel"
args5(0).Value = true
dispatcher.executeDispatch(document, ".uno:GoToEndOfData", "", 0, args5())
oCurrentSelection = ThisComponent.getCurrentSelection()
oRows = oCurrentSelection.getRows()
oCols = oCurrentSelection.getColumns()
Dim oDocument As Object, oSheet As Object, oCell As Object
Dim l As Integer, pair As Integer, nbrCol As Integer,nbrRow As Integer
Dim strLayer As String, index As Integer, nbOccurences As Integer, oCell2 As Object
oDocument = ThisComponent
oSheet=oDocument.Sheets.getByName ("Feuille1" )
pair = 0
nbrCol = oCols.getCount()
nbrRow = oRows.getCount()
rem ----diplays Top or Bottom----------------------------------------
osheet = ThisComponent.CurrentController.ActiveSheet
For l = 1 To nbrRow
oCell2 = osheet.getCellByPosition(7, l)
strLayer = oCell2.getString()
oCell2.setString("")
index = InStr(strLayer, "Top")
if index > 0 then
oCell2 = osheet.getCellByPosition(7, l)
oCell2.setString("T")
endif
index = InStr(strLayer, "Bottom")
if index > 0 then
oCell2 = osheet.getCellByPosition(7, l)
oCell2.setString(oCell2.getString() +"B")
endif
Next l
For l = 1 To nbrRow
oCell = oSheet.getCellrangeByPosition(0,l,nbrCol-1,l)
if pair = 0 then
oCell.CellBackColor = RGB(245,245,245)
pair = 1
else
oCell.CellBackColor = RGB(250,240,230)
pair = 0
endif
Next l
oCell = oSheet.getCellrangeByPosition(0,0,nbrCol-1,nbrRow)
oCell.VERTJUSTIFY=com.sun.star.table.CellVertJustify.CENTER
oCell.HORIJUSTIFY=com.sun.star.table.CellHoriJustify.LEFT
rem Mise en form des enttes
oCell = oSheet.getCellrangeByPosition(0,0,nbrCol-1,0)
oCell.CharWeight = com.sun.star.awt.FontWeight.BOLD
oCell.HORIJUSTIFY=com.sun.star.table.CellHoriJustify.CENTER
rem semble faire un unselect
dispatcher.executeDispatch(document, ".uno:GoToCell", "", 0, args5())
end sub
\ No newline at end of file
hardOrsTypeB/Project Outputs for OrsTypeB/Design Rule Check - OrsTypeB.drc 0 → 100644
View file @ fe3a9293
Protel Design System Design Rule Check
PCB File : V:\Work\Projets\RapidSpaceLocal\ors-hardware\hardOrsTypeB\OrsTypeB.PcbDoc
Date : 17/03/2023
Time : 16:48:49
Processing Rule : Clearance Constraint (Gap=0.21mm) (InPolygon),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.2mm) (InNamedPolygon('TOP-GND') OR InNamedPolygon('GND-BOTTOM_PWR1')),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.12mm) (All),(IsVia)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.2mm) (InNamedPolygon('L4-+12V-2')OR InNamedPolygon('L4-+12V')OR InNamedPolygon('BOTTOM+12V')OR InNamedPolygon('BOTTOM+12V-1')OR InNamedPolygon('L6_NoNet2') OR InNamedPolygon('L6_NoNet')),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.5mm) (InNetClass('50OhmsL8tol4')),(InPolygon)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.5mm) (InNamedPolygon('L5_NoNet') OR InNamedPolygon('L6_NoNet') OR InNamedPolygon('L4_NoNet') OR InNamedPolygon('L7_NoNet')OR InNamedPolygon('L3_NoNet')),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.1mm) (InNetClass('DiffPairNetClass')),(All)
Rule Violations :0
Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0
Processing Rule : Un-Routed Net Constraint ( (All) )
Rule Violations :0
Processing Rule : Power Plane Connect Rule(Direct Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
Rule Violations :0
Processing Rule : Width Constraint (Min=0.1mm) (Max=10mm) (Preferred=0.254mm) (All)
Rule Violations :0
Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
Rule Violations :0
Processing Rule : Hole Size Constraint (Min=0.02mm) (Max=3.5mm) (All)
Rule Violations :0
Processing Rule : Hole To Hole Clearance (Gap=0.25mm) (All),(All)
Rule Violations :0
Processing Rule : Minimum Solder Mask Sliver (Gap=0.05mm) (All),(All)
Rule Violations :0
Processing Rule : Silk To Solder Mask (Clearance=0.2mm) (Disabled)(IsPad),(All)
Rule Violations :0
Processing Rule : Silk to Silk (Clearance=0.2mm) (Disabled)(All),(All)
Rule Violations :0
Processing Rule : Net Antennae (Tolerance=0mm) (Disabled)(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.6mm) (InNetClass('50OhmsL1toL2')),(InPolygon)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.1mm) (All),(All)
Rule Violations :0
Processing Rule : Matched Net Lengths(Tolerance=0.5mm) (InNetClass('POENetClass2'))
Rule Violations :0
Processing Rule : Matched Net Lengths(Tolerance=0.3mm) (InNetClass('POENetClass1'))
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.21mm) (InNetClass('50OhmsL8toL5')),(InPolygon)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.12mm) (InNetClass('DiffPairNetClass100Ohms_1_2')),(InPolygon)
Rule Violations :0
Violations Detected : 0
Time Elapsed : 00:02:12
\ No newline at end of file
hardOrsTypeB/Project Outputs for OrsTypeB/Gerber/Gerber Files.EXTREP 0 → 100644
View file @ fe3a9293
------------------------------------------------------------------------------------------
Gerber File Extension Report For: Gerber Files.GBR 17/03/2023 16:51:35
------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
Layer Extension Layer Description
------------------------------------------------------------------------------------------
.GTL TOP
.G1 L2
.G2 L3
.G3 L4
.G4 L5
.G5 L6
.G6 L7
.GBL BOTTOM
.GTO Top Overlay
.GTP Top Paste
.GTS Top Solder
.GBS Bottom Solder
.GBP Bottom Paste
.GBO Bottom Overlay
.GM1 Mechanical 1
.GM2 Mechanical 2
.GM3 Mechanical 3
.GM7 SOLE_EDGE-V4
.GM13 DIMENSION
------------------------------------------------------------------------------------------
hardOrsTypeB/Project Outputs for OrsTypeB/Gerber/Gerber Files.RUL 0 → 100644
View file @ fe3a9293
DRC Rules Export File for PCB: V:\Work\Projets\RapidSpaceLocal\ors-hardware\hardOrsTypeB\OrsTypeB.PcbDoc
RuleKind=Clearance|RuleName=PolyGon Clearance_ALL|Scope=Board|Minimum=8.27
RuleKind=Clearance|RuleName=PolyGon Clearance_GND|Scope=Board|Minimum=7.87
RuleKind=Clearance|RuleName=Clearance-Via_1|Scope=Board|Minimum=4.72
RuleKind=Clearance|RuleName=PolyGon Pour Clearance_12V|Scope=Board|Minimum=7.87
RuleKind=Clearance|RuleName=50OhmsL8toL4|Scope=Board|Minimum=19.69
RuleKind=Clearance|RuleName=PolyGon PourClearance_NoNet|Scope=Board|Minimum=19.69
RuleKind=Clearance|RuleName=DiffPairNetClass|Scope=Board|Minimum=3.94
RuleKind=ShortCircuit|RuleName=ShortCircuit|Scope=Board|Allowed=0
RuleKind=Width|RuleName=Width|Scope=Board|Minimum=3.94
RuleKind=SolderMaskExpansion|RuleName=SolderMaskExpansion|Scope=Board|Minimum=1.97
RuleKind=Clearance|RuleName=50OhmsL1toL2|Scope=Board|Minimum=23.62
RuleKind=Clearance|RuleName=Clearance|Scope=Board|Minimum=3.94
RuleKind=Clearance|RuleName=50OhmsL8toL5|Scope=Board|Minimum=8.27
RuleKind=Clearance|RuleName=100OhmsL8toL1_2|Scope=Board|Minimum=4.72
hardOrsTypeB/Project Outputs for OrsTypeB/NC Drill/NC Drill Files-NonPlated.TXT 0 → 100644
View file @ fe3a9293
M48
;Layer_Color=9474304
;FILE_FORMAT=4:3
METRIC,TZ
;TYPE=NON_PLATED
T7F00S00C1.000
%
T07
X325250Y204650
Y209350
X242150Y269900
X325255Y255805
Y251105
X325250Y243850
Y239150
X242150Y279900
M30
hardOrsTypeB/Project Outputs for OrsTypeB/NC Drill/NC Drill Files.DRR 0 → 100644
View file @ fe3a9293
---------------------------------------------------------------------------
NCDrill File Report For: OrsTypeB.PcbDoc 17/03/2023 16:51:49
---------------------------------------------------------------------------
Layer Pair : TOP to BOTTOM
ASCII Plated RoundHoles File : NC Drill Files-Plated.TXT
ASCII Non-Plated RoundHoles File : NC Drill Files-NonPlated.TXT
Tool Hole Size Hole Type Hole Count Plated Tool Travel
---------------------------------------------------------------------------
T1 0.2mm (7.874mil) Round 2497 4655.43 mm (183.28 Inch)
T2 0.25mm (9.842mil) Round 1811 4546.94 mm (179.01 Inch)
T3 0.3mm (11.811mil) Round 223 921.30 mm (36.27 Inch)
T4 0.5mm (19.685mil) Round 34 313.99 mm (12.36 Inch)
T5 2.6mm (102.362mil) Round 17 650.39 mm (25.61 Inch)
T6 3.25mm (127.953mil) Round 4 35.10 mm (1.38 Inch)
T7 1mm (39.37mil) Round 8 NPTH 301.02 mm (11.85 Inch)
---------------------------------------------------------------------------
Totals 4594 11424.18 mm (449.77 Inch)
Total Processing Time (hh:mm:ss) : 00:00:02
hardOrsTypeB/Project Outputs for OrsTypeB/NC Drill/NC Drill Files.LDP 0 → 100644
View file @ fe3a9293
Layer Pairs Export File for PCB: V:\Work\Projets\RapidSpaceLocal\ors-hardware\hardOrsTypeB\OrsTypeB.PcbDoc
LayersSetName=Top_Bot_Plated_Thru_Holes|DrillFile=nc drill files-plated.txt|LayerPairs=gtl,gbl
LayersSetName=Top_Bot_NonPlated_Thru_Holes|DrillFile=nc drill files-nonplated.txt|LayerPairs=gtl,gbl
hardOrsTypeB/Project Outputs for OrsTypeB/Status Report.Txt 0 → 100644
View file @ fe3a9293
Output: NC Drill Files
Type : NC Drill
From : PCB Document [OrsTypeB.PcbDoc]
Generated File[NC Drill Files-Plated.TXT]
Generated File[NC Drill Files-NonPlated.TXT]
Generated File[NC Drill Files.LDP]
Generated File[NC Drill Files.DRR]
Files Generated : 4
Documents Printed : 0
Finished Output Generation At 16:51:51 On 17/03/2023
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