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- 31 May, 2021 25 commits
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Rajendra Nayak authored
Document the google,senor board based on sc7280 SoC Acked-by:
Rob Herring <robh@kernel.org> Reviewed-by:
Matthias Kaehlcke <mka@chromium.org> Reviewed-by:
Douglas Anderson <dianders@chromium.org> Signed-off-by:
Rajendra Nayak <rnayak@codeaurora.org> Link: https://lore.kernel.org/r/1619674827-26650-1-git-send-email-rnayak@codeaurora.orgSigned-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org>
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Sibi Sankar authored
Add miscellaneous nodes to boot the Wireless Processor Subsystem (WPSS) on SC7280 SoCs. Signed-off-by:
Sibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/1619508824-14413-6-git-send-email-sibis@codeaurora.orgSigned-off-by:
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Sibi Sankar authored
Add WPSS remote processor client index to Inter-Processor Communication Controller (IPCC) block. Acked-by:
Stephen Boyd <swboyd@chromium.org> Signed-off-by:
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Sujit Kautkar authored
Move rmtfs memory region so that it does not overlap with system RAM (kernel data) when KAsan is enabled. This puts rmtfs right after mba_mem which is not supposed to increase beyond 0x94600000 Reviewed-by:
Sujit Kautkar <sujitka@chromium.org> Link: https://lore.kernel.org/r/20210514113430.1.Ic2d032cd80424af229bb95e2c67dd4de1a70cb0c@changeidSigned-off-by:
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Taniya Das authored
Add support for the video, gpu, display, lpass clock controller device nodes for SC7280 SoC. Signed-off-by:
Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1618020280-5470-3-git-send-email-tdas@codeaurora.org [bjorn: Dropped includes, as they are not present in v5.13-rc1] Signed-off-by:
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Taniya Das authored
Add cpufreq HW device node to scale 4-Silver/3-Gold/1-Gold+ cores on SC7280 SoCs. Reviewed-by:
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Matthias Kaehlcke authored
Add ADC and thermal monitor configuration for skin temperature, plus a thermal zone that monitors the skin temperature and uses the big cores as cooling devices. CoachZ rev1 is stuffed with an incompatible thermistor for the skin temperature, disable the thermal zone for rev1 to avoid the use of bogus temperature values. Reviewed-by:
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Douglas Anderson authored
As per Dmitry Baryshkov [1]: a) The 2nd "reg" should be 0x3c because "Offset 0x38 is USB3_DP_COM_REVISION_ID3 (not used by the current driver though)." b) The 3rd "reg" "is a serdes region and qmp_v3_dp_serdes_tbl contains registers 0x148 and 0x154." I think because the 3rd "reg" is a serdes region we should just use the same size as the 1st "reg"? [1] https://lore.kernel.org/r/ee5695bb-a603-0dd5-7a7f-695e919b1af1@linaro.orgReviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by:
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Jonathan Marek authored
Use sm8250 compatibles instead of sdm845 compatibles Reviewed-by:
Jonathan Marek <jonathan@marek.ca> Signed-off-by:
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Stephen Boyd authored
We should indicate that we're not using the HPD pin on this device, per the binding document. Otherwise if code in the future wants to enable HPD in the bridge when this property is absent we'll be enabling HPD when it isn't supposed to be used. Presumably this board isn't using hpd on the bridge. Reviewed-by:
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Serge Semin authored
In accordance with the DWC USB3 bindings the corresponding node name is suppose to comply with the Generic USB HCD DT schema, which requires the USB nodes to have the name acceptable by the regexp: "^usb(@.*)?" . Make sure the "snps,dwc3"-compatible nodes are correctly named. Signed-off-by:
Serge Semin <Sergey.Semin@baikalelectronics.ru> Acked-by:
Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by:
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Stephen Boyd authored
We should indicate that we're not using the HPD pin on this device, per the binding document. Otherwise if code in the future wants to enable HPD in the bridge when this property is absent we'll be wasting power powering hpd when we don't use it on trogdor boards. We didn't notice this before because the kernel driver blindly disables hpd, but that won't be true for much longer. Reviewed-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by:
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Petr Vorel authored
Reserve GPIO pins 85-88 as these aren't meant to be accessible from the application CPUs (causes reboot). Yet another fix similar to 91345867, 5f8d3ab1, which is needed to allow angler to boot after 3edfb7bd ("gpiolib: Show correct direction from the beginning"). Fixes: feeaf56a ("arm64: dts: msm8994 SoC and Huawei Angler (Nexus 6P) support") Signed-off-by:
Petr Vorel <petr.vorel@gmail.com> Reviewed-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210415193913.1836153-1-petr.vorel@gmail.comSigned-off-by:
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Konrad Dybcio authored
Fix the compatible to make the driver probe and tell the driver where to look for the "xo" clock to make sure everything works. Then we get a happy (eh, happier) 8996: somainline-sdcard:/home/konrad# cat /sys/kernel/debug/clk/pwrcl_pll/clk_rate 1152000000 Don't backport without "arm64: dts: qcom: msm8996: Add CPU opps", as the system fails to boot without consumers for these clocks. Signed-off-by:
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Loic Poulain authored
Add the operating points capabilities of the kryo CPUs, that can be used for frequency scaling. There are two differents operating point tables, one for the big cluster and one for the LITTLE cluster. This frequency scaling support can then be used as a passive cooling device (cpufreq cooling device). Only add nominal fmax for now, since there is no dynamic control of VDD APC (s11..) which is statically set at its nominal value. Original patch link: https://patchwork.kernel.org/project/linux-arm-msm/patch/1595253740-29466-6-git-send-email-loic.poulain@linaro.org/Signed-off-by:
Loic Poulain <loic.poulain@linaro.org> [konrad: drop the thermals part, rebase and remove spaces within <>] Signed-off-by:
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Matthias Kaehlcke authored
CoachZ rev3 uses a 100k NTC thermistor for the charger temperatures, instead of the 47k NTC that is stuffed in earlier revisions. Add .dts files for rev3. The 47k NTC currently isn't supported by the PM6150 ADC driver. Disable the charger thermal zone for rev1 and rev2 to avoid the use of bogus temperature values. This also gets rid of the explicit DT files for rev2 and handles rev2 in the rev1 .dts instead. There was some back and forth downstream involving the 'dmic_clk_en' pin, after that was sorted out the DT for rev1 and rev2 is the same. Signed-off-by:
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Matthias Kaehlcke authored
The only kernel visible change with respect to rev2 is that pompom rev3 changed the charger thermistor from a 47k to a 100k NTC to use a thermistor which is supported by the PM6150 ADC driver. Disable the charger thermal zone for pompom rev1 and rev2 to avoid the use of bogus temperature values from the unsupported thermistor. Signed-off-by:
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Matthias Kaehlcke authored
Commit f73558cc83d1 ("arm64: dts: qcom: sc7180: Disable charger thermal zone for lazor") disables the charger thermal zone for specific lazor revisions due to an unsupported thermistor type. The initial idea was to disable the thermal zone for older revisions and leave it enabled for newer ones that use a supported thermistor. Finally the thermistor won't be changed on newer revisions, hence the thermal zone should be disabled for all lazor (and limozeen) revisions. Instead of disabling it per revision do it once in the shared .dtsi for lazor. Signed-off-by: -
Roja Rani Yarubandi authored
We had introduced the QUP-CORE ICC path to put proxy votes from QUP wrapper on behalf of earlycon, if other users of QUP-CORE turn off this clock before the real console is probed, unclocked access to HW was seen from earlycon. With ICC sync state support proxy votes are no longer need as ICC will ensure that the default bootloader votes are not removed until all it's consumer are probed. We can safely remove ICC path for QUP-CORE clock from QUP wrapper device. Signed-off-by:
Roja Rani Yarubandi <rojay@codeaurora.org> Signed-off-by:
Akash Asthana <akashast@codeaurora.org> Reviewed-by:
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Vinod Koul authored
Some node unit addresses were put wrongly in the dts, resulting in below warning when run with W=1 arch/arm64/boot/dts/qcom/sm8350.dtsi:693.34-702.5: Warning (simple_bus_reg): /soc@0/thermal-sensor@c222000: simple-bus unit address format error, expected "c263000" arch/arm64/boot/dts/qcom/sm8350.dtsi:704.34-713.5: Warning (simple_bus_reg): /soc@0/thermal-sensor@c223000: simple-bus unit address format error, expected "c265000" arch/arm64/boot/dts/qcom/sm8350.dtsi:1180.32-1185.5: Warning (simple_bus_reg): /soc@0/interconnect@90e0000: simple-bus unit address format error, expected "90c0000" Fix by correcting to the correct address as given in reg node Reviewed-by:
Robert Foss <robert.foss@linaro.org> Signed-off-by:
Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210513060733.382420-1-vkoul@kernel.orgSigned-off-by:
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Vinod Koul authored
Add interconnect enums instead of numbers now that interconnect is in mainline. Reviewed-by:
Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by:
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Felipe Balbi authored
With this patch, DMA has a chance of probing and doing something useful. Reviewed-by:
Felipe Balbi <felipe.balbi@microsoft.com> Link: https://lore.kernel.org/r/20210417061951.2105530-3-balbi@kernel.orgSigned-off-by:
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Vincent Knecht authored
Enable the MStar msg2638 touchscreen. Reviewed-by:
Stephan Gerhold <stephan@gerhold.net> Signed-off-by:
Vincent Knecht <vincent.knecht@mailoo.org> Link: https://lore.kernel.org/r/20210528114345.543761-1-vincent.knecht@mailoo.orgSigned-off-by:
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Loic Poulain authored
The speedbin value blown in the efuse is used to determine is used to determine the voltage and frequency value for different IPs, including GPU, CPUs... So it's really not a gpu specific information. This patch simply renames 'gpu_speed_bin' node to 'speedbin'. Signed-off-by:
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Robert Marko authored
One of the QUSB USB PHY-s has been left enabled by default, this is probably just a mistake as other USB PHY-s are disabled by default. It makes no sense to have it enabled by default as not all board implement USB ports, so disable it. Reviewed-by:
Kathiravan T <kathirav@codeaurora.org> Signed-off-by:
Robert Marko <robimarko@gmail.com> Link: https://lore.kernel.org/r/20210526150125.1816335-1-robimarko@gmail.comSigned-off-by:
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- 26 May, 2021 15 commits
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Konrad Dybcio authored
Add BAM DMA nodes and add required properties to devices to enable DMA operations. Signed-off-by:
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Konrad Dybcio authored
As the name implies, the USB2 controller should only operate at USB2 speeds. Make sure it does just that by pinning it to USB High-Speed (USB2) mode. Signed-off-by:
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satya priya authored
Add channel nodes for the on die temperatures of PMICS pmk8350, pm8350, pmr735a and pmr735b. Signed-off-by:
satya priya <skakit@codeaurora.org> Reviewed-by:
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satya priya authored
The sc7280-idp has four PMICs, include their .dtsi files. Reviewed-by:
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satya priya authored
Add gpio ranges and correct the compatible to add "qcom,spmi-gpio" as this pmic is on spmi bus. Reviewed-by:
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satya priya authored
Add PON, RTC, VADC and ACD_TM support for PMK8350. Signed-off-by:
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satya priya authored
Add gpio ranges and correct the compatible to add "qcom,spmi-gpio" as this pmic is on spmi bus. Reviewed-by:
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satya priya authored
Add temp-alarm support for PMR735A pmic. Signed-off-by:
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satya priya authored
Add gpio ranges and correct the compatible to add "qcom,spmi-gpio" as this pmic is on spmi bus. Reviewed-by:
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satya priya authored
Add temp-alarm support for PM8350C pmic. Signed-off-by:
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satya priya authored
Add base DTS file for pm7325 along with GPIOs and temp-alarm nodes. Signed-off-by:
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satya priya authored
Add label "thermal_zones" for thermal-zones node. Signed-off-by:
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Rajeshwari Ravindra Kamble authored
Adding thermal zone and cooling maps support in SC7280. Reviewed-by:
Rajeshwari Ravindra Kamble <rkambl@codeaurora.org> Link: https://lore.kernel.org/r/1620367641-23383-4-git-send-email-rkambl@codeaurora.orgSigned-off-by:
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Rajeshwari Ravindra Kamble authored
Adding device node for TSENS controller and critical interrupt support in SC7280. Signed-off-by:
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Yassine Oudjana authored
Add hs_phy_irq and ss_phy_irq to usb3. Tested-by:
Yassine Oudjana <y.oudjana@protonmail.com> Link: https://lore.kernel.org/r/dvfyYKA9vnJdunbQ1CL-dgjXtv_1wYpRnezdc3PHoCyrgmfi5KP0Dn4MtaumQEpHIQAHL9tTdqcaCK7YJWyrdWXCrPeGd4uMh-nFeu7xQYw=@protonmail.comSigned-off-by:
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