- 08 Nov, 2019 13 commits
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Brian Masney authored
Add driver for the Qualcomm MSM8974 interconnect providers that support setting system bandwidth requirements between various network-on-chip fabrics. Signed-off-by:
Brian Masney <masneyb@onstation.org> Reviewed-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20191024103054.9770-3-masneyb@onstation.orgSigned-off-by:
Georgi Djakov <georgi.djakov@linaro.org> Link: https://lore.kernel.org/r/20191108125349.24191-3-georgi.djakov@linaro.orgSigned-off-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Brian Masney authored
Add device tree bindings for the Qualcomm MSM8974 interconnect providers that support setting system bandwidth requirements between various network-on-chip fabrics. Signed-off-by:
Rob Herring <robh@kernel.org> Reviewed-by:
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Andrew Jeffery authored
The data byte order selection registers in the APB2OPB primarily expose some internal plumbing necessary to get correct write accesses onto the OPB. OPB write cycles require "data mirroring" across the 32-bit data bus to support variable data width slaves that don't implement "byte enables". For slaves that do implement byte enables the master can signal which bytes on the data bus the slave should consider valid. The data mirroring behaviour is specified by the following table: +-----------------+----------+-----------------------------------+ | | | 32-bit Data Bus | +---------+-------+----------+---------+---------+-------+-------+ | | | | | | | | | ABus | Mn_BE | Request | Dbus | Dbus | Dbus | Dbus | | (30:31) | (0:3) | Transfer | 0:7 | 8:15 | 16:23 | 24:31 | | | | Size | byte0 | byte1 | byte2 | byte3 | +---------+-------+----------+---------+---------+-------+-------+ | 00 | 1111 | fullword | byte0 | byte1 | byte2 | byte3 | +---------+-------+----------+---------+---------+-------+-------+ | 00 | 1110 | halfword | byte0 | byte1 | byte2 | | +---------+-------+----------+---------+---------+-------+-------+ | 01 | 0111 | byte | _byte1_ | byte1 | byte2 | byte3 | +---------+-------+----------+---------+---------+-------+-------+ | 00 | 1100 | halfword | byte0 | byte1 | | | +---------+-------+----------+---------+---------+-------+-------+ | 01 | 0110 | byte | _byte1_ | byte1 | byte2 | | +---------+-------+----------+---------+---------+-------+-------+ | 10 | 0011 | halfword | _byte2_ | _byte3_ | byte2 | byte3 | +---------+-------+----------+---------+---------+-------+-------+ | 00 | 1000 | byte | byte0 | | | | +---------+-------+----------+---------+---------+-------+-------+ | 01 | 0100 | byte | _byte1_ | byte1 | | | +---------+-------+----------+---------+---------+-------+-------+ | 10 | 0010 | byte | _byte2_ | | byte2 | | +---------+-------+----------+---------+---------+-------+-------+ | 11 | 0001 | byte | _byte3_ | _byte3_ | | byte3 | +---------+-------+----------+---------+---------+-------+-------+ Mirrored data values are highlighted by underscores in the Dbus columns. The values in the ABus and Request Transfer Size columns correspond to values in the field names listed in the write data order select register descriptions. Similar configuration registers are exposed for reads which enables the secondary purpose of configuring hardware endian conversions. It appears the data bus byte order is switched around in hardware so set the registers such that we can access the correct values for all widths. The values were determined by experimentation on hardware against fixed CFAM register values to configure the read data order, then in combination with the table above and the register layout documentation in the AST2600 datasheet performing write/read cycles to configure the write data order registers. Signed-off-by:Andrew Jeffery <andrew@aj.id.au> Signed-off-by:
Joel Stanley <joel@jms.id.au> Acked-by:
Alistair Popple <alistair@popple.id.au> Link: https://lore.kernel.org/r/20191108051945.7109-12-joel@jms.id.auSigned-off-by:
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Joel Stanley authored
These trace points help with debugging the FSI master. They show the low level reads, writes and error states of the master. Signed-off-by:
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Joel Stanley authored
The ast2600 BMC has a pair of FSI masters in it, behind an AHB to OPB bridge. The master driver supports reads and writes of full words, half word and byte accesses to remote CFAMs. It can perform very basic error recovery through resetting of the FSI port when an error is detected, and the issuing of breaks and terms. Signed-off-by:
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Joel Stanley authored
This describes the FSI master present in the AST2600. Signed-off-by:
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Joel Stanley authored
The FSI master registers are common to the hub and AST2600 master (and the FSP2, if someone was to upstream a driver for that). Add defines to the fsi-master.h header, and introduce headings to delineate the existing low level details. Acked-by:
Jeremy Kerr <jk@ozlabs.org> Signed-off-by:
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kbuild test robot authored
There are no users outside of this file. Fixes: 0604d53d4da8 ("fsi: Add fsi-master class") Signed-off-by:kbuild test robot <lkp@intel.com> Signed-off-by:
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Andrew Jeffery authored
Subtracting the offset delta from four-byte alignment lead to wrapping of the requested length where `count` is less than `off`. Generalise the length handling to enable and optimise aligned access sizes for all offset and size combinations. The new formula produces the following results for given offset and count values: offset count | length --------------+------- 0 1 | 1 0 2 | 2 0 3 | 2 0 4 | 4 0 5 | 4 1 1 | 1 1 2 | 1 1 3 | 1 1 4 | 1 1 5 | 1 2 1 | 1 2 2 | 2 2 3 | 2 2 4 | 2 2 5 | 2 3 1 | 1 3 2 | 1 3 3 | 1 3 4 | 1 3 5 | 1 We might need something like this for the cfam chardevs as well, for example we don't currently implement any alignment restrictions / handling in the hardware master driver. Signed-off-by: -
Andrew Jeffery authored
Due to other bugs I observed a spurious -1 transfer size. Signed-off-by:
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Joel Stanley authored
The paths added back in 4.13 weren't quite correct. The in reality the files documented lived under /sys/devices/../fsi0/rescan /sys/devices/../fsi0/break /sys/devices/../fsi0/slave@00:00/term /sys/devices/../fsi0/slave@00:00/raw In 5.5 with the addition of the FSI class they move to /sys/devices/../fsi-master/fsi0/rescan /sys/devices/../fsi-master/fsi0/break /sys/devices/../fsi-master/fsi0/slave@00:00/term /sys/devices/../fsi-master/fsi0/slave@00:00/raw This is closer to how the (incorrect) documentation described them. Signed-off-by:
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Jeremy Kerr authored
Populate fsi_master_class->dev_attrs with the existing attribute definitions, so we don't need to explicitly register. Signed-off-by:
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Jeremy Kerr authored
This change adds a device class for FSI masters, allowing access under /sys/class/fsi-master/, and easier udev rules. Signed-off-by:
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- 07 Nov, 2019 6 commits
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Greg Kroah-Hartman authored
Merge tag 'thunderbolt-for-v5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/westeri/thunderbolt into char-misc-next Mika writes: thunderbolt: Changes for v5.5 merge window This adds Thunderbolt 3 support for the software connection manager. It is currently only used in Apple systems. Previously the driver started the firmware connection manager on those but it is not necessary anymore with these patches (we still leave user an option to start the firmware in case there are problems with the software connection manager). This includes: - Expose 'generation' attribute under each device in sysfs - Converting register names to follow the USB4 spec. - Lane bonding support - Expose link speed and width in sysfs - Display Port handshake needed for Titan Ridge devices - Display Port pairing and resource management - Display Port bandwidth management * tag 'thunderbolt-for-v5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/westeri/thunderbolt: (21 commits) thunderbolt: Do not start firmware unless asked by the user thunderbolt: Add bandwidth management for Display Port tunnels thunderbolt: Add Display Port adapter pairing and resource management thunderbolt: Add Display Port CM handshake for Titan Ridge devices thunderbolt: Add downstream PCIe port mappings for Alpine and Titan Ridge thunderbolt: Expand controller name in tb_switch_is_xy() thunderbolt: Add default linking between lane adapters if not provided by DROM thunderbolt: Add support for lane bonding thunderbolt: Refactor add_switch() into two functions thunderbolt: Add helper macro to iterate over switch ports thunderbolt: Make tb_sw_write() take const parameter thunderbolt: Convert DP adapter register names to follow the USB4 spec thunderbolt: Convert PCIe adapter register names to follow the USB4 spec thunderbolt: Convert basic adapter register names to follow the USB4 spec thunderbolt: Log error if adding switch fails thunderbolt: Log switch route string on config read/write timeout thunderbolt: Introduce tb_switch_is_icm() thunderbolt: Add 'generation' attribute for devices thunderbolt: Drop unnecessary read when writing LC command in Ice Lake thunderbolt: Fix lockdep circular locking depedency warning ...
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Alexander Usyskin authored
The glitch detection HW (TRC) save it status information into TRC status register. Make it available to user-space via read-only sysfs file. The TRC register is availab for PCH15 gen and newer, for older platforms reading the sysfs file will fail with EOPNOTSUPP. Signed-off-by:
Alexander Usyskin <alexander.usyskin@intel.com> Signed-off-by:
Tomas Winkler <tomas.winkler@intel.com> Link: https://lore.kernel.org/r/20191107104445.19101-1-tomas.winkler@intel.comSigned-off-by:
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Tomas Winkler authored
This is to allow working with mei devices embedded within another pci device, where mei device is represented as a platform child device and fw status registers are not necessarily resident in the device pci config space. Bump the copyright year to 2019 on the modified files. Signed-off-by:
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Alexander Usyskin authored
Store irq number in hw struct to by used by synchronize_irq(). This is to allow working with mei devices embedded within another pci devices, via MFD framework, where mei device is represented as a platform device. Bump the copyright year to 2019 on hw-me.c and hw-me.h Signed-off-by:
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Tomas Winkler authored
It's enough to bind mei_device with associated 'struct device' instead of actual 'struct pci_dev'. This is to allow working with mei devices embedded within another pci device, usually via MFD framework, where mei device is represented as a platform device. Bump copyright year to 2019 on effected files. Signed-off-by:
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Greg Kroah-Hartman authored
Merge tag 'phy-for-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into char-misc-next Kishon writes: phy: for 5.5 *) Add a new PHY driver for USB3 PHY on Allwinner H6 SoC *) Add a new PHY driver for Innosilicon Video Combo PHY(MIPI/LVDS/TTL) *) Add support in xusb-tegra210 PHY driver to get USB device mode functional in Tegra 210 *) Add support for SM8150 QMP UFS PHY in phy-qcom-qmp PHY driver *) Fix smatch warning (array off by one) in phy-rcar-gen2 PHY driver *) Enable mac tx internal delay for rgmii-rxid in phy-gmii-sel driver *) Fix phy-qcom-usb-hs from registering multiple extcon notifiers during PHY power cycle *) Use devm_platform_ioremap_resource() in phy-mvebu-a3700-utmi, phy-hisi-inno-usb2, phy-histb-combphy and regulator_bulk_set_supply_names() in xusb to simplify code *) Remove unused variable in xusb-tegra210 and phy-dm816x-usb *) Fix sparse warnings in phy-brcm-usb-init Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> * tag 'phy-for-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy: (28 commits) phy: phy-rockchip-inno-usb2: add phy description for px30 phy: qcom-usb-hs: Fix extcon double register after power cycle phy: renesas: phy-rcar-gen2: Fix the array off by one warning phy: lantiq: vrx200-pcie: fix error return code in ltq_vrx200_pcie_phy_power_on() dt-bindings: phy: add yaml binding for rockchip,px30-dsi-dphy phy/rockchip: Add support for Innosilicon MIPI/LVDS/TTL PHY phy: add PHY_MODE_LVDS phy: allwinner: add phy driver for USB3 PHY on Allwinner H6 SoC dt-bindings: Add bindings for USB3 phy on Allwinner H6 phy: qcom-qmp: Add SM8150 QMP UFS PHY support dt-bindings: phy-qcom-qmp: Add sm8150 UFS phy compatible string phy: ti: gmii-sel: fix mac tx internal delay for rgmii-rxid phy: tegra: use regulator_bulk_set_supply_names() phy: ti: dm816x: remove set but not used variable 'phy_data' phy: renesas: rcar-gen3-usb2: Fix sysfs interface of "role" phy: tegra: xusb: Add vbus override support on Tegra186 phy: tegra: xusb: Add vbus override support on Tegra210 phy: tegra: xusb: Add usb3 port fake support on Tegra210 phy: tegra: xusb: Add XUSB dual mode support on Tegra210 dt-bindings: rcar-gen3-phy-usb3: Add r8a774b1 support ...
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- 05 Nov, 2019 15 commits
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Finley Xiao authored
Newer Rockchip socs like the px30 use a different one-time-programmable memory controller for things like cpu-id and leakage information, so add the necessary driver for it. Signed-off-by:
Finley Xiao <finley.xiao@rock-chips.com> [ported from vendor 4.4, converted to clock-bulk API and cleanups] Signed-off-by:
Heiko Stuebner <heiko@sntech.de> Signed-off-by:
Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Link: https://lore.kernel.org/r/20191029114240.14905-11-srinivas.kandagatla@linaro.orgSigned-off-by:
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Heiko Stuebner authored
Newer Rockchip SoCs use a different IP for accessing special one- time-programmable memory, so add a binding for these controllers. Signed-off-by:
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Srinivas Kandagatla authored
Fix below error by adding HAVE_ARM_SMCCC dependency in Kconfig ERROR: "__arm_smccc_smc" [drivers/nvmem/nvmem-imx-ocotp-scu.ko] undefined! Reported-by:
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Freeman Liu authored
The Spreadtrum eFuse controller is widely used to dump chip ID, configuration setting, function select and so on, as well as supporting one-time programming. Signed-off-by:
Freeman Liu <freeman.liu@unisoc.com> Signed-off-by:
Baolin Wang <baolin.wang@linaro.org> Signed-off-by:
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Freeman Liu authored
This patch adds the binding documentation for Spreadtrum eFuse controller. Signed-off-by:
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Lucas Stach authored
If software running before the OCOTP driver is loaded left the controller with the error status pending, the driver will never be able to complete the read timing setup. Reset the error status on probe to make sure the controller is in usable state. Signed-off-by:
Lucas Stach <l.stach@pengutronix.de> Signed-off-by:
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Peng Fan authored
The fuse programming from non-secure world is blocked, so we could only use Arm Trusted Firmware SIP call to let ATF program fuse. Because there is ECC region that could only be programmed once, so add a heler in_ecc to check the ecc region. Signed-off-by:
Peng Fan <peng.fan@nxp.com> Signed-off-by:
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Peng Fan authored
Introduce HOLE/ECC_REGION flag and in_hole helper to ease the check of hole region. The ECC_REGION is also introduced here which is preparing for programming support. ECC_REGION could only be programmed once, so need take care. Signed-off-by:
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Baolin Wang authored
Change to use devm_hwspin_lock_request_specific() to help to simplify the cleanup code for drivers requesting one hwlock. Thus we can remove the redundant sc27xx_efuse_remove() and platform_set_drvdata(). Signed-off-by:
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Sebastian Reichel authored
nvmem_cell_write's buf argument uses different types based on the configuration of CONFIG_NVMEM. The function prototype for enabled NVMEM uses 'void *' type, but the static dummy function for disabled NVMEM uses 'const char *' instead. Fix the different behaviour by always expecting a 'void *' typed buf argument. Fixes: 7a78a7f7 ("power: reset: nvmem-reboot-mode: use NVMEM as reboot mode write interface") Reported-by:
Sebastian Reichel <sebastian.reichel@collabora.com> Reviewed-By:
Han Nandor <nandor.han@vaisala.com> Signed-off-by:
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YueHaibing authored
Use devm_platform_ioremap_resource() to simplify the code a bit. This is detected by coccinelle. Signed-off-by:
YueHaibing <yuehaibing@huawei.com> Acked-by:
Eli Billauer <eli.billauer@gmail.com> Link: https://lore.kernel.org/r/20191016092546.26332-1-yuehaibing@huawei.comSigned-off-by:
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Marcel Holtmann authored
udev has a feature of creating /dev/<node> device-nodes if it finds a devnode:<node> modalias. This allows for auto-loading of modules that provide the node. This requires to use a statically allocated minor number for misc character devices. However, rfkill uses dynamic minor numbers and prevents auto-loading of the module. So allocate the next static misc minor number and use it for rfkill. Signed-off-by:
Marcel Holtmann <marcel@holtmann.org> Link: https://lore.kernel.org/r/20191024174042.19851-1-marcel@holtmann.orgSigned-off-by:
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Alexander Usyskin authored
Comet Point (Comet Lake) V device id. Cc: <stable@vger.kernel.org> Signed-off-by:
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Alexander Usyskin authored
Add parent device name to the name of devices on bus to avoid device names collisions for same client UUID available from different MEI heads. Namely this prevents sysfs collision under /sys/bus/mei/device/ In the device part leave just UUID other parameters that are required for device matching are not required here and are just bloating the name. Cc: <stable@vger.kernel.org> Signed-off-by:
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Greg Kroah-Hartman authored
Merge tag 'extcon-next-for-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/extcon into char-misc-next Chanwoo writes: Update extcon for 5.5 Detailed description for this pull request: 1. Clean up the and fix the minor issue of extcon provider driver - extcon-intel-cht-wc don't reset the USB data connection at probe time in order to prevent the removing all devices from bus. - extcon-sm5502 reset the registers at proble time in order to prevent the some stuck state. And remove the redundant variable initializaiton. * tag 'extcon-next-for-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/extcon: extcon: sm5502: remove redundant assignment to variable cable_type extcon: sm5502: Reset registers during initialization extcon-intel-cht-wc: Don't reset USB data connection at probe
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- 04 Nov, 2019 6 commits
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Rikard Falkeborn authored
The second argument should be the lsb and the third argument should be the msb. Signed-off-by:
Rikard Falkeborn <rikard.falkeborn@gmail.com> Signed-off-by:
Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20191104181251.26732-15-mathieu.poirier@linaro.orgSigned-off-by:
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Yabin Cui authored
When tracing etm data of multiple threads on multiple cpus through perf interface, some link devices are shared between paths of different cpus. It creates race conditions when different cpus wants to enable/disable the same link device at the same time. Example 1: Two cpus want to enable different ports of a coresight funnel, thus calling the funnel enable operation at the same time. But the funnel enable operation isn't reentrantable. Example 2: For an enabled coresight dynamic replicator with refcnt=1, one cpu wants to disable it, while another cpu wants to enable it. Ideally we still have an enabled replicator with refcnt=1 at the end. But in reality the result is uncertain. Since coresight devices claim themselves when enabled for self-hosted usage, the race conditions above usually make the link devices not usable after many cycles. To fix the race conditions, this patch uses spinlocks to serialize enabling/disabling link devices. Fixes: a06ae860 ("coresight: add CoreSight core layer framework") Signed-off-by:
Yabin Cui <yabinc@google.com> Signed-off-by:
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Mark Brown authored
Coresight hardware is only likely to appear on Arm systems and currently the core code has Arm-specific barrier operations in it so can't be built anywhere else so add an explicit dependency saying so. This will make no practical difference currently due to the way subsystems are referenced, the subsystem is only pulled in on arm and arm64, so mainly serves as documentation in case someone wants to increase build coverage. Signed-off-by:
Mark Brown <broonie@kernel.org> Signed-off-by:
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Mike Leach authored
An API to control single-shot comparator operation was missing from sysfs. This adds the parameters to sysfs to allow programming of this feature. Signed-off-by:
Mike Leach <mike.leach@linaro.org> Signed-off-by:
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Mike Leach authored
Currently it is not possible to view the current settings of a given address comparator without knowing what type it is set to. For example, if a comparator is set as an addr_start comparator, attempting to read addr_stop for the same index will result in an error. addr_cmp_view is added to allow the user to see the current settings of the indexed address comparator without resorting to trial and error when the set type is not known. Signed-off-by:
Leo Yan <leo.yan@linaro.org> Signed-off-by:
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Mike Leach authored
Context ID and VM ID masks required 2 value inputs, even when the second value is ignored as insufficient CID / VMID comparators are implemented. Permit a single value to be used if that is sufficient to cover all implemented comparators. Signed-off-by:
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