- 15 Jun, 2023 23 commits
-
-
Vaishnav Achath authored
J721E common processor board has an onboard mux for selecting whether the OSPI signals are externally routed to OSPI flash or Hyperflash. The mux state signal input is tied to WKUP_GPIO0_8 and is used by bootloader for enabling the corresponding node accordingly. Add pinmux for the same. Signed-off-by:
Vaishnav Achath <vaishnav.a@ti.com> Link: https://lore.kernel.org/r/20230513123313.11462-5-vaishnav.a@ti.comSigned-off-by:
Vignesh Raghavendra <vigneshr@ti.com>
-
Vaishnav Achath authored
J7200 common processor board has an onboard mux for selecting whether the OSPI signals are externally routed to OSPI flash or Hyperflash. The mux state signal input is tied to WKUP_GPIO0_6 and is used by bootloader for enabling the corresponding node accordingly. Add pinmux for the same. Signed-off-by:
-
Vaishnav Achath authored
J721E SoM has a HyperFlash and HyperRam connected to HyperBus memory controller, add corresponding node, pinmux and partitions for the same. HyperBus is muxed with OSPI and only one controller can be active at a time, therefore keep HyperBus node disabled. Bootloader will detect the external mux state through a wkup gpio and enable the node as required. Signed-off-by:
-
Vaishnav Achath authored
J721E has a Flash SubSystem that has one OSPI and one HyperBus with muxed datapath and another independent OSPI. Add DT nodes for HyperBus controller and keep it disabled and model the data path selection mux as a reg-mux. Signed-off-by:
-
Andrew Davis authored
MDIO nodes defined in the top-level J721e SoC dtsi files are incomplete and will not be functional unless they are extended with a pinmux. As the attached PHY is only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the MDIO nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by:
Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20230515172137.474626-5-afd@ti.comSigned-off-by:
-
Andrew Davis authored
Mailbox nodes defined in the top-level AM64x SoC dtsi files are incomplete and may not be functional unless they are extended with a chosen interrupt and connection to a remote processor. As the remote processors depend on memory nodes which are only known at the board integration level, these nodes should only be enabled when provided with the above information. Disable the Mailbox nodes in the dtsi files and only enable the ones that are actually used on a given board. Signed-off-by:
-
Andrew Davis authored
PCIe nodes defined in the top-level J721e SoC dtsi files are incomplete and will not be functional unless they are extended with a SerDes PHY. And usually only one of the two modes can be used at a time as they share a SerDes link. As the PHY and mode is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the PCIe nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by:
-
Andrew Davis authored
These nodes are example nodes for the PCIe controller in "endpoint" mode. By default the controller is in "root complex" mode and there is already a DT node for the same. Examples should go in the bindings or other documentation. Remove this node. Signed-off-by:
-
Andrew Davis authored
Mailbox nodes are now disabled by default. The BeagleBoard AI64 DT addition went in at around the same time and must have missed that change so the mailboxes are not re-enabled. Do that here. Fixes: fae14a1c ("arm64: dts: ti: Add k3-j721e-beagleboneai64") Signed-off-by:
Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230515172137.474626-1-afd@ti.comSigned-off-by:
-
Bhavya Kapoor authored
eMMC tuning was incomplete earlier, so support for high speed modes was kept disabled. Remove no-1-8-v property to enable support for high speed modes for eMMC in J784S4 SoC. Signed-off-by:
Bhavya Kapoor <b-kapoor@ti.com> Link: https://lore.kernel.org/r/20230502090814.144791-1-b-kapoor@ti.comSigned-off-by:
-
Bhavya Kapoor authored
J784S4 has two instances of 8 channel ADCs in MCU domain. Add pinmux information for both ADC nodes. Signed-off-by:
-
Bhavya Kapoor authored
J784S4 has two instances of 8 channel ADCs in MCU domain. Add support for both ADC nodes. Signed-off-by:
-
Jyri Sarha authored
The OLDI-LCD1EVM add on board has Rocktech RK101II01D-CT panel[1] with integrated touch screen. The integrated touch screen is Goodix GT928. This panel connects with AM65 GP-EVM[2]. Add DT nodes for these and connect the endpoint nodes with DSS. [1]: Panel link https://www.digimax.it/en/tft-lcd/20881-RK101II01D-CT [2]: AM654 LCD EVM: https://www.ti.com/tool/TMDSLCD1EVMSigned-off-by:
Jyri Sarha <jsarha@ti.com> Signed-off-by:
Nikhil Devshatwar <nikhil.nd@ti.com> [abhatia1@ti.com: Make cosmetic and 6.4 kernel DTSO syntax changes] Signed-off-by:
Aradhya Bhatia <a-bhatia1@ti.com> Reviewed-by:
Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Reviewed-by:
-
Bhavya Kapoor authored
Update the delay values for various speed modes supported, based on the revised august 2021 J721E Datasheet. [1] - Table 7-77. MMC0 DLL Delay Mapping for All Timing Modes and Table 7-86. MMC1/2 DLL Delay Mapping for All Timing Modes, in https://www.ti.com/lit/ds/symlink/tda4vm.pdf, (SPRSP36J – FEBRUARY 2019 – REVISED AUGUST 2021) Signed-off-by:
-
Nishanth Menon authored
Include documentation of the AMC package pin name as well to keep it consistent with the rest of the pinctrl documentation. Signed-off-by:
-
Nishanth Menon authored
Add board EEPROM support to device tree Signed-off-by:
-
Nishanth Menon authored
wkup_uart and main_uart1 on this platform is used by tifs and DM firmwares. Describe them for completeness including the pinmux. Signed-off-by:
-
Nishanth Menon authored
Drop an extra EoL Signed-off-by:
-
Nishanth Menon authored
Looks like a couple of http:// links crept in. Use https instead. While at it, drop unicode encoded character. Signed-off-by:
-
Keerthy authored
VTM stands for Voltage Thermal Management. Add the thermal zones. Six sensors mapping to six thermal zones. Main0, Main1, Main2, Main3, WKUP1 & WKUP2 domains respectively. Signed-off-by:
Keerthy <j-keerthy@ti.com> [bb@ti.com: rebased on v6.3-rc1] Signed-off-by:
Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20230405215328.3755561-8-bb@ti.comSigned-off-by:
-
Keerthy authored
VTM stands for Voltage Thermal Management. Add the thermal zones. Three sensors mapping to 3 thermal zones. MCU, MPU & Main domains respectively. Signed-off-by:
-
Keerthy authored
VTM stands for Voltage Thermal Management. Add the thermal zones. Five sensors mapping ton 5 thermal zones. WKUP, MPU, C7x, GPU & R5F respectively. Signed-off-by:
-
Keerthy authored
VTM stands for Voltage Thermal Management. Add the thermal zones. Seven sensors mapping to seven thermal zones. Main0, Main1, Main2, Main3, Main4, WKUP1 & WKUP2 domains respectively. Signed-off-by:
-
- 14 Jun, 2023 15 commits
-
-
Bryan Brattlof authored
The am62ax supports a single Voltage and Thermal Management (VTM) device located in the wakeup domain with three associated temperature monitors located in various hot spots of the die. Signed-off-by:
-
Bryan Brattlof authored
The am62x supports a single Voltage and Thermal Management (VTM) module located in the wakeup domain with two associated temperature monitors located in hot spots of the die. Signed-off-by:
-
Bryan Brattlof authored
The am64x supports a single VTM module which is located in the main domain with two associated temperature monitors located at different hot spots on the die. Tested-by:
Christian Gmeiner <christian.gmeiner@gmail.com> Signed-off-by:
-
Aswath Govindraju authored
x1 lane PCIe slot in the common processor board is enabled and connected to J721S2 SOM. Add PCIe DT node in common processor board to reflect the same. Reviewed-by:
Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by:
Aswath Govindraju <a-govindraju@ti.com> Signed-off-by:
Matt Ranostay <mranostay@ti.com> Signed-off-by:
Ravi Gunasekaran <r-gunasekaran@ti.com> Reviewed-by:
Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230331090028.8373-9-r-gunasekaran@ti.comSigned-off-by:
-
Aswath Govindraju authored
Add PCIe1 RC device tree node for the single PCIe instance present on the J721S2. Reviewed-by:
-
Aswath Govindraju authored
J721S2 has an OSPI NOR flash on its SOM connected the OSPI0 instance and a QSPI NOR flash on the common processor board connected to the OSPI1 instance. Add support for the same Reviewed-by:
-
Aswath Govindraju authored
The board uses lane 1 of SERDES for USB. Set the mux accordingly. The USB controller and EVM supports super-speed for USB0 on the Type-C port. However, the SERDES has a limitation that up to 2 protocols can be used at a time. The SERDES is wired for PCIe, eDP and USB super-speed. It has been chosen to use PCIe and eDP as default. So restrict USB0 to high-speed mode. Signed-off-by:
-
Aswath Govindraju authored
Configure first lane to PCIe, the second lane to USB and the last two lanes to eDP. Also, add sub-nodes to SERDES0 DT node to represent SERDES0 is connected to PCIe. Signed-off-by:
-
Aswath Govindraju authored
Add support for two instance of OSPI in J721S2 SoC. Reviewed-by:
-
Matt Ranostay authored
Add dt node for the single instance of WIZ (SERDES wrapper) and SERDES module shared by PCIe, eDP and USB. Signed-off-by:
-
Aswath Govindraju authored
Add support for single instance of USB 3.0 controller in J721S2 SoC. Signed-off-by:
-
Roger Quadros authored
USB0 is a Type-C port with dual data role and power sink. Signed-off-by:
-
Hari Nagalla authored
Reserve memory for remote processors. Two memory regions are reserved for each remote processor. The first 1Mb region is used for virtio Vring buffers for IPC and the second region is used for holding resource table, trace buffer and as external memory to the remote processor. The mailboxes are also assigned for each remote processor. Signed-off-by:
Hari Nagalla <hnagalla@ti.com> Link: https://lore.kernel.org/r/20230502231527.25879-4-hnagalla@ti.comSigned-off-by:
-
Hari Nagalla authored
The J784S4 SoCs have four TMS320C71x DSP subsystems in the MAIN voltage domain. The functionality of these DSP subsystems is similar to the C71x DSP subsystems on earlier k3 device J721S2. Each subsystem has a 48 KB of L1D configurable SRAM/Cache and 512 KB of L2 SRAM/Cache. This subsystem has a CMMU but is not currently used. The inter-processor communication between the main A72 cores and the C71x DSPs is achieved through shared memory and mailboxes. Add the DT nodes for these DSP processor sub-systems. Signed-off-by:
-
Hari Nagalla authored
The J784S4 SoCs have 4 dual-core Arm Cortex-R5F processor (R5FSS) subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within the MCU domain, and the remaining three clusters are present in the MAIN domain (MAIN_R5FSS0, MAIN_R5FSS1 & MAIN_R5FSS2). The functionality of the R5FSS is same as the R5FSS functionality on earlier K3 platform device J721S2. Each of the R5FSS can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. These subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal memories for each core split between two banks - ATCM and BTCM (further interleaved into two banks). There are some IP integration differences from standard Arm R5 clusters such as the absence of an ACP port, presence of an additional TI-specific Region Address Translater (RAT) module for translating 32-bit CPU addresses into larger system bus addresses etc. Add the DT nodes for the R5F cluster/subsystems, the two R5F cores are each added as child nodes to the corresponding cluster node. The clusters are configured to run in LockStep mode by default, with the ATCMs enabled to allow the R5 cores to execute code from DDR with boot-strapping code from ATCM. The inter-processor communication between the main A72 cores and these processors is achieved through shared memory and Mailboxes. The following firmware names are used by default for these cores, and can be overridden in a board dts file if needed: MAIN R5FSS0 Core0: j784s4-main-r5f0_0-fw (both in LockStep and Split modes) MAIN R5FSS0 Core1: j784s4-main-r5f0_1-fw (needed only in Split mode) MAIN R5FSS1 Core0: j784s4-main-r5f1_0-fw (both in LockStep and Split modes) MAIN R5FSS1 Core1: j784s4-main-r5f1_1-fw (needed only in Split mode) MAIN R5FSS2 Core0: j784s4-main-r5f2_0-fw (both in LockStep and Split modes) MAIN R5FSS2 Core1: j784s4-main-r5f2_1-fw (needed only in Split mode) MCU R5FSS0 Core0: j784s4-mcu-r5f0_0-fw (needed only in Split mode) MCU R5FSS0 Core1: j784s4-mcu-r5f0_1-fw (needed only in Split mode) Signed-off-by:
-
- 06 Jun, 2023 2 commits
-
-
Udit Kumar authored
This patch enables wkup_i2c0 node in board dts file along with pin mux and speed. Also enables underneath eeprom CAV24C256WE. J7200 Datasheet (Table 6-106, Section 6.4 Pin Multiplexing) : https://www.ti.com/lit/ds/symlink/dra821u.pdf J7200 User Guide (Section 4.3, Table 4-2) : https://www.ti.com/lit/ug/spruiw7a/spruiw7a.pdfSigned-off-by:
Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20230419040007.3022780-3-u-kumar1@ti.comSigned-off-by:
-
Keerthy authored
wkup_pmx splits into multiple regions. Like wkup_pmx0 -> 13 pins (WKUP_PADCONFIG 0 - 12) wkup_pmx1 -> 2 pins (WKUP_PADCONFIG 14 - 15) wkup_pmx2 -> 59 pins (WKUP_PADCONFIG 26 - 84) wkup_pmx3 -> 8 pins (WKUP_PADCONFIG 93 - 100) With this split, pin offset needs to be adjusted to match with new pmx for all pins above wkup_pmx0. Example a pin under wkup_pmx1 should start from 0 instead of old offset(0x38 WKUP_PADCONFIG 14 offset) J7200 Datasheet (Table 6-106, Section 6.4 Pin Multiplexing) : https://www.ti.com/lit/ds/symlink/dra821u.pdf Fixes: 9ae21ac4 ("arm64: dts: ti: k3-j7200: Fix wakeup pinmux range") Signed-off-by:
-
