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    • Andrejs Cainikovs's avatar
      arm64: dts: ti: verdin-am62: dahlia: fix audio clock · a15e5320
      Andrejs Cainikovs authored
      In current configuration, wm8904 codec on Dahlia carrier board provides
      distorted audio output. This happens due to reference clock is fixed to
      25MHz and no FLL is enabled. During playback following parameters are set:
      
      44100Hz:
      
      [  310.276924] wm8904 1-001a: Target BCLK is 1411200Hz
      [  310.276990] wm8904 1-001a: Using 25000000Hz MCLK
      [  310.277001] wm8904 1-001a: CLK_SYS is 12500000Hz
      [  310.277018] wm8904 1-001a: Selected CLK_SYS_RATIO of 256
      [  310.277026] wm8904 1-001a: Selected SAMPLE_RATE of 44100Hz
      [  310.277034] wm8904 1-001a: Selected BCLK_DIV of 80 for 1562500Hz BCLK
      [  310.277044] wm8904 1-001a: LRCLK_RATE is 35
      
      Deviation = 1411200 vs 1562500 = 10.721%
      Also, LRCLK_RATE is 35, should be 32.
      
      48000Hz:
      
      [  302.449970] wm8904 1-001a: Target BCLK is 1536000Hz
      [  302.450037] wm8904 1-001a: Using 25000000Hz MCLK
      [  302.450049] wm8904 1-001a: CLK_SYS is 12500000Hz
      [  302.450065] wm8904 1-001a: Selected CLK_SYS_RATIO of 256
      [  302.450074] wm8904 1-001a: Selected SAMPLE_RATE of 48000Hz
      [  302.450083] wm8904 1-001a: Selected BCLK_DIV of 80 for 1562500Hz BCLK
      [  302.450092] wm8904 1-001a: LRCLK_RATE is 32
      
      Deviation = 1536000 vs 1562500 = 1.725%
      
      Enabling wm8904 FLL via providing mclk-fs property to simple-audio-card
      configures clocks properly, but also adjusts audio reference clock
      (mclk), which in case of TI AM62 should be avoided, as it only
      supports 25MHz output [1][2].
      
      This change enables FLL on wm8904 by providing mclk-fs, and drops
      audio reference clock out of DAI configuration, which prevents
      simple-audio-card to adjust it before every playback [3].
      
      41000Hz:
      
      [  111.820533] wm8904 1-001a: FLL configured for 25000000Hz->11289600Hz
      [  111.820597] wm8904 1-001a: Clock source is 0 at 11289600Hz
      [  111.820651] wm8904 1-001a: Using 11289600Hz FLL clock
      [  111.820703] wm8904 1-001a: CLK_SYS is 11289600Hz
      [  111.820798] wm8904 1-001a: Target BCLK is 1411200Hz
      [  111.820847] wm8904 1-001a: Using 11289600Hz FLL clock
      [  111.820894] wm8904 1-001a: CLK_SYS is 11289600Hz
      [  111.820933] wm8904 1-001a: Selected CLK_SYS_RATIO of 256
      [  111.820971] wm8904 1-001a: Selected SAMPLE_RATE of 44100Hz
      [  111.821009] wm8904 1-001a: Selected BCLK_DIV of 80 for 1411200Hz BCLK
      [  111.821051] wm8904 1-001a: LRCLK_RATE is 32
      
      48000Hz:
      
      [  144.119254] wm8904 1-001a: FLL configured for 25000000Hz->12288000Hz
      [  144.119309] wm8904 1-001a: Clock source is 0 at 12288000Hz
      [  144.119364] wm8904 1-001a: Using 12288000Hz FLL clock
      [  144.119413] wm8904 1-001a: CLK_SYS is 12288000Hz
      [  144.119512] wm8904 1-001a: Target BCLK is 1536000Hz
      [  144.119561] wm8904 1-001a: Using 12288000Hz FLL clock
      [  144.119608] wm8904 1-001a: CLK_SYS is 12288000Hz
      [  144.119646] wm8904 1-001a: Selected CLK_SYS_RATIO of 256
      [  144.119685] wm8904 1-001a: Selected SAMPLE_RATE of 48000Hz
      [  144.119723] wm8904 1-001a: Selected BCLK_DIV of 80 for 1536000Hz BCLK
      [  144.119764] wm8904 1-001a: LRCLK_RATE is 32
      
      [1]: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1175479/processor-sdk-am62x-output-audio_ext_refclk0-as-mclk-for-codec-and-mcbsp/4444986#4444986
      [2]: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1188051/am625-audio_ext_refclk1-clock-output---dts-support/4476322#4476322
      [3]: sound/soc/generic/simple-card-utils.c#L441
      
      Fixes: f5bf894c ("arm64: dts: ti: verdin-am62: dahlia: add sound card")
      Suggested-by: default avatarCharles Keepax <ckeepax@opensource.cirrus.com>
      Signed-off-by: default avatarAndrejs Cainikovs <andrejs.cainikovs@toradex.com>
      Reviewed-by: default avatarCharles Keepax <ckeepax@opensource.cirrus.com>
      Reviewed-by: default avatarFrancesco Dolcini <francesco.dolcini@toradex.com>
      Link: https://lore.kernel.org/r/20240315102500.18492-1-andrejs.cainikovs@gmail.comSigned-off-by: default avatarNishanth Menon <nm@ti.com>
      a15e5320