- 31 Jul, 2020 3 commits
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Daniel Palmer authored
The compatible string for the pmsleep region has changed. Update the MStar/Sigmastar v7 base dtsi with the new string. Link: https://lore.kernel.org/r/20200729150748.1945589-4-daniel@0x0f.comSigned-off-by:
Daniel Palmer <daniel@0x0f.com> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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Daniel Palmer authored
Remove the unneeded binding description. Compatible string is in mfd/syscon.yaml now. Link: https://lore.kernel.org/r/20200729150748.1945589-3-daniel@0x0f.comSigned-off-by:
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Daniel Palmer authored
Add a compatible string for the pmsleep register region in the MStar MSC313 SoC. Link: https://lore.kernel.org/r/20200729150748.1945589-2-daniel@0x0f.comSigned-off-by:
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- 28 Jul, 2020 24 commits
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Daniel Palmer authored
MStar v7 SoCs support reset by writing a magic value to a register in the "pmsleep" area. This adds a node for using the syscon reboot driver to trigger a reset. Signed-off-by:
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Daniel Palmer authored
This patch adds a node for the pmsleep area so that other drivers can access registers contained within it. Signed-off-by:
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Daniel Palmer authored
Adds the ARM PMU to the base MStar v7 dtsi. Signed-off-by:
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Daniel Palmer authored
infinity3 has 128KB of SRAM at the IMI region. Signed-off-by:
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Daniel Palmer authored
mercury5 family chips have 128KB of SRAM in the IMI region. Signed-off-by:
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Daniel Palmer authored
infinity has 88KB of SRAM at the IMI region. Signed-off-by:
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Daniel Palmer authored
All MStar v7 SoCs have an internal SRAM region that is between 64KB (infinity2m) and 128KB(infinity3, mercury5). The region is always at the same base address and is used for the second stage loader (MStar IPL or u-boot SPL) and will be used for the DDR self-refresh entry code within the kernel eventually. This patch adds a 128KB region to the SoC and the minimum 64KB SRAM region to the base dtsi. Families with more SRAM will override the size in their family level dtsi. Signed-off-by:
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Daniel Palmer authored
Now there is an mstar directory move the existing MStar specific descriptions into that directory. Signed-off-by:
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Daniel Palmer authored
This adds a YAML description of the pmsleep node used by MStar/SigmaStar Armv7 SoCs. Signed-off-by:
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Daniel Palmer authored
Fixes the filename for the 70mai midrive d08 dts. Signed-off-by:
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Daniel Palmer authored
Adds initial support for the 70mai midrive d08 dash camera. Signed-off-by:
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Daniel Palmer authored
BreadBee is an opensource development board based on the MStar msc313(e) SoC. Hardware details, schematics and so on can be found at: https://github.com/breadbee/breadbeeSigned-off-by:
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Daniel Palmer authored
This adds a family level dtsi for the mercury5 and then a chip level dtsi for the ssc8336n chip. Signed-off-by:
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Daniel Palmer authored
This adds two family level dtsis for the infinity and infinity3 and then adds a chip level dtsi each for a chip in those families. infinity3.dtsi includes infinity.dtsi as these SoCs share most of their memory map and we would have a lot of duplication otherwise. Signed-off-by:
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Daniel Palmer authored
Adds initial dtsi for the base MStar/Sigmastar Armv7 SoCs. These SoCs have very similar memory maps and this will avoid duplicating nodes across multiple dtsis. Signed-off-by:
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Daniel Palmer authored
This adds a YAML description of the l3bridge node needed by the platform code for the MStar/SigmaStar Armv7 SoCs. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Daniel Palmer authored
Initial support for the MStar/Sigmastar Armv7 based IP camera and dashcam SoCs. These chips are interesting in that they contain a Cortex-A7, peripherals and system memory in a single tiny QFN package that can be hand soldered allowing almost anyone to embed Linux in their projects. Signed-off-by:
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Daniel Palmer authored
Signed-off-by:
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Daniel Palmer authored
Add prefix for thingy.jp Signed-off-by:
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Daniel Palmer authored
Add prefix for 70mai Co., Ltd Signed-off-by:
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Daniel Palmer authored
Add prefix for Xiamen Xingchen Technology Co., Ltd Signed-off-by:
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Daniel Palmer authored
Add prefix for MStar Semiconductor, Inc. Signed-off-by:
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Lars Povlsen authored
This patch adds i2c devices and muxes to the Sparx5 reference boards. Link: https://lore.kernel.org/r/20200615133242.24911-11-lars.povlsen@microchip.comReviewed-by:
Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by:
Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by:
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Lars Povlsen authored
This adds a DPLL clock to the Sparx5 SoC. It is used to generate clock to misc peripherals, specifically the SDHCI/eMMC controller. Link: https://lore.kernel.org/r/20200615133242.24911-10-lars.povlsen@microchip.comSigned-off-by:
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- 22 Jul, 2020 6 commits
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Lars Povlsen authored
The Sparx5 support 9 different clock outputs. This include file has defines for each supported clock ordinal. Link: https://lore.kernel.org/r/20200615133242.24911-8-lars.povlsen@microchip.comReviewed-by:
Stephen Boyd <sboyd@kernel.org> Reviewed-by:
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Lars Povlsen authored
This add the DT bindings documentation for the Sparx5 SoC DPLL clock Link: https://lore.kernel.org/r/20200615133242.24911-7-lars.povlsen@microchip.comReviewed-by:
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Lars Povlsen authored
This add pinctrl support to the Microchip Sparx5 SoC. Link: https://lore.kernel.org/r/20200615133242.24911-5-lars.povlsen@microchip.comReviewed-by:
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Lars Povlsen authored
This adds the basic DT structure for the Microchip Sparx5 SoC, and the reference boards, pcb125, pcb134 and pcb135. The two latter have a NAND vs a eMMC centric variant (as a mount option). Link: https://lore.kernel.org/r/20200615133242.24911-4-lars.povlsen@microchip.comReviewed-by:
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Lars Povlsen authored
This adds support for the Microchip Sparx5 ARMv8-based SoC family of TSN-capable gigabit switches. Link: https://lore.kernel.org/r/20200615133242.24911-3-lars.povlsen@microchip.comReviewed-by:
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Lars Povlsen authored
This adds the main Sparx5 SoC DT documentation file, with information abut the supported board types. Link: https://lore.kernel.org/r/20200615133242.24911-2-lars.povlsen@microchip.comReviewed-by:
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- 17 Jul, 2020 5 commits
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Daniele Alessandrelli authored
Add initial device tree for Keem Bay EVM board. With this minimal device tree the board boots fine using an initramfs image. Link: https://lore.kernel.org/r/20200717090414.313530-6-daniele.alessandrelli@linux.intel.comReviewed-by:
Dinh Nguyen <dinguyen@kernel.org> Signed-off-by:
Daniele Alessandrelli <daniele.alessandrelli@intel.com> Signed-off-by:
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Daniele Alessandrelli authored
Add initial device tree for Intel Movidius SoC code-named Keem Bay. This initial DT includes nodes for Cortex-A53 cores, UARTs, GIC, PSCI, and PMU. Link: https://lore.kernel.org/r/20200717090414.313530-5-daniele.alessandrelli@linux.intel.comReviewed-by:
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Daniele Alessandrelli authored
Add maintainers for the new Intel Movidius SoC code-named Keem Bay. Link: https://lore.kernel.org/r/20200717090414.313530-4-daniele.alessandrelli@linux.intel.comReviewed-by:
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Daniele Alessandrelli authored
Document Intel Movidius SoC code-named Keem Bay, along with the Keem Bay EVM board. Link: https://lore.kernel.org/r/20200717090414.313530-3-daniele.alessandrelli@linux.intel.comReviewed-by:
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Daniele Alessandrelli authored
Add ARCH_KEEMBAY configuration option to support Intel Movidius SoC code-named Keem Bay. Link: https://lore.kernel.org/r/20200717090414.313530-2-daniele.alessandrelli@linux.intel.comReviewed-by:
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- 21 Jun, 2020 2 commits
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Linus Torvalds authored
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git://git.kernel.org/pub/scm/linux/kernel/git/pcmoore/selinuxLinus Torvalds authored
Pull SELinux fixes from Paul Moore: "Three small patches to fix problems in the SELinux code, all found via clang. Two patches fix potential double-free conditions and one fixes an undefined return value" * tag 'selinux-pr-20200621' of git://git.kernel.org/pub/scm/linux/kernel/git/pcmoore/selinux: selinux: fix undefined return of cond_evaluate_expr selinux: fix a double free in cond_read_node()/cond_read_list() selinux: fix double free
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