This patch adds a node for the pmsleep area so that other
drivers can access registers contained within it.
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Adds the ARM PMU to the base MStar v7 dtsi.
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

infinity3 has 128KB of SRAM at the IMI region.
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

mercury5 family chips have 128KB of SRAM in the IMI region.
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

infinity has 88KB of SRAM at the IMI region.
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

All MStar v7 SoCs have an internal SRAM region that is between 64KB
(infinity2m) and 128KB(infinity3, mercury5).

The region is always at the same base address and is used for the
second stage loader (MStar IPL or u-boot SPL) and will be used for
the DDR self-refresh entry code within the kernel eventually.

This patch adds a 128KB region to the SoC and the minimum 64KB SRAM
region to the base dtsi. Families with more SRAM will override the
size in their family level dtsi.
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Now there is an mstar directory move the existing MStar specific
descriptions into that directory.
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

This adds a YAML description of the pmsleep node used by
MStar/SigmaStar Armv7 SoCs.
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Fixes the filename for the 70mai midrive d08 dts.
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Adds initial support for the 70mai midrive d08 dash camera.
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

BreadBee is an opensource development board based on the
MStar msc313(e) SoC.

Hardware details, schematics and so on can be found at:
https://github.com/breadbee/breadbeeSigned-off-by: Daniel Palmer <daniel@0x0f.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

This adds a family level dtsi for the mercury5 and then a
chip level dtsi for the ssc8336n chip.
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

This adds two family level dtsis for the infinity and infinity3
and then adds a chip level dtsi each for a chip in those families.

infinity3.dtsi includes infinity.dtsi as these SoCs share most of
their memory map and we would have a lot of duplication otherwise.
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Adds initial dtsi for the base MStar/Sigmastar Armv7 SoCs.

These SoCs have very similar memory maps and this will avoid
duplicating nodes across multiple dtsis.
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

This adds a YAML description of the l3bridge node needed by the
platform code for the MStar/SigmaStar Armv7 SoCs.
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Initial support for the MStar/Sigmastar Armv7 based IP camera
and dashcam SoCs.

These chips are interesting in that they contain a Cortex-A7,
peripherals and system memory in a single tiny QFN package that
can be hand soldered allowing almost anyone to embed Linux
in their projects.
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Add prefix for thingy.jp
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Add prefix for 70mai Co., Ltd
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Add prefix for Xiamen Xingchen Technology Co., Ltd
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Add prefix for MStar Semiconductor, Inc.
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

This patch adds i2c devices and muxes to the Sparx5 reference boards.

Link: https://lore.kernel.org/r/20200615133242.24911-11-lars.povlsen@microchip.comReviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

This adds a DPLL clock to the Sparx5 SoC. It is used to generate clock
to misc peripherals, specifically the SDHCI/eMMC controller.

Link: https://lore.kernel.org/r/20200615133242.24911-10-lars.povlsen@microchip.comSigned-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

The Sparx5 support 9 different clock outputs. This include file has
defines for each supported clock ordinal.

Link: https://lore.kernel.org/r/20200615133242.24911-8-lars.povlsen@microchip.comReviewed-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

This add the DT bindings documentation for the Sparx5 SoC DPLL clock

Link: https://lore.kernel.org/r/20200615133242.24911-7-lars.povlsen@microchip.comReviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

This add pinctrl support to the Microchip Sparx5 SoC.

Link: https://lore.kernel.org/r/20200615133242.24911-5-lars.povlsen@microchip.comReviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

This adds the basic DT structure for the Microchip Sparx5 SoC, and the
reference boards, pcb125, pcb134 and pcb135. The two latter have a
NAND vs a eMMC centric variant (as a mount option).

Link: https://lore.kernel.org/r/20200615133242.24911-4-lars.povlsen@microchip.comReviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

This adds support for the Microchip Sparx5 ARMv8-based SoC family of
TSN-capable gigabit switches.

Link: https://lore.kernel.org/r/20200615133242.24911-3-lars.povlsen@microchip.comReviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

This adds the main Sparx5 SoC DT documentation file, with information
abut the supported board types.

Link: https://lore.kernel.org/r/20200615133242.24911-2-lars.povlsen@microchip.comReviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Add initial device tree for Keem Bay EVM board. With this minimal device
tree the board boots fine using an initramfs image.

Link: https://lore.kernel.org/r/20200717090414.313530-6-daniele.alessandrelli@linux.intel.comReviewed-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Add initial device tree for Intel Movidius SoC code-named Keem Bay.

This initial DT includes nodes for Cortex-A53 cores, UARTs, GIC, PSCI,
and PMU.

Link: https://lore.kernel.org/r/20200717090414.313530-5-daniele.alessandrelli@linux.intel.comReviewed-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Add maintainers for the new Intel Movidius SoC code-named Keem Bay.

Link: https://lore.kernel.org/r/20200717090414.313530-4-daniele.alessandrelli@linux.intel.comReviewed-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Document Intel Movidius SoC code-named Keem Bay, along with the Keem Bay
EVM board.

Link: https://lore.kernel.org/r/20200717090414.313530-3-daniele.alessandrelli@linux.intel.comReviewed-by: Dinh Nguyen <dinguyen@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Add ARCH_KEEMBAY configuration option to support Intel Movidius SoC
code-named Keem Bay.

Link: https://lore.kernel.org/r/20200717090414.313530-2-daniele.alessandrelli@linux.intel.comReviewed-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Pull SELinux fixes from Paul Moore:
 "Three small patches to fix problems in the SELinux code, all found via
  clang.

  Two patches fix potential double-free conditions and one fixes an
  undefined return value"

* tag 'selinux-pr-20200621' of git://git.kernel.org/pub/scm/linux/kernel/git/pcmoore/selinux:
  selinux: fix undefined return of cond_evaluate_expr
  selinux: fix a double free in cond_read_node()/cond_read_list()
  selinux: fix double free

Pull pin control fixes from Linus Walleij:
 "Some early fixes collected during the first week after the merge
  window, all pretty self-evident, with the details below. The revert is
  the crucial thing.

   - Fix a warning on the Qualcomm SPMI GPIO chip being instatiated
     twice without a unique irqchip struct

   - Use the noirq variants of the suspend and resume callbacks in the
     Tegra driver

   - Clean up the errorpath on the MCP23s08 driver

   - Revert the use of devm_of_iomap() in the Freescale driver as it was
     regressing the platform

   - Add some missing pins in the Qualcomm IPQ6018 driver

   - Fix a simple documentation bug in the pinctrl-single driver"

* tag 'pinctrl-v5.8-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
  pinctrl: single: fix function name in documentation
  pinctrl: qcom: ipq6018 Add missing pins in qpic pin group
  Revert "pinctrl: freescale: imx: Use 'devm_of_iomap()' to avoid a resource leak in case of error in 'imx_pinctrl_probe()'"
  pinctrl: mcp23s08: Split to three parts: fix ptr_ret.cocci warnings
  pinctrl: tegra: Use noirq suspend/resume callbacks
  pinctrl: qcom: spmi-gpio: fix warning about irq chip reusage

Merge tag 'kbuild-fixes-v5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild

Pull Kbuild fixes from Masahiro Yamada:

 - fix -gz=zlib compiler option test for CONFIG_DEBUG_INFO_COMPRESSED

 - improve cc-option in scripts/Kbuild.include to clean up temp files

 - improve cc-option in scripts/Kconfig.include for more reliable
   compile option test

 - do not copy modules.builtin by 'make install' because it would break
   existing systems

 - use 'userprogs' syntax for watch_queue sample

* tag 'kbuild-fixes-v5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild:
  samples: watch_queue: build sample program for target architecture
  Revert "Makefile: install modules.builtin even if CONFIG_MODULES=n"
  scripts: Fix typo in headers_install.sh
  kconfig: unify cc-option and as-option
  kbuild: improve cc-option to clean up all temporary files
  Makefile: Improve compressed debug info support detection

Pull powerpc fixes from Michael Ellerman:

 - One fix for the interrupt rework we did last release which broke
   KVM-PR

 - Three commits fixing some fallout from the READ_ONCE() changes
   interacting badly with our 8xx 16K pages support, which uses a pte_t
   that is a structure of 4 actual PTEs

 - A cleanup of the 8xx pte_update() to use the newly added pmd_off()

 - A fix for a crash when handling an oops if CONFIG_DEBUG_VIRTUAL is
   enabled

 - A minor fix for the SPU syscall generation

Thanks to Aneesh Kumar K.V, Christian Zigotzky, Christophe Leroy, Mike
Rapoport, Nicholas Piggin.

* tag 'powerpc-5.8-3' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux:
  powerpc/8xx: Provide ptep_get() with 16k pages
  mm: Allow arches to provide ptep_get()
  mm/gup: Use huge_ptep_get() in gup_hugepte()
  powerpc/syscalls: Use the number when building SPU syscall table
  powerpc/8xx: use pmd_off() to access a PMD entry in pte_update()
  powerpc/64s: Fix KVM interrupt using wrong save area
  powerpc: Fix kernel crash in show_instructions() w/DEBUG_VIRTUAL

Pull crypto fixes from Herbert Xu:

 - NULL dereference in octeontx

 - PM reference imbalance in ks-sa

 - deadlock in crypto manager

 - memory leak in drbg

 - missing socket limit check on receive SG list size in algif_skcipher

 - typos in caam

 - warnings in ccp and hisilicon

* 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6:
  crypto: drbg - always try to free Jitter RNG instance
  crypto: marvell/octeontx - Fix a potential NULL dereference
  crypto: algboss - don't wait during notifier callback
  crypto: caam - fix typos
  crypto: ccp - Fix sparse warnings in sev-dev
  crypto: hisilicon - Cap block size at 2^31
  crypto: algif_skcipher - Cap recv SG list at ctx->used
  hwrng: ks-sa - Fix runtime PM imbalance on error