- 26 Sep, 2017 40 commits
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Andrey Grodzovsky authored
We can keep a 1:1 relation between a link and a physical connector and hence skip the iteration. This function is used in context of only physical connetors. Signed-off-by:
Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Reviewed-by:
Harry Wentland <Harry.Wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
Tony Cheng <Tony.Cheng@amd.com> Signed-off-by:
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Zeyu Fan authored
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Zeyu Fan <Zeyu.Fan@amd.com> Acked-by:
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Reza Amini authored
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Reza Amini <reza.amini@amd.com> Reviewed-by:
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Reza Amini authored
Surface information is by default copied from old context in dc_commit_stream. Thus unchange streams will not be affected. For new streams, we shouldn't validate the new mode against the surface configuration of old_context. Signed-off-by:
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Shirish S authored
This patch introduces amdgpu_drm_plane_state structure, which subclasses drm_plane_state and holds data suitable for configuring hardware. It switches reset(), atomic_duplicate_state() & atomic_destroy_state() functions to new internal implementation, earlier they were pointing to drm core functions. TESTS(On Chromium OS on Stoney Only) * Builds without compilation errors. * 'plane_test' passes for XR24 format based Overlay plane. * Chromium OS ui comes up. Signed-off-by:
Shirish S <shirish.s@amd.com> Signed-off-by:
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Harry Wentland authored
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Alex Deucher authored
Current design has per-crtc-plane model. As a result, for asic's that support underlay, are unable to expose it to user space for modesetting. To enable this, the drm driver intialisation now runs for number of surfaces instead of stream/crtc. This patch plumbs surface capabilities to drm framework so that it can be effectively used by user space. Tests: (On Chromium OS for Stoney Only) * 'modetest -p' now shows additional plane with YUV capabilities in case of CZ and ST. * 'plane_test' fails with below error: [drm:amdgpu_dm_connector_atomic_set_property [amdgpu]] *ERROR* Unsupported screen depth 0 as ther is no support for YUYV * Checked multimonitor display works fine Signed-off-by:
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Ding Wang authored
ASICs using bios parser 1 don't check HBR3 capability as there is no such a bit usHBR3En in ATOM_ENCODER_CAP_RECORDER. Therefore, will use ATOM_ENCODER_CAP_RECORDER_V2 and thus obtain the usHBR3En bit. Signed-off-by:
Ding Wang <ding.wang@amd.com> Acked-by:
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Vitaly Prosyak authored
Frame sequential, top-bottom and side-by-side support. Signed-off-by:
Vitaly Prosyak <vitaly.prosyak@amd.com> Acked-by:
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Tony Cheng authored
Signed-off-by:
Hersen Wu <hersenxs.wu@amd.com> Signed-off-by:
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Yongqiang Sun authored
Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
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Roman Li authored
In some use-cases, e.g. multiple 4K displays, exisitng wait time for reg update of 30msec timed out during mode setiing that sometimes resulted in system bad state as we continue without waiting for registry update complete. Increasing timeout to 35msec fixes that problem. Signed-off-by:
Roman Li <Roman.Li@amd.com> Acked-by:
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Charlene Liu authored
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Charlene Liu <charlene.liu@amd.com> Acked-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Signed-off-by:
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Andrey Grodzovsky authored
Register ISR hnadler on the new interrupt. Signed-off-by:
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Andrey Grodzovsky authored
VBLANK interrupt is driven bu line buffer vcounter which is ahead of CRTC vcounter. Use an interrupt that fires at the actual CRTC vblank start boundry. Signed-off-by:
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Harry Wentland authored
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Yongqiang Sun authored
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xhdu authored
Leave hardcoded if no ContainerId provided by DM. Signed-off-by:
Duke Du <Duke.Du@amd.com> Acked-by:
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Charlene Liu authored
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Charlene Liu authored
Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Signed-off-by:
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Charlene Liu authored
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Leon Elazar authored
1. Locking all pipes before doing any changes 2. Applying surface for both top and bottom pipes Signed-off-by:
Leon Elazar <leon.elazar@amd.com> Acked-by:
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Andrey Grodzovsky authored
Signed-off-by:
Jordan Lazare <Jordan.Lazare@amd.com> Reviewed-by:
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Andrey Grodzovsky authored
This will return back MAX cursor size for given ASIC. Signed-off-by:
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Andrey Grodzovsky authored
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Andrey Grodzovsky authored
Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Andrey Grodzovsky authored
ret value in amdgpu_dm_atomic_check was not rest to EINVAL after drm_atomic_add_affected_planes and by this making any subsequent validation failure pass when returning to atomic_check. v2: Add WARN_ON print for dc_commit_streams in amdgpu_dm_atomic_commit_tail since this should never fail. Signed-off-by:
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Tony Cheng authored
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Tony Cheng authored
- also some clean up Signed-off-by:
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Yongqiang Sun authored
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Dmytro Laktyushkin authored
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Tony Cheng authored
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Leon Elazar authored
1. Adding the ability to update the stream parameters during FULL_UPDATE type Signed-off-by:
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Dmytro Laktyushkin authored
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Logatharshan Thothiralingam authored
[Problem] VSR greyed out [Root cause] When converting fractions, we were using the integer function, which let to a large display clock and the view was not supported [Solution] Change the integer to fraction functions Signed-off-by:
Logatharshan Thothiralingam <logatharshan.thothiralingam@amd.com> Acked-by:
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Leon Elazar authored
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Alex Deucher authored
Add the DC display module to drive the DCE12 IP on vega10. Signed-off-by: -
Alex Deucher authored
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Jordan Lazare authored
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