Merge tag 'amlogic-dt64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/late

Pull "Amlogic 64-bit DT changes for v4.9, round 2" from Kevin Hilman:

Primarily adding support for newly added drivers

- USB host
- I2C
- SPI flash controller
- PWM
- mailbox, MHU
- pinctrl: add pins for SPI, I2C, SDIO

and then enabling these drivers on various boards.

* tag 'amlogic-dt64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
  ARM64: dts: meson-gxbb-vega-s95: Enable USB Nodes
  ARM64: dts: meson-gxbb-p20x: Enable USB Nodes
  ARM64: dts: meson-gxbb: add USB Nodes
  ARM64: dts: gxbb: add i2c bus
  ARM64: dts: meson-gxbb: add I2C nodes
  ARM64: dts: meson-gxbb: add pins for I2C
  ARM64: dts: meson-gxbb: Add SPIFC node
  ARM64: dts: meson-gxbb: add the SDIO pins
  ARM64: dts: amlogic: add spi nor pins
  ARM64: dts: meson-gxbb: use the new GXBB DWMAC glue driver
  ARM64: dts: meson-gxbb: Add Meson GXBB PWM Controller nodes
  ARM64: dts: meson-gxbb: Add Meson MHU Node
  ARM64: dts: amlogic: enable ethernet on all Tronsmart Vega S95 devices

Merge tag 'amlogic-drivers-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/late

Pull "Amlogic driver updates for v4.9, 2nd round" from Kevin Hilman:

- media: update IR support for newer SoCs
- firmware: add secure monitor driver
- net: new stmmac glue driver
- usb: udd DWC2 support for meson-gxbb
- clocks: expose more clock IDs for use by DT
- DT binding updates

* tag 'amlogic-drivers-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: (21 commits)
  clk: gxbb: expose i2c clocks
  clk: gxbb: expose USB clocks
  clk: gxbb: expose spifc clock
  clk: gxbb: expose MPLL2 clock for use by DT
  Documentation: dt-bindings: Add documentation for the Meson USB2 PHYs
  usb: dwc2: add support for Meson8b and GXBB SoCs
  net: stmmac: update the module description of the dwmac-meson driver
  net: stmmac: add a glue driver for the Amlogic Meson 8b / GXBB DWMAC
  stmmac: introduce get_stmmac_bsp_priv() helper
  net: dt-bindings: Document the new Meson8b and GXBB DWMAC bindings
  clk: meson-gxbb: Export PWM related clocks for DT
  meson: clk: Add support for clock gates
  gxbb: clk: Adjust MESON_GATE macro to be shared with meson8b
  clk: meson: Copy meson8b CLKID defines to private header file
  meson: clk: Rename register names according to Amlogic datasheet
  meson: clk: Move register definitions to meson8b.h
  clk: meson: Rename meson8b-clkc.c to reflect gxbb naming convention
  nvmem: amlogic: Add Amlogic Meson EFUSE driver
  firmware: Amlogic: Add secure monitor driver
  media: rc: meson-ir: Add support for newer versions of the IR decoder
  ...

Amlogic driver updates for v4.9, 2nd round
- media: update IR support for newer SoCs
- firmware: add secure monitor driver
- net: new stmmac glue driver
- usb: udd DWC2 support for meson-gxbb
- clocks: expose more clock IDs for use by DT
- DT binding updates

Enable both gxbb USB controller and add a 5V regulator for the OTG port
VBUS
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

Enable both gxbb USB controller and add a 5V regulator for the OTG port
VBUS
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
[khilman: rename vbus node to match P200 schematics]
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

I2C and AO_I2C clocks are needed for the i2c driver, expose to DT
(and comment out in clk driver)
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

USB0_DDR_BRIDGE and USB1_DDR_BRIDGE1 are needed for the related
dwc2 usb controller. USB, USB0 and USB1 are needed for the PHYs.
Expose these clocks to DT and comment out in clk driver.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

SPI clock is needed for the spifc driver, expose to DT
(and comment out in the clk driver)
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

This exposes the MPLL2 clock as this is one of the input clocks of the
ethernet controller's internal mux.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

Merge branch 'clk-meson-gxbb' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux into v4.8/drivers

* 'clk-meson-gxbb' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: meson-gxbb: Export PWM related clocks for DT
  meson: clk: Add support for clock gates
  gxbb: clk: Adjust MESON_GATE macro to be shared with meson8b
  clk: meson: Copy meson8b CLKID defines to private header file
  meson: clk: Rename register names according to Amlogic datasheet
  meson: clk: Move register definitions to meson8b.h
  clk: meson: Rename meson8b-clkc.c to reflect gxbb naming convention
  clk: meson: Fix invalid use of sizeof in gxbb_aoclkc_probe()
  clk: meson: Add GXBB AO Clock and Reset controller driver
  dt-bindings: clock: reset: Add GXBB AO Clock and Reset Bindings
  clk: gxbb: add MMC gate clocks, and expose for DT

Add the documentation for the bindings for the Meson8b and GXBB USB2
PHYs.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

Add compatible strings for amlogic Meson8b and GXBB SoCs with the
corresponding configuration parameters.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

Add the nodes for the dwc2 USB controller and the related USB PHYs.
Currently we force usb0 to host mode because OTG is currently not
working in our PHY driver.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

Add nodes for i2c bus on gxbb based platforms.
On the OdroidC2 (I2C A) and P200 (I2C B), the pull-up resistor are
present directly on the board. This indicates that these pins are
dedicated to i2c.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

This is used to configure the pins of the sd_emmc_a controller to
which an SDIO module is connected (when available).
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

The Amlogic reference driver uses the "mc_val" devicetree property to
configure the PRG_ETHERNET_ADDR0 register. Unfortunately it uses magic
values for this configuration.
According to the datasheet the PRG_ETHERNET_ADDR0 register is at address
0xc8834108. However, the reference driver uses 0xc8834540 instead.
According to my tests, the value from the reference driver is correct.

No changes are required to the board dts files because the only
required configuration option is the phy-mode, which had to be
configured correctly before as well.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Jérôme Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

All of these have a Realtek Gbit RGMII PHY.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

Merge tag 'integrator-armsoc-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into next/late

Pull "This is a bunch of Integrator changes for v4.9" Linus Walleij:

- Add and fix a bunch of clocks in the DTS corresponding
  to the new clock support merged into the clk tree.
- Move the CLCD display configuration from boardfile to
  device tree using the new CLCD support merged into the
  fbdev tree.
- Cut some auxdata.
- Cut some static remappings.
- Move the sched_clock() counter to use syscon+regmap.

* tag 'integrator-armsoc-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator:
  ARM: integrator: read counter using syscon/regmap
  ARM: integrator: cut down on static maps
  ARM: integrator: delete some auxdata
  ARM: integrator: move CP CLCD display to DTS
  ARM: dts: add the core module clocks to Integrator/CP
  ARM: dts: Add the core module clocks to Integrator/AP
  ARM: dts: add the Integrator/AP baseboard clocks
  ARM: dts: set the 24MHz xtal as parent of the UART clock

Merge tag 'renesas-arm64-dt-for-v4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/late

Pull "Renesas ARM64 Based SoC DT Updates for v4.9" from Simon Horman:

Clean up:
* Remove unnecessary cap-mmc-highspeed property from SDHI nodes on r8a7795 SoC
* Add SoC-specific compatible property to audio-dmac nodes on r8a7795 SoC

New Board:
* Add r8a7794/h3ulcb board

Enablement:
* Add PFC and GPIO to r8a7796 SoC
* Enable DU and USB 2.0 on r8a7795/salvator-x board
* Add VTP, FCPV, FCPF and FDP1 to r8a7795 SoC
* Set maximum frequency for SDHI clocks on r8a7795 SoC

* tag 'renesas-arm64-dt-for-v4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (43 commits)
  arm64: dts: r8a7796: Add GPIO device nodes
  arm64: dts: r8a7796: salvator-x: add serial console pins
  arm64: dts: r8a7796: Add pinctrl device node
  arm64: dts: r8a7795: salvator-x: Configure pins for the DU RGB output
  arm64: dts: h3ulcb: enable GPIO leds
  arm64: dts: h3ulcb: Sound SSI support
  arm64: dts: h3ulcb: enable SDHI0
  arm64: dts: h3ulcb: enable GPIO keys
  arm64: dts: r8a7795: remove unnecessary cap-mmc-highspeed property
  arm64: dts: h3ulcb: enable USB2.0 Host channel 1
  arm64: dts: h3ulcb: enable USB2 PHY of channel 1
  arm64: dts: h3ulcb: enable WDT
  arm64: dts: h3ulcb: enable EXTALR clk
  arm64: dts: h3ulcb: enable I2C2
  arm64: dts: h3ulcb: enable EthernetAVB
  arm64: dts: h3ulcb: enable SCIF clk and pins
  arm64: dts: h3ulcb: initial device tree
  arm64: dts: h3ulcb: add H3ULCB board DT bindings
  arm64: dts: r8a7795: Add SoC-specific compatible property to audio-dmac nodes
  arm64: dts: r8a7795: renesas: salvator-x: Enable DU
  ...

Merge tag 'amlogic-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/late

Pull "Amlogic 64-bit DT changes for v4.9" from Kevin Hilman:

- add watchdog, reset, IR remote, PWM
- add secure monitor and eFuse
- add always-on (AO) domain clock and reset

* tag 'amlogic-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
  ARM64: dts: amlogic: gxbb: Enable NVMEM
  documentation: Add nvmem bindings documentation
  ARM64: dts: amlogic: gxbb: Enable secure monitor
  documentation: Add secure monitor bindings documentation
  ARM64: dts: meson-gxbb: Add PWM pinctrl nodes
  ARM64: dts: meson-gxbb: Enable the the IR decoder on supported boards
  ARM64: dts: meson-gxbb: Add Infrared Remote Controller decoder
  dt-bindings: media: meson-ir: Add Meson8b and GXBB compatible strings
  ARM64: dts: amlogic: add the input pin for the IR remote
  ARM64: dts: meson-gxbb: Add GXBB AO Clock and Reset node
  clk: meson: Fix invalid use of sizeof in gxbb_aoclkc_probe()
  clk: meson: Add GXBB AO Clock and Reset controller driver
  dt-bindings: clock: reset: Add GXBB AO Clock and Reset Bindings
  ARM64: DTS: meson-gxbb: switch ethernet to real clock
  ARM64: dts: amlogic: meson-gxbb: Add watchdog node

Merge tag 'sunxi-dt-for-4.9-2' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into next/late

Merge "Allwinner DT changes for 4.9, take 2" from Maxime Ripard:

A second set of device tree changes, this time switching a few SoCs to the
new sunxi-ng clock framework. We also added the support for a new SoC
(NextThing GR8 and its evaluation board), and the support for the DRM
driver in the A33.

To maintain bisectability, while avoiding some un-trivial merge
conflicts, I had to merge the clk branch that I've sent a PR to Mike
and Stephen. This branch will of course be stable.

* tag 'sunxi-dt-for-4.9-2' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: (53 commits)
  ARM: dts: gr8: Add support for the GR8 evaluation board
  ARM: dts: Add NextThing GR8 dtsi
  ARM: dts: sun8i: Move A23/A33 usbphy and usb_otg nodes to common dtsi
  ARM: sun8i: a23/a33: Add RGB666 pins
  ARM: sun8i: a33: Add display pipeline
  ARM: sun8i: Convert the A23 and A33 to the CCU
  ARM: dts: sun6i: switch A31/A31s to new CCU clock bindings
  clk: sunxi-ng: Add hardware dependency
  clk: sunxi-ng: Add A23 CCU
  clk: sunxi-ng: Add A33 CCU support
  clk: sunxi-ng: Add N-class clocks support
  clk: sunxi-ng: mux: Add mux table macro
  clk: sunxi-ng: div: Allow to set a maximum
  clk: sunxi-ng: div: Add kerneldoc for the _ccu_div structure
  clk: sunxi-ng: div: Add mux table macros
  devicetree: Add vendor prefix for FriendlyARM
  ARM: dts: sun8i: Add dts file for the NanoPi NEO SBC
  ARM: dts: sun8i-q8-common: Add support for SDIO wifi controllers
  ARM: dts: sun8i: Add dts file for the Orange Pi Plus2E SBC
  ARM: dts: sun8i: Orange Pi Plus dts is for the Plus and Plus 2
  ...

The GR8-EVB is a small board with an NextThing GR8, an Hynix MLC NAND,
an AXP209 PMIC, USB host and OTG, an SPDIF output and a connectors for CSI,
I2S and LCD.
Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>

The GR8 is an SoC made by Nextthing loosely based on the sun5i family.

Since it's not clear yet what we can factor out and merge with the A10s and
A13 support, let's keep it out of the sun5i.dtsi include tree. We will
figure out what can be shared when things settle down.
Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>

The usbphy and usb_otg nodes in the A23 and A33 dts files only differ
by compatible, and for the usbphy, the size of one of its register
regions.

Move all the common bits to the A23/A33 common dtsi file.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

The LCD output needs to be muxed. Add the proper pinctrl node.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>

Add all the needed blocks to the A33 DTSI.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>

Now that we have support for the CCU driver in sunxi-ng, convert the A23
and A33 DTs to that driver.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>

Now that we have a different clock representation, switch to it.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

The sunxi-ng clock driver is useless for other architectures.
Signed-off-by: Jean Delvare <jdelvare@suse.de>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Add support for the clock unit found in the A23. Due to the similarities
with the A33, it also shares its clock IDs to allow sharing the DTSI.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>

This commit introduces the clocks found in the Allwinner A33 CCU.

Since this SoC is very similar to the A23, and we share a significant share
of the DTSI, the clock IDs that are going to be used will also be shared
with the A23, hence the name of the various header files.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>

Add support for the class with a single factor, N, being a multiplier.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>