- 15 Jun, 2023 4 commits
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Keerthy authored
VTM stands for Voltage Thermal Management. Add the thermal zones. Six sensors mapping to six thermal zones. Main0, Main1, Main2, Main3, WKUP1 & WKUP2 domains respectively. Signed-off-by:
Keerthy <j-keerthy@ti.com> [bb@ti.com: rebased on v6.3-rc1] Signed-off-by:
Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20230405215328.3755561-8-bb@ti.comSigned-off-by:
Vignesh Raghavendra <vigneshr@ti.com>
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Keerthy authored
VTM stands for Voltage Thermal Management. Add the thermal zones. Three sensors mapping to 3 thermal zones. MCU, MPU & Main domains respectively. Signed-off-by:
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Keerthy authored
VTM stands for Voltage Thermal Management. Add the thermal zones. Five sensors mapping ton 5 thermal zones. WKUP, MPU, C7x, GPU & R5F respectively. Signed-off-by:
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Keerthy authored
VTM stands for Voltage Thermal Management. Add the thermal zones. Seven sensors mapping to seven thermal zones. Main0, Main1, Main2, Main3, Main4, WKUP1 & WKUP2 domains respectively. Signed-off-by:
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- 14 Jun, 2023 15 commits
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Bryan Brattlof authored
The am62ax supports a single Voltage and Thermal Management (VTM) device located in the wakeup domain with three associated temperature monitors located in various hot spots of the die. Signed-off-by:
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Bryan Brattlof authored
The am62x supports a single Voltage and Thermal Management (VTM) module located in the wakeup domain with two associated temperature monitors located in hot spots of the die. Signed-off-by:
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Bryan Brattlof authored
The am64x supports a single VTM module which is located in the main domain with two associated temperature monitors located at different hot spots on the die. Tested-by:
Christian Gmeiner <christian.gmeiner@gmail.com> Signed-off-by:
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Aswath Govindraju authored
x1 lane PCIe slot in the common processor board is enabled and connected to J721S2 SOM. Add PCIe DT node in common processor board to reflect the same. Reviewed-by:
Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by:
Aswath Govindraju <a-govindraju@ti.com> Signed-off-by:
Matt Ranostay <mranostay@ti.com> Signed-off-by:
Ravi Gunasekaran <r-gunasekaran@ti.com> Reviewed-by:
Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230331090028.8373-9-r-gunasekaran@ti.comSigned-off-by:
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Aswath Govindraju authored
Add PCIe1 RC device tree node for the single PCIe instance present on the J721S2. Reviewed-by:
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Aswath Govindraju authored
J721S2 has an OSPI NOR flash on its SOM connected the OSPI0 instance and a QSPI NOR flash on the common processor board connected to the OSPI1 instance. Add support for the same Reviewed-by:
Vaishnav Achath <vaishnav.a@ti.com> Signed-off-by:
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Aswath Govindraju authored
The board uses lane 1 of SERDES for USB. Set the mux accordingly. The USB controller and EVM supports super-speed for USB0 on the Type-C port. However, the SERDES has a limitation that up to 2 protocols can be used at a time. The SERDES is wired for PCIe, eDP and USB super-speed. It has been chosen to use PCIe and eDP as default. So restrict USB0 to high-speed mode. Signed-off-by:
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Aswath Govindraju authored
Configure first lane to PCIe, the second lane to USB and the last two lanes to eDP. Also, add sub-nodes to SERDES0 DT node to represent SERDES0 is connected to PCIe. Signed-off-by:
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Aswath Govindraju authored
Add support for two instance of OSPI in J721S2 SoC. Reviewed-by:
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Matt Ranostay authored
Add dt node for the single instance of WIZ (SERDES wrapper) and SERDES module shared by PCIe, eDP and USB. Signed-off-by:
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Aswath Govindraju authored
Add support for single instance of USB 3.0 controller in J721S2 SoC. Signed-off-by:
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Roger Quadros authored
USB0 is a Type-C port with dual data role and power sink. Signed-off-by:
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Hari Nagalla authored
Reserve memory for remote processors. Two memory regions are reserved for each remote processor. The first 1Mb region is used for virtio Vring buffers for IPC and the second region is used for holding resource table, trace buffer and as external memory to the remote processor. The mailboxes are also assigned for each remote processor. Signed-off-by:
Hari Nagalla <hnagalla@ti.com> Link: https://lore.kernel.org/r/20230502231527.25879-4-hnagalla@ti.comSigned-off-by:
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Hari Nagalla authored
The J784S4 SoCs have four TMS320C71x DSP subsystems in the MAIN voltage domain. The functionality of these DSP subsystems is similar to the C71x DSP subsystems on earlier k3 device J721S2. Each subsystem has a 48 KB of L1D configurable SRAM/Cache and 512 KB of L2 SRAM/Cache. This subsystem has a CMMU but is not currently used. The inter-processor communication between the main A72 cores and the C71x DSPs is achieved through shared memory and mailboxes. Add the DT nodes for these DSP processor sub-systems. Signed-off-by:
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Hari Nagalla authored
The J784S4 SoCs have 4 dual-core Arm Cortex-R5F processor (R5FSS) subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within the MCU domain, and the remaining three clusters are present in the MAIN domain (MAIN_R5FSS0, MAIN_R5FSS1 & MAIN_R5FSS2). The functionality of the R5FSS is same as the R5FSS functionality on earlier K3 platform device J721S2. Each of the R5FSS can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. These subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal memories for each core split between two banks - ATCM and BTCM (further interleaved into two banks). There are some IP integration differences from standard Arm R5 clusters such as the absence of an ACP port, presence of an additional TI-specific Region Address Translater (RAT) module for translating 32-bit CPU addresses into larger system bus addresses etc. Add the DT nodes for the R5F cluster/subsystems, the two R5F cores are each added as child nodes to the corresponding cluster node. The clusters are configured to run in LockStep mode by default, with the ATCMs enabled to allow the R5 cores to execute code from DDR with boot-strapping code from ATCM. The inter-processor communication between the main A72 cores and these processors is achieved through shared memory and Mailboxes. The following firmware names are used by default for these cores, and can be overridden in a board dts file if needed: MAIN R5FSS0 Core0: j784s4-main-r5f0_0-fw (both in LockStep and Split modes) MAIN R5FSS0 Core1: j784s4-main-r5f0_1-fw (needed only in Split mode) MAIN R5FSS1 Core0: j784s4-main-r5f1_0-fw (both in LockStep and Split modes) MAIN R5FSS1 Core1: j784s4-main-r5f1_1-fw (needed only in Split mode) MAIN R5FSS2 Core0: j784s4-main-r5f2_0-fw (both in LockStep and Split modes) MAIN R5FSS2 Core1: j784s4-main-r5f2_1-fw (needed only in Split mode) MCU R5FSS0 Core0: j784s4-mcu-r5f0_0-fw (needed only in Split mode) MCU R5FSS0 Core1: j784s4-mcu-r5f0_1-fw (needed only in Split mode) Signed-off-by:
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- 06 Jun, 2023 3 commits
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Udit Kumar authored
This patch enables wkup_i2c0 node in board dts file along with pin mux and speed. Also enables underneath eeprom CAV24C256WE. J7200 Datasheet (Table 6-106, Section 6.4 Pin Multiplexing) : https://www.ti.com/lit/ds/symlink/dra821u.pdf J7200 User Guide (Section 4.3, Table 4-2) : https://www.ti.com/lit/ug/spruiw7a/spruiw7a.pdfSigned-off-by:
Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20230419040007.3022780-3-u-kumar1@ti.comSigned-off-by:
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Keerthy authored
wkup_pmx splits into multiple regions. Like wkup_pmx0 -> 13 pins (WKUP_PADCONFIG 0 - 12) wkup_pmx1 -> 2 pins (WKUP_PADCONFIG 14 - 15) wkup_pmx2 -> 59 pins (WKUP_PADCONFIG 26 - 84) wkup_pmx3 -> 8 pins (WKUP_PADCONFIG 93 - 100) With this split, pin offset needs to be adjusted to match with new pmx for all pins above wkup_pmx0. Example a pin under wkup_pmx1 should start from 0 instead of old offset(0x38 WKUP_PADCONFIG 14 offset) J7200 Datasheet (Table 6-106, Section 6.4 Pin Multiplexing) : https://www.ti.com/lit/ds/symlink/dra821u.pdf Fixes: 9ae21ac4 ("arm64: dts: ti: k3-j7200: Fix wakeup pinmux range") Signed-off-by: -
Nishanth Menon authored
wkup_uart and main_uart1 on this platform is used by tifs and DM firmwares. Describe them for completeness including the pinmux. Signed-off-by:
Nishanth Menon <nm@ti.com> [bb@ti.com: updated pinmux and commit subject] Signed-off-by:
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- 08 May, 2023 18 commits
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Nishanth Menon authored
Remove "syscon" nodes added for pcieX_ctrl and have the PCIe node point to the parent with an offset argument. This change is as discussed in [1]. [1] http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.comSigned-off-by:
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Krzysztof Kozlowski authored
As all level 2 and level 3 caches are unified, add required cache-unified properties to fix warnings like: k3-am6528-iot2050-basic-pg2.dtb: l3-cache0: 'cache-unified' is a required property Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by:
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Nishanth Menon authored
iot boards have always defined their own aliases and with the base-board defining it's own aliases, there are no pending boards depending on common aliases defined in SoC level. aliases are meant to be defined appropriately based on the exposed interfaces at a board level, drop the aliases defined at SoC level. Signed-off-by:
Kamlesh Gurudasani <kamlesh@ti.com> Link: https://lore.kernel.org/r/20230419225913.663448-8-nm@ti.comSigned-off-by:
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Nishanth Menon authored
Introduce aliases compatible with the base definition, but focussed on the interfaces that have been exposed on the platform. Signed-off-by:
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Nishanth Menon authored
Enable AT24CM01 on the base board using the corresponding compatible. Signed-off-by:
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Nishanth Menon authored
Add the missing vdd_mpu PMIC. Signed-off-by:
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Nishanth Menon authored
Hold the DDR vtt regulator active for functionality. Signed-off-by:
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Nishanth Menon authored
Rename the regulator node names to the standard regulator-0.. numbers. Signed-off-by:
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Nishanth Menon authored
Many of the definitions depend on pinmux done by the bootloader. Be explicit about the pinmux for functionality and completeness. Signed-off-by:
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Nishanth Menon authored
Add nodes for watchdogs: - 5 in main domain - 1 in MCU domain - 1 in wakeup domain Signed-off-by:
Tony Lindgren <tony@atomide.com> Reviewed-by:
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Nishanth Menon authored
Similar to commit 3308a31c ("arm64: dts: ti: k3-am62: Add general purpose timers for am62"), there are 12 general purpose timers on am62a7 split between 8 in main and 4 in mcu domains. The 4 in mcu domain do not have interrupts that are routable to a53. We configure the timers with the 25 MHz input clock by default as the 32.768 kHz clock may not be wired on the device. We leave the MCU domain timers clock mux unconfigured, and mark the MCU domain timers reserved. The MCU domain timers are likely reserved by the software for the ESM module. Signed-off-by:
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Nishanth Menon authored
Drop bootargs from the dts. The console arguments are already covered in stdout-path property and earlycon is a debug property that should be enabled only when debug is desired and not as default. Link: https://lore.kernel.org/linux-arm-kernel/81134eb9-2b7d-05bc-3035-a47f020861a8@linaro.org/Suggested-by:
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Nishanth Menon authored
Drop bootargs from the dts. The console arguments are already covered in stdout-path property and earlycon is a debug property that should be enabled only when debug is desired and not as default. Link: https://lore.kernel.org/linux-arm-kernel/81134eb9-2b7d-05bc-3035-a47f020861a8@linaro.org/Suggested-by:
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Nishanth Menon authored
Drop bootargs from the dts. The console arguments are already covered in stdout-path property and earlycon is a debug property that should be enabled only when debug is desired and not as default. Link: https://lore.kernel.org/linux-arm-kernel/81134eb9-2b7d-05bc-3035-a47f020861a8@linaro.org/Suggested-by:
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Nishanth Menon authored
Drop bootargs from the dts. earlycon is a debug property that should be enabled only when debug is desired and not as default - see referenced link on discussion on this topic. Cc: Jan Kiszka <jan.kiszka@siemens.com> Link: https://lore.kernel.org/linux-arm-kernel/81134eb9-2b7d-05bc-3035-a47f020861a8@linaro.org/Suggested-by:
Jan Kiszka <jan.kiszka@siemens.com> Link: https://lore.kernel.org/r/20230419141222.383567-3-nm@ti.comSigned-off-by:
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Nishanth Menon authored
Drop bootargs from the dts. The console arguments are already covered in stdout-path property and earlycon is a debug property that should be enabled only when debug is desired and not as default. Link: https://lore.kernel.org/linux-arm-kernel/81134eb9-2b7d-05bc-3035-a47f020861a8@linaro.org/Suggested-by:
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Nishanth Menon authored
Drop bootargs and add aliases based on base pinout of SK as per [1] and evm per [2]. Indices chosen attempt to maintain some level of consistency with existing aliases. While at this, drop a extra EoL. While this patch could be split, it seems trivial to add additional cleanup steps. [1] https://www.ti.com/lit/df/sprr432/sprr432.pdf [2] https://www.ti.com/lit/zip/swrr171Signed-off-by:
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Nishanth Menon authored
Hold the DDR vtt regulator active for functionality. Signed-off-by:
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